U.S. patent application number 16/104261 was filed with the patent office on 2019-02-21 for semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface.
The applicant listed for this patent is ATOMERA INCORPORATED. Invention is credited to SCOTT A. KREPS, ROBERT J. MEARS, KALIPATNAM VIVEK RAO, Robert John STEPHENSON.
Application Number | 20190058059 16/104261 |
Document ID | / |
Family ID | 63638321 |
Filed Date | 2019-02-21 |
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United States Patent
Application |
20190058059 |
Kind Code |
A1 |
STEPHENSON; Robert John ; et
al. |
February 21, 2019 |
SEMICONDUCTOR DEVICE INCLUDING NON-MONOCRYSTALLINE STRINGER
ADJACENT A SUPERLATTICE-STI INTERFACE
Abstract
A semiconductor device may include a semiconductor substrate and
first and second spaced apart shallow trench isolation (STI)
regions therein, and a superlattice on the semiconductor substrate
and extending between the first and second STI regions. The
superlattice may include stacked groups of layers, with each group
of layers including stacked base semiconductor monolayers defining
a base semiconductor portion, and at least one non-semiconductor
monolayer constrained within a crystal lattice of adjacent base
semiconductor portions. The semiconductor device may further
include a first semiconductor stringer including a
non-monocrystalline body at an interface between a first end of the
superlattice and the first STI region, and a gate above the
superlattice.
Inventors: |
STEPHENSON; Robert John;
(DUXFORD, GB) ; KREPS; SCOTT A.; (Indian Harbour
Beach, FL) ; MEARS; ROBERT J.; (WELLESLEY, MA)
; RAO; KALIPATNAM VIVEK; (GRAFTON, MA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
ATOMERA INCORPORATED |
LOS GATOS |
CA |
US |
|
|
Family ID: |
63638321 |
Appl. No.: |
16/104261 |
Filed: |
August 17, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62547417 |
Aug 18, 2017 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/1054 20130101;
H01L 29/15 20130101; H01L 29/7833 20130101; H01L 29/0607 20130101;
H01L 29/7782 20130101; H01L 29/1604 20130101; H01L 29/1083
20130101; H01L 21/3065 20130101; H01L 21/3083 20130101; H01L
21/823878 20130101; H01L 29/152 20130101; H01L 21/76237 20130101;
H01L 29/665 20130101; H01L 29/0649 20130101 |
International
Class: |
H01L 29/778 20060101
H01L029/778; H01L 29/06 20060101 H01L029/06; H01L 29/15 20060101
H01L029/15; H01L 29/16 20060101 H01L029/16 |
Claims
1. A semiconductor device comprising: a semiconductor substrate and
first and second spaced apart shallow trench isolation (STI)
regions therein; a superlattice on the semiconductor substrate and
extending between the first and second STI regions, the
superlattice comprising a plurality of stacked groups of layers,
each group of layers comprising a plurality of stacked base
semiconductor monolayers defining a base semiconductor portion, and
at least one non-semiconductor monolayer constrained within a
crystal lattice of adjacent base semiconductor portions; a first
semiconductor stringer comprising a non-monocrystalline body at an
interface between a first end of the superlattice and the first STI
region; and a gate above the superlattice.
2. The semiconductor device of claim 1 wherein the first
semiconductor stringer is above the superlattice.
3. The semiconductor device of claim 1 wherein the semiconductor
substrate and superlattice include dopants therein to define spaced
apart source and drain regions.
4. The semiconductor device of claim 1 further comprising a second
semiconductor stringer adjacent an interface between a second end
of the superlattice and the second STI region.
5. The semiconductor device of claim 1 wherein the first
semiconductor stringer separates the first end of the superlattice
and the first STI region.
6. The semiconductor device of claim 1 wherein the semiconductor
stringer comprises amorphous silicon.
7. The semiconductor device of claim 1 further comprising a channel
stop implant in the first semiconductor stringer.
8. The semiconductor device of claim 1 further comprising an oxide
cap on the first semiconductor stringer.
9. The semiconductor device of claim 1 wherein the base
semiconductor monolayers comprise silicon.
10. The semiconductor device of claim 1 wherein the at least one
non-semiconductor monolayer comprises oxygen.
11. A semiconductor device comprising: a semiconductor substrate
and first and second spaced apart shallow trench isolation (STI)
regions therein; a superlattice on the semiconductor substrate and
extending between the first and second STI regions, the
superlattice comprising a plurality of stacked groups of layers,
each group of layers comprising a plurality of stacked base
semiconductor monolayers defining a base semiconductor portion, and
at least one non-semiconductor monolayer constrained within a
crystal lattice of adjacent base semiconductor portions; a first
semiconductor stringer comprising a non-monocrystalline body at an
interface between a first end of the superlattice and the first STI
region; a second semiconductor stringer adjacent an interface
between a second end of the superlattice and the second STI region;
and a gate above the superlattice; the semiconductor substrate and
superlattice including dopants therein to define spaced apart
source and drain regions.
12. The semiconductor device of claim 11 wherein the first
semiconductor stringer is above the superlattice.
13. The semiconductor device of claim 11 wherein the second
semiconductor stringer separates the second end of the superlattice
and the second STI region.
14. The semiconductor device of claim 11 further comprising a
channel stop implant in the first and second semiconductor
stringers.
15. The semiconductor device of claim 11 further comprising an
oxide cap on the first semiconductor stringer.
16. The semiconductor device of claim 11 wherein the base
semiconductor monolayers comprise silicon.
17. The semiconductor device of claim 11 wherein the at least one
non-semiconductor monolayer comprises oxygen.
18. A semiconductor device comprising: a semiconductor substrate
and first and second spaced apart shallow trench isolation (STI)
regions therein; a superlattice on the semiconductor substrate and
extending between the first and second STI regions, the
superlattice comprising a plurality of stacked groups of layers,
each group of layers comprising a plurality of stacked base silicon
monolayers defining a base silicon portion, and at least one oxygen
monolayer constrained within a crystal lattice of adjacent base
silicon portions; a first semiconductor stringer comprising a
non-monocrystalline body at an interface between a first end of the
superlattice and the first STI region, the first semiconductor
stringer being above the superlattice; and a gate above the
superlattice.
19. The semiconductor device of claim 18 wherein the semiconductor
substrate and superlattice include dopants therein to define spaced
apart source and drain regions.
20. The semiconductor device of claim 18 further comprising a
second semiconductor stringer adjacent an interface between a
second end of the superlattice and the second STI region.
21. The semiconductor device of claim 20 wherein the second
semiconductor stringer separates the second end of the superlattice
and the second STI region.
22. The semiconductor device of claim 18 further comprising a
channel stop implant in the first semiconductor stringer.
23. The semiconductor device of claim 18 further comprising an
oxide cap on the first semiconductor stringer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. provisional
application No. 62/547,417 filed Aug. 18, 2017, which is hereby
incorporated herein in its entirety by reference.
TECHNICAL FIELD
[0002] The present invention relates to the field of
semiconductors, and, more particularly, to semiconductors having
enhanced properties based upon energy band engineering and
associated methods.
BACKGROUND
[0003] Structures and techniques have been proposed to enhance the
performance of semiconductor devices, such as by enhancing the
mobility of the charge carriers. For example, U.S. Patent
Application No. 2003/0057416 to Currie et al. discloses strained
material layers of silicon, silicon-germanium, and relaxed silicon
and also including impurity-free zones that would otherwise cause
performance degradation. The resulting biaxial strain in the upper
silicon layer alters the carrier mobilities enabling higher speed
and/or lower power devices. Published U.S. Patent Application No.
2003/0034529 to Fitzgerald et al. discloses a CMOS inverter also
based upon similar strained silicon technology.
[0004] U.S. Pat. No. 6,472,685 B2 to Takagi discloses a
semiconductor device including a silicon and carbon layer
sandwiched between silicon layers so that the conduction band and
valence band of the second silicon layer receive a tensile strain.
Electrons having a smaller effective mass, and which have been
induced by an electric field applied to the gate electrode, are
confined in the second silicon layer, thus, an n-channel MOSFET is
asserted to have a higher mobility.
[0005] U.S. Pat. No. 4,937,204 to Ishibashi et al. discloses a
superlattice in which a plurality of layers, less than eight
monolayers, and containing a fractional or binary or a binary
compound semiconductor layer, are alternately and epitaxially
grown. The direction of main current flow is perpendicular to the
layers of the superlattice.
[0006] U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si--Ge
short period superlattice with higher mobility achieved by reducing
alloy scattering in the superlattice. Along these lines, U.S. Pat.
No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET
including a channel layer comprising an alloy of silicon and a
second material substitutionally present in the silicon lattice at
a percentage that places the channel layer under tensile
stress.
[0007] U.S. Pat. No. 5,216,262 to Tsu discloses a quantum well
structure comprising two barrier regions and a thin epitaxially
grown semiconductor layer sandwiched between the barriers. Each
barrier region consists of alternate layers of SiO.sub.2/Si with a
thickness generally in a range of two to six monolayers. A much
thicker section of silicon is sandwiched between the barriers.
[0008] An article entitled "Phenomena in silicon nanostructure
devices" also to Tsu and published online Sep. 6, 2000 by Applied
Physics and Materials Science & Processing, pp. 391-402
discloses a semiconductor-atomic superlattice (SAS) of silicon and
oxygen. The Si/O superlattice is disclosed as useful in a silicon
quantum and light-emitting devices. In particular, a green
electroluminescence diode structure was constructed and tested.
Current flow in the diode structure is vertical, that is,
perpendicular to the layers of the SAS. The disclosed SAS may
include semiconductor layers separated by adsorbed species such as
oxygen atoms, and CO molecules. The silicon growth beyond the
adsorbed monolayer of oxygen is described as epitaxial with a
fairly low defect density. One SAS structure included a 1.1 nm
thick silicon portion that is about eight atomic layers of silicon,
and another structure had twice this thickness of silicon. An
article to Luo et al. entitled "Chemical Design of Direct-Gap
Light-Emitting Silicon" published in Physical Review Letters, Vol.
89, No. 7 (Aug. 12, 2002) further discusses the light emitting SAS
structures of Tsu.
[0009] U.S. Pat. No. 7,105,895 to Wang et al. discloses a barrier
building block of thin silicon and oxygen, carbon, nitrogen,
phosphorous, antimony, arsenic or hydrogen to thereby reduce
current flowing vertically through the lattice more than four
orders of magnitude. The insulating layer/barrier layer allows for
low defect epitaxial silicon to be deposited next to the insulating
layer.
[0010] Published Great Britain Patent Application 2,347,520 to
Mears et al. discloses that principles of Aperiodic Photonic
Band-Gap (APBG) structures may be adapted for electronic bandgap
engineering. In particular, the application discloses that material
parameters, for example, the location of band minima, effective
mass, etc., can be tailored to yield new aperiodic materials with
desirable band-structure characteristics. Other parameters, such as
electrical conductivity, thermal conductivity and dielectric
permittivity or magnetic permeability are disclosed as also
possible to be designed into the material.
[0011] Furthermore, U.S. Pat. No. 6,376,337 to Wang et al.
discloses a method for producing an insulating or barrier layer for
semiconductor devices which includes depositing a layer of silicon
and at least one additional element on the silicon substrate
whereby the deposited layer is substantially free of defects such
that epitaxial silicon substantially free of defects can be
deposited on the deposited layer. Alternatively, a monolayer of one
or more elements, preferably comprising oxygen, is absorbed on a
silicon substrate. A plurality of insulating layers sandwiched
between epitaxial silicon forms a barrier composite.
[0012] Despite the existence of such approaches, further
enhancements may be desirable for using advanced semiconductor
materials and processing techniques to achieve improved performance
in semiconductor devices.
SUMMARY
[0013] A semiconductor device may include a semiconductor substrate
and first and second spaced apart shallow trench isolation (STI)
regions therein, and a superlattice on the semiconductor substrate
and extending between the first and second STI regions. The
superlattice may include a plurality of stacked groups of layers,
with each group of layers comprising a plurality of stacked base
semiconductor monolayers defining a base semiconductor portion, and
at least one non-semiconductor monolayer constrained within a
crystal lattice of adjacent base semiconductor portions. The
semiconductor device may further include a first semiconductor
stringer including a non-monocrystalline body at an interface
between a first end of the superlattice and the first STI region,
and a gate above the superlattice.
[0014] More particularly, the first semiconductor stringer may be
above the superlattice. Furthermore, the substrate and superlattice
may include dopants therein to define spaced apart source and drain
regions. In some embodiments, the semiconductor device may further
include a second semiconductor stringer adjacent an interface
between a second end of the superlattice and the second STI region.
In one example implementation, the first semiconductor stringer may
separate the first end of the superlattice and the first STI
region.
[0015] In addition, the semiconductor stringer may comprise
amorphous silicon. The semiconductor device may further include a
channel stop implant in the first semiconductor stringer. The
semiconductor device may also include an oxide cap on the first
semiconductor stringer. By way of example, the base semiconductor
monolayers may comprise silicon, and the at least one
non-semiconductor monolayer may comprise oxygen.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a cross-sectional view of a semiconductor device
in accordance with the present invention including a
superlattice.
[0017] FIGS. 2A through 2D are cross-sectional views illustrating
formation of the semiconductor device of FIG. 1 and potential
difficulties associated therewith.
[0018] FIG. 3 is a top view of a portion of the semiconductor
device of FIG. 1 after gate electrode pattern and etch.
[0019] FIG. 4 is a flow diagram illustrating a process flow for
making the semiconductor device of FIG. 1.
[0020] FIGS. 5A and 5B are top views of NFET and PFET channel-stop
masks used in the method of FIG. 4.
[0021] FIGS. 6A through 6B are cross-sectional views illustrating
the masking and channel-stop implantation steps of the method of
FIG. 4.
[0022] FIG. 7 is a top view of the device structure after gate
electrode pattern and etch, showing the device regions where the
channel-stop implant is targeted to benefit, as part of the method
of FIG. 4.
[0023] FIGS. 8A through 8C are cross-sectional views illustrating
the resist stripping, gate doping, spacer formation, and
source/drain doping steps of the method of FIG. 4.
[0024] FIG. 9 is a flow diagram illustrating an alternative process
flow for making the semiconductor device of FIG. 1.
[0025] FIGS. 10A through 10B are cross-sectional views illustrating
the non-monocrystalline semiconductor etching, channel-stop
implant, and gate deposition/implantation steps of the method of
FIG. 9.
[0026] FIG. 11 is a top view of the device structure after the
spacer formation step of the method of FIG. 9.
[0027] FIGS. 12A and 12B are cross-sectional views of the device
structure after silicide formation taken parallel and perpendicular
to the gate layer, respectively.
[0028] FIGS. 13A and 13B are top views illustrating active area and
tab channel-stop masking steps in accordance with another
alternative process flow for making the semiconductor device of
FIG. 1.
[0029] FIG. 14 is a greatly enlarged schematic cross-sectional view
of the superlattice as shown in FIG. 1.
[0030] FIG. 15 is a perspective schematic atomic diagram of a
portion of the superlattice shown in FIG. 14.
[0031] FIG. 16 is a greatly enlarged schematic cross-sectional view
of another embodiment of a superlattice that may be used in the
device of FIG. 1.
[0032] FIG. 17A is a graph of the calculated band structure from
the gamma point (G) for both bulk silicon as in the prior art, and
for the 4/1 Si/O superlattice as shown in FIG. 14.
[0033] FIG. 17B is a graph of the calculated band structure from
the Z point for both bulk silicon as in the prior art, and for the
4/1 Si/O superlattice as shown in FIG. 14.
[0034] FIG. 17C is a graph of the calculated band structure from
both the gamma and Z points for both bulk silicon as in the prior
art, and for the 5/1/3/1 Si/O superlattice as shown in FIG. 16.
[0035] FIGS. 18-24 are a series of schematic cross-sectional
diagrams illustrating a method for performing maskless superlattice
deposition following STI formation in accordance an example
embodiment.
[0036] FIGS. 25-27 are a series of schematic cross-sectional
drawings illustrating an alternative embodiment for performing
maskless superlattice deposition following STI formation.
[0037] FIGS. 28A, 28B, 29-31, 32A, 32B, and 33-34 are a series of
schematic cross-sectional diagrams illustrating another alternative
embodiment for performing maskless superlattice deposition
following STI formation.
[0038] FIG. 35 is a table including dimensions associated with the
approach illustrated in FIGS. 28A, 28B, 29-31, 32A, 32B, and
33-34.
[0039] FIG. 36 is a flow diagram illustrating method aspects
associated with the approach illustrated in FIGS. 28A, 28B, 29-31,
32A, 32B, and 33-34.
DETAILED DESCRIPTION
[0040] The present invention will now be described more fully
hereinafter with reference to the accompanying drawings, in which
preferred embodiments of the invention are shown. This invention
may, however, be embodied in many different forms and should not be
construed as limited to the embodiments set forth herein. Rather,
these embodiments are provided so that this disclosure will be
thorough and complete, and will fully convey the scope of the
invention to those skilled in the art. Like numbers refer to like
elements throughout, and prime and multiple prime notation are used
to indicate similar elements in alternate embodiments.
[0041] The present embodiments relate to controlling the properties
of semiconductor materials at the atomic or molecular level to
achieve improved performance within semiconductor devices. Further,
the embodiments relate to the identification, creation, and use of
improved materials for use in the conduction paths of semiconductor
devices.
[0042] Applicants theorize, without wishing to be bound thereto,
that certain superlattices as described herein reduce the effective
mass of charge carriers and that this thereby leads to higher
charge carrier mobility. Effective mass is described with various
definitions in the literature. As a measure of the improvement in
effective mass Applicants use a "conductivity reciprocal effective
mass tensor", M.sub.e.sup.-1 and M.sub.h.sup.-1 for electrons and
holes respectively, defined as:
M e , ij - 1 ( E F , T ) = E > E F .intg. B . Z . ( .gradient. k
E ( k , n ) ) i ( .gradient. k E ( k , n ) ) j .differential. f ( E
( k , n ) , E F , T ) .differential. E d 3 k E > E F .intg. B .
Z . f ( E ( k , n ) , E F , T ) d 3 k ##EQU00001##
for electrons and:
M e , ij - 1 ( E F , T ) = - E < E F .intg. B . Z . ( .gradient.
k E ( k , n ) ) i ( .gradient. k E ( k , n ) ) j .differential. f (
E ( k , n ) , E F , T ) .differential. E d 3 k E < E F .intg. B
. Z . ( 1 - f ( E ( k , n ) , E F , T ) ) d 3 k ##EQU00002##
for holes, where f is the Fermi-Dirac distribution, E.sub.F is the
Fermi energy, T is the temperature (Kelvin), E(k,n) is the energy
of an electron in the state corresponding to wave vector k and the
n.sup.th energy band, the indices i and j refer to Cartesian
coordinates x, y and z, the integrals are taken over the Brillouin
zone (B.Z.), and the summations are taken over bands with energies
above and below the Fermi energy for electrons and holes
respectively.
[0043] Applicants' definition of the conductivity reciprocal
effective mass tensor is such that a tensorial component of the
conductivity of the material is greater for greater values of the
corresponding component of the conductivity reciprocal effective
mass tensor. Again Applicants theorize without wishing to be bound
thereto that the superlattices described herein set the values of
the conductivity reciprocal effective mass tensor so as to enhance
the conductive properties of the material, such as typically for a
preferred direction of charge carrier transport. The inverse of the
appropriate tensor element is referred to as the conductivity
effective mass. In other words, to characterize semiconductor
material structures, the conductivity effective mass for
electrons/holes as described above and calculated in the direction
of intended carrier transport is used to distinguish improved
materials.
[0044] Using the above-described measures, one can select materials
having improved band structures for specific purposes. One such
example would be a superlattice 25 material for a channel region in
a semiconductor device. A planar MOSFET 20 including the
superlattice 25 in accordance with the invention is now first
described with reference to FIG. 1. One skilled in the art,
however, will appreciate that the materials identified herein could
be used in many different types of semiconductor devices, such as
discrete devices and/or integrated circuits.
[0045] The illustrated MOSFET 20 includes a substrate 21 with
shallow trench isolation (STI) regions 80, 81 therein. More
particularly, the MOSFET device 20 may be a complementary MOS
(CMOS) device including N and P-channel transistors with respective
superlattice channels, in which the STI regions are for
electrically insulating adjacent transistors, as will be
appreciated by those skilled in the art. By way of example, the
substrate 21 may be a semiconductor (e.g., silicon) substrate or a
silicon-on-insulator (SOI) substrate. The STI regions 80, 81 may
include an oxide such as silicon dioxide, for example, although
other suitable materials may be used in other embodiments.
[0046] The MOSFET 20 further illustratively includes lightly doped
source/drain extension regions 22, 23, more heavily doped
source/drain regions 26, 27, and a channel region therebetween
provided by the superlattice 25. Halo implant regions 42, 43 are
illustratively included between the source and drain regions 26, 27
below the superlattice 25. Source/drain silicide layers 30, 31
overlie the source/drain regions, as will be appreciated by those
skilled in the art. A gate 35 illustratively includes a gate
dielectric layer 37 adjacent the channel provided by the
superlattice 25, and a gate electrode layer 36 on the gate
dielectric layer. Sidewall spacers 40, 41 are also provided in the
illustrated MOSFET 20, as well as a silicide layer 34 on the gate
electrode layer 36.
[0047] Process integration of the superlattice 25 into
state-of-the-art CMOS flow may require the removal of the
superlattice film 25 that is formed over the STI regions 80, 81 to
prevent shorting or leakage between adjacent device structures.
Referring more particularly to FIGS. 2A-2D through 3, fabrication
may begin with the substrate 21 which has the STI regions 80, 81
formed therein as well as a sacrificial oxide layer 85 thereon and
a V.sub.T implant 84 (represented by a row of "+" signs). In the
case of a crystalline silicon superlattice, which will be described
further below, when the sacrificial oxide layer 85 is removed and
the superlattice 25 is formed on the substrate 21, the silicon
deposition results in non-monocrystalline (i.e., polycrystalline or
amorphous) silicon deposits 86, 87 overlying the STI regions 80,
81. However, the non-monocrystalline silicon deposits 86, 87
typically need to be removed to prevent shorting or leakage between
adjacent device structures, as noted above.
[0048] While a relatively straightforward approach of performing
masking with a single baseline active area (AA) photoresist mask 88
(FIG. 2C) and subsequent etching of the non-monocrystalline silicon
deposits 86, 87 (FIG. 2D) may be acceptable in some
implementations, in other cases this can lead to certain
difficulties. More particularly, if the mask is misaligned
(resulting in a portion of the non-monocrystalline silicon deposit
86 on STI edges being masked by the photoresist 88) or due to
insufficient over-etch during plasma etch, then portions of the
non-monocrystalline silicon deposit on the STI edges and in the STI
divots may remain unetched and hence remain as a parasitic device
adjacent to the active device, while an active device area adjacent
the STI region (due to channel stop mask misalignment) is
inadvertently etched leaving a gap 89. The result is that dopant
creep may unintentionally occur adjacent the non-monocrystalline
silicon portion 86, while non-uniform silicide and source/drain
junction leakage substrate may occur adjacent the gap 89.
[0049] Accordingly, the masking and etching operations may
advantageously be modified to provide non-monocrystalline
semiconductor stringers or unetched tabs 82, 83 with channel-stop
implants in divots and edges of the STI regions 80, 81, as shown in
FIG. 1. Again, the non-monocrystalline semiconductor deposition
occurs during the epitaxial growth of the semiconductor monolayers
of the superlattice 25, which over the STI regions 80, 81 results
in a non-monocrystalline silicon. The non-monocrystalline stringers
82, 83 are preferably advantageously doped with a channel-stop
implant dopant, for example, as will be discussed further in the
various fabrication examples set forth below.
[0050] Referring more particularly to FIGS. 4 through 8, a first
process integration flow for making the semiconductor device 20 is
now described. Beginning with an STI wafer at Block 90, V.sub.T
wells are implanted (through 150 .ANG. pad oxide 85), at Block 91,
followed by a dry etch (120 .ANG. oxide), at Block 92. This is
followed by a hydrofluoric acid (HF) exposure (SC1/100:1, 50
.ANG.), at Block 93. In particular, the partial dry etch of the pad
oxide 85 and relatively short HF exposure time may help to reduce
the depth of the STI divots, for example. Next, the superlattice
film 25' is deposited, at Block 94, which will be discussed further
below, followed by a cleaning step (SPM/200:1, HF/RCA), at Block
95.
[0051] Rather than using a single baseline AA mask as described
above, in the present example a first, oversized N channel AA mask
is formed (FIGS. 5A and 6A), at Block 96, followed by a plasma etch
of the non-monocrystalline semiconductor material over the STI
regions adjacent the N-channel regions (Block 97) and an NFET
channel-stop implant (FIG. 9B) using the oversized N channel AA
mask, at Block 98. In FIGS. 8A and 8B, the N and P oversized masks
are indicated with reference numerals 88n' and 88p', respectively,
and the N and P active areas are indicated with reference numerals
21n', 21p', respectively. Moreover, reverse N and P wells are
indicated with reference numerals 79n' and 79p', respectively.
[0052] Next, an over-sized P-channel mask is then formed (FIG. 5B),
at Block 99, followed by a plasma etch of the non-monocrystalline
silicon over the STI regions adjacent the P-channel region (Block
100) and the PFET channel-stop implantation, at Block 101. The NFET
and PFET channel-stop implants are preferably performed at an angle
or tilt, such as a thirty degree angle, for example, as illustrated
in FIG. 6B, although other angles may also be used. The
channel-stop implantations are illustratively shown with arrows in
the drawings. By way of example, boron may be used for the NFET
channel-stop implant, and arsenic or phosphorous may be used for
the PFET channel-stop implant. The stringers 82', 83' in the STI
region 80', 81' divots and unetched silicon tabs at STI edges are
preferably highly counter-doped by the channel-stop implant to
neutralize or lessen the diffusion creep of dopants from
source-drain regions into the non-monocrystalline silicon in the
STI divots or tabs at the corner of the channel of the device to
advantageously provide a higher diode break down voltage, higher
threshold voltage and lower off current of this parasitic edge
device. The use of two different oversized masks for the P and N
channel devices advantageously helps protect the AA alignment marks
during the non-monocrystalline silicon etching, as well as to
protect each active device during channel stop implant of the
opposite type of device.
[0053] Once the PFET channel-stop implants are completed, a
pre-gate clean (SPM/HF/RCA) is performed, at Block 102 (FIG. 8A),
followed by gate oxide 37' formation (approximately 20 .ANG.), at
Block 103, and non-monocrystalline silicon gate electrode 36
deposition and implantation doping, at Block 104 (FIG. 8B). Gate
patterning and etching is then performed, at Block 105, followed by
sidewall spacer 40', 41' formation (e.g., 100 .ANG. oxide) (Block
106) and LDD 22', 23 and halo 42', 43' implantations, at Block 107
(FIG. 8C). The spacers 40', 41' are then etched (e.g., 1900 .ANG.
oxide), at Block 108. The spacer 40, 41 formation is followed by
the source/drain 26', 27' implants and annealing (e.g.,
1000.degree. C. for 10 seconds), at Block 109, and silicide
formation (Block 110) to provide the device 20 shown in FIG. 1.
More particularly, the silicide may be TiSi.sub.2 (e.g., Ti
deposition, germanium implant, RTA @ 690.degree. C., selective
strip, followed by RTA at 750.degree. C.).
[0054] FIGS. 12A and 12B are cross-sectional views of the device
structure after silicide formation taken parallel and perpendicular
to the gate layer 36', respectively. In these figures, the
non-monocrystalline stringers 82', 83' are shown with stippling to
indicate that they have been doped with the channel-stop implant.
It should be noted that the depth of the silicon recess in the
source/drain areas will depend upon the amount of over-etch used to
remove the non-monocrystalline stringers and unetched tabs (due to
use of oversized active-area channel-stop masks) 82', 83' in the
STI divots and STI edges. Moreover, excessive recesses may lead to
increased series RSD or loss of contact between the source/drain
and the LDD regions, as will be appreciated by those skilled in the
art. As such, these depths may require adjustment depending upon
the given implantation.
[0055] In the above-noted process flow, the NFET and PFET masking,
etching of the non-monocrystalline silicon 86', 87' over the STI
regions 80', 81', and channel-stop implants are performed prior to
gate oxidation. In an alternative process flow now described with
reference to FIGS. 9 through 11, the above-described approach is
modified so that etching of the non-monocrystalline silicon 86',
87' is performed after the spacer etching step (Block 108').
Moreover, this alternative process flow also uses an oxide or
nitride cap film 78'' (FIG. 10B) over the gate electrode layer 36''
to protect the gate polysilicon from being etched during the
etching of the non-monocrystalline silicon 86'', 87''.
[0056] After dry etching (Block 92'), a cleaning step (SPM/200:1,
HF (50 .ANG.)/RCA) is performed, at Block 120', followed by an HF
pre-clean (100:1) for approximately one minute. For the NFET and
PFET masking deposition steps (Blocks 96', 99'), in the present
example oversized hybrid photoresist masks are used (FIG. 10A).
Additionally, after the non-monocrystalline silicon gate electrode
layer 36'' deposition (Block 104'), the illustrated method includes
an NSD masking step (Block 122'), followed by an N+ gate implant
and cap oxide deposition, at Blocks 123', 124'. Other process
variations from the above-described approach include an etching of
the non-monocrystalline silicon 86'', 87'' on the STI regions 80'',
81'' (e.g., 300 .ANG.), at Block 125', followed by etching of the
cap oxide layer (with a high selectivity to silicon), at Block
126'. Those remaining process steps not specifically discussed here
are similar to those discussed above with reference to FIG. 4.
[0057] Yet another alternative process flow will now be described
with reference to FIGS. 13A and 13B. This process flow uses a
common oversized AA mask for etching the non-monocrystalline
silicon 86''', 87''' on the STI regions 80''', 81''', followed by
two separate masking steps for patterning tab openings. More
particularly, an NFET channel-stop mask 130n''' and a PFET
channel-stop mask 130p''' are used (FIG. 13B). The NFET and PFET
masking steps are followed by channel-stop implantation steps to
dope the non-monocrystalline silicon in the tab openings. The
foregoing steps may be performed prior to gate oxidation.
[0058] It will be appreciated that the exemplary process flows
outlined above advantageously allow the etching of the
non-monocrystalline semiconductor material on the STI regions prior
to gate oxide growth. In addition, the channel-stop implants with
appropriate energy and dose would electrically neutralize dopant
diffusion from adjacent source and drain regions into any unetched
superlattice stringers inadvertently hiding in recessed STI divots
at active area edges or tabs of the non-monocrystalline silicon on
the STI oxide, surrounding the active area due to the over-sized
active-area mask. Of course, it will be appreciated that other
suitable materials and process flow parameters besides the
exemplary ones noted above may be used in different
implementations.
[0059] Improved materials or structures for the channel region of
the MOSFET 20 having energy band structures for which the
appropriate conductivity effective masses for electrons and/or
holes are substantially less than the corresponding values for
silicon will now be described. Referring now additionally to FIGS.
14 and 15, the superlattice 25 has a structure that is controlled
at the atomic or molecular level and may be formed using known
techniques of atomic or molecular layer deposition. The
superlattice 25 includes a plurality of layer groups 45a-45n
arranged in stacked relation, as noted above, as perhaps best
understood with specific reference to the schematic cross-sectional
view of FIG. 14.
[0060] Each group of layers 45a-45n of the superlattice 25
illustratively includes a plurality of stacked base semiconductor
monolayers 46 defining a respective base semiconductor portion
46a-46n and an energy band-modifying layer 50 thereon. The energy
band-modifying layers 50 are indicated by stippling in FIG. 14 for
clarity of illustration.
[0061] The energy-band modifying layer 50 illustratively includes
one non-semiconductor monolayer constrained within a crystal
lattice of adjacent base semiconductor portions. That is, opposing
base semiconductor monolayers 46 in adjacent groups of layers
45a-45n are chemically bound together. For example, in the case of
silicon monolayers 46, some of the silicon atoms in the upper or
top semiconductor monolayer of the group of monolayers 46a will be
covalently bonded with silicon atoms in the lower or bottom
monolayer of the group 46b. This allows the crystal lattice to
continue through the groups of layers despite the presence of the
non-semiconductor monolayer(s) (e.g., oxygen monolayer(s)). Of
course, there will not be a complete or pure covalent bond between
the opposing silicon layers 46 of adjacent groups 45a-45n as some
of the silicon atoms in each of these layers will be bonded to
non-semiconductor atoms (i.e., oxygen in the present example), as
will be appreciated by those skilled in the art.
[0062] In other embodiments, more than one non-semiconductor layer
monolayer may be possible. By way of example, the number of
non-semiconductor monolayers in the energy band-modifying layer 50
may preferably be less than about five monolayers to thereby
provide desired energy band-modifying properties.
[0063] It should be noted that reference herein to a
non-semiconductor or semiconductor monolayer means that the
material used for the monolayer would be a non-semiconductor or
semiconductor if formed in bulk. That is, a single monolayer of a
material, such as semiconductor, may not necessarily exhibit the
same properties that it would if formed in bulk or in a relatively
thick layer, as will be appreciated by those skilled in the
art.
[0064] Applicants theorize without wishing to be bound thereto that
energy band-modifying layers 50 and adjacent base semiconductor
portions 46a-46n cause the superlattice 25 to have a lower
appropriate conductivity effective mass for the charge carriers in
the parallel layer direction than would otherwise be present.
Considered another way, this parallel direction is orthogonal to
the stacking direction. The band modifying layers 50 may also cause
the superlattice 25 to have a common energy band structure, while
also advantageously functioning as an insulator between layers or
regions vertically above and below the superlattice. Moreover, as
noted above, this structure also advantageously provides a barrier
to dopant and/or material bleed or diffusion and to carrier flow
between layers vertically above and below the superlattice 25.
[0065] It is also theorized that the superlattice 25 provides a
higher charge carrier mobility based upon the lower conductivity
effective mass than would otherwise be present. Of course, all of
the above-described properties of the superlattice 25 need not be
utilized in every application. For example, in some applications
the superlattice 25 may only be used for its dopant
blocking/insulation properties or its enhanced mobility, or it may
be used for both in other applications, as will be appreciated by
those skilled in the art.
[0066] A cap layer 52 is on an upper layer group 45n of the
superlattice 25. The cap layer 52 may comprise a plurality of base
semiconductor monolayers 46. The cap layer 52 may have between 2 to
100 monolayers of the base semiconductor, and, more preferably
between 10 to 50 monolayers. Other thicknesses may be used as
well.
[0067] Each base semiconductor portion 46a-46n may comprise a base
semiconductor selected from the group consisting of Group IV
semiconductors, Group III-V semiconductors, and Group II-VI
semiconductors. Of course, the term Group IV semiconductors also
includes Group IV-IV semiconductors, as will be appreciated by
those skilled in the art. More particularly, the base semiconductor
may comprise at least one of silicon and germanium, for
example.
[0068] Each energy band-modifying layer 50 may comprise a
non-semiconductor selected from the group consisting of oxygen,
nitrogen, fluorine, and carbon-oxygen, for example. The
non-semiconductor is also desirably thermally stable through
deposition of a next layer to thereby facilitate manufacturing. In
other embodiments, the non-semiconductor may be another inorganic
or organic element or compound that is compatible with the given
semiconductor processing, as will be appreciated by those skilled
in the art.
[0069] It should be noted that the term "monolayer" is meant to
include a single atomic layer and also a single molecular layer. It
is also noted that the energy band-modifying layer 50 provided by a
single monolayer is also meant to include a monolayer wherein not
all of the possible sites are occupied. For example, with
particular reference to the atomic diagram of FIG. 15, a 4/1
repeating structure is illustrated for silicon as the base
semiconductor material, and oxygen as the energy band-modifying
material. Only half of the possible sites for oxygen are
occupied.
[0070] In other embodiments and/or with different materials this
one half occupation would not necessarily be the case as will be
appreciated by those skilled in the art. Indeed it can be seen even
in this schematic diagram, that individual atoms of oxygen in a
given monolayer are not precisely aligned along a flat plane as
will also be appreciated by those of skill in the art of atomic
deposition. By way of example, a preferred occupation range is from
about one-eighth to one-half of the possible oxygen sites being
full, although other numbers may be used in certain
embodiments.
[0071] Silicon and oxygen are currently widely used in conventional
semiconductor processing, and, hence, manufacturers will be readily
able to use these materials as described herein. Atomic or
monolayer deposition is also now widely used. Accordingly,
semiconductor devices incorporating the superlattice 25 in
accordance with the invention may be readily adopted and
implemented, as will be appreciated by those skilled in the
art.
[0072] It is theorized without wishing to be bound thereto, that
for a superlattice, such as the Si/O superlattice, for example,
that the number of silicon monolayers should desirably be seven or
less so that the energy band of the superlattice is common or
relatively uniform throughout to achieve the desired advantages.
The 4/1 repeating structure shown in FIGS. 14 and 15, for Si/O has
been modeled to indicate an enhanced mobility for electrons and
holes in the X direction. For example, the calculated conductivity
effective mass for electrons (isotropic for bulk silicon) is 0.26
and for the 4/1 SiO superlattice in the X direction it is 0.12
resulting in a ratio of 0.46. Similarly, the calculation for holes
yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O
superlattice resulting in a ratio of 0.44.
[0073] While such a directionally preferential feature may be
desired in certain semiconductor devices, other devices may benefit
from a more uniform increase in mobility in any direction parallel
to the groups of layers. It may also be beneficial to have an
increased mobility for both electrons and holes, or just one of
these types of charge carriers, as will be appreciated by those
skilled in the art. It may also be beneficial to have a decreased
carrier mobility in a direction perpendicular to the groups of
layers.
[0074] The lower conductivity effective mass for the 4/1 Si/O
embodiment of the superlattice 25 may be less than two-thirds the
conductivity effective mass than would otherwise occur, and this
applies for both electrons and holes. It may be especially
appropriate to dope some portion of the superlattice 25 in some
embodiments, particularly when the superlattice is to provide a
portion of a channel as in the device 20, for example. In other
embodiments, it may be preferably to have one or more groups of
layers 45 of the superlattice 25 substantially undoped depending
upon its position within the device.
[0075] Referring now additionally to FIG. 16, another embodiment of
a superlattice 25' in accordance with the invention having
different properties is now described. In this embodiment, a
repeating pattern of 3/1/5/1 is illustrated. More particularly, the
lowest base semiconductor portion 46a' has three monolayers, and
the second lowest base semiconductor portion 46b' has five
monolayers. This pattern repeats throughout the superlattice 25'.
The energy band-modifying layers 50' may each include a single
monolayer. For such a superlattice 25' including Si/O, the
enhancement of charge carrier mobility is independent of
orientation in the plane of the layers. Those other elements of
FIG. 16 not specifically mentioned are similar to those discussed
above with reference to FIG. 14 and need no further discussion
herein.
[0076] In some device embodiments, all of the base semiconductor
portions 46a-46n of a superlattice 25 may be a same number of
monolayers thick. In other embodiments, at least some of the base
semiconductor portions 46a-46n may be a different number of
monolayers thick. In still other embodiments, all of the base
semiconductor portions 46a-46n may be a different number of
monolayers thick.
[0077] In FIGS. 17A-17C band structures calculated using Density
Functional Theory (DFT) are presented. It is well known in the art
that DFT underestimates the absolute value of the bandgap. Hence
all bands above the gap may be shifted by an appropriate "scissors
correction." However the shape of the band is known to be much more
reliable. The vertical energy axes should be interpreted in this
light.
[0078] FIG. 17A shows the calculated band structure from the gamma
point (G) for both bulk silicon (represented by continuous lines)
and for the 4/1 Si/O superlattice 25 as shown in FIG. 14
(represented by dotted lines). The directions refer to the unit
cell of the 4/1 Si/O structure and not to the conventional unit
cell of Si, although the (001) direction in the figure does
correspond to the (001) direction of the conventional unit cell of
Si, and, hence, shows the expected location of the Si conduction
band minimum. The (100) and (010) directions in the figure
correspond to the (110) and (-110) directions of the conventional
Si unit cell. Those skilled in the art will appreciate that the
bands of Si on the figure are folded to represent them on the
appropriate reciprocal lattice directions for the 4/1 Si/O
structure.
[0079] It can be seen that the conduction band minimum for the 4/1
Si/O structure is located at the gamma point in contrast to bulk
silicon (Si), whereas the valence band minimum occurs at the edge
of the Brillouin zone in the (001) direction which we refer to as
the Z point. One may also note the greater curvature of the
conduction band minimum for the 4/1 Si/O structure compared to the
curvature of the conduction band minimum for Si owing to the band
splitting due to the perturbation introduced by the additional
oxygen layer.
[0080] FIG. 17B shows the calculated band structure from the Z
point for both bulk silicon (continuous lines) and for the 4/1 Si/O
superlattice 25 (dotted lines) of FIG. 14. This figure illustrates
the enhanced curvature of the valence band in the (100)
direction.
[0081] FIG. 17C shows the calculated band structure from both the
gamma and Z point for both bulk silicon (continuous lines) and for
the 5/1/3/1 Si/O structure of the superlattice 25' of FIG. 16
(dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure,
the calculated band structures in the (100) and (010) directions
are equivalent. Thus the conductivity effective mass and mobility
are expected to be isotropic in the plane parallel to the layers,
i.e. perpendicular to the (001) stacking direction. Note that in
the 5/1/3/1 Si/O example the conduction band minimum and the
valence band maximum are both at or close to the Z point.
[0082] Although increased curvature is an indication of reduced
effective mass, the appropriate comparison and discrimination may
be made via the conductivity reciprocal effective mass tensor
calculation. This leads Applicants to further theorize that the
5/1/3/1 superlattice 25' should be substantially direct bandgap. As
will be understood by those skilled in the art, the appropriate
matrix element for optical transition is another indicator of the
distinction between direct and indirect bandgap behavior.
[0083] Referring now additionally to FIGS. 18-24, a method of
maskless superlattice deposition on a substrate 200 after formation
of STI structures 201 is now described. As shown in FIG. 18, a
slightly thicker nitride stop layer 203 is formed over an oxide
layer 202 on the substrate 200, and adjacent portions of the oxide
filled STI region 201, which is left after a CMP step. More
particularly, the remaining STI portion 201 may have a thickness X
of about 450 .ANG. or more, as opposed to a conventional thickness
of about 200 .ANG.. This additional thickness is such as to leave
sufficient space for formation of a superlattice 225 and a
protective oxide 204 thereon as described further below. The oxide
layer 202, covers the substrate 200 beneath the nitride layer 203,
and generally should be thick enough to serve as a CMP stop (e.g.,
greater than 150 .ANG. thick, and more particularly greater than
200 .ANG. thick). Those of skill in the art will appreciate the
appropriate technique to set the CMP stop point to form the
slightly thicker nitride layer 203.
[0084] The oxide layer 202 and nitride layer 203 may then be
stripped off of the substrate 200, and the superlattice layer 225
formed thereover as shown in FIG. 19. Additionally, the protective
oxide layer 204 may be thermally grown or deposited over the
superlattice layer 225.
[0085] As shown in FIGS. 20 and 21, a nitride layer 205 may be
deposited over the structure to a thickness of about 450 .ANG., for
example. This nitride layer 205 may be planarized to the oxide
layer 204 by CMP as shown in FIG. 21. Some dishing or pitting may
occur during CMP as shown, but this will not affect the process as
will be appreciated by those skilled in the art.
[0086] As shown in FIG. 22, a plasma etch, for example, may be used
to remove the superlattice layer 225 and oxide layer 204 on top of
the STI structure 201. Indeed, the prior CMP step may also be used
to remove all or some of the superlattice layer 225 and oxide layer
204 on the STI structure 201 in some implementations.
[0087] The exposed edge of the superlattice layer 225 may be
re-oxidized to form an oxide cap 206, producing the intermediate
structure shown in FIG. 23. In accordance with one example
approach, a wet etch of the silicon stringer or "whisker" 207
(e.g., target under-etch) may be performed, followed by a wet
oxidation. Thereafter, the remaining portion of the nitride layer
205 may be removed by wet etching, for example, leaving the
structure as shown in FIG. 24. The manufacturing process may
continue with implanting through the oxide, etc., as will be
appreciated by those skilled in the art. If desired, the remaining
superlattice film stringer 207 on the edge of the STI structure 201
may be removed by subjecting it to a smoothing anneal after removal
of the hard oxide mask, as will also be appreciated by those
skilled in the art.
[0088] An alternative to the CMP step described above with respect
to FIG. 21 is to re-use the STI photoresist mask 210' and wet etch
the nitride 205', as shown in FIG. 25. In this case, the
photoresist mask 210' may be removed and a plasma etch used to
expose the original STI 201', as indicated by the dashed line 211'
in FIG. 26. This will result in the removal of the stringer 207
discussed above, as well underlying portions of the substrate 200'
and adjacent portions of the superlattice 225' and oxide layer 204'
as represented by the "registration error" shown in FIG. 27. The
exposed silicon (i.e., the substrate 200' and end of the
superlattice 225') may then be re-oxidized to form an oxide layer
212', followed by a wet strip of the nitride layer 205' and
subsequent processing. A deglazing may also be performed to etch
off the oxide layer 212' as well.
[0089] Referring to FIGS. 28-34, the table 350 of FIG. 35, and the
flow diagram 360 of FIG. 36, another post-STI superlattice
integration scheme is now described. Initial processing steps may
include an STI module (Block 361) to form the STI regions 201'' in
the substrate 200'', followed by a deep well implant 213'' and
threshold voltage (V.sub.T) implants 214'' (Block 362) through a
pad oxide (e.g., 150 .ANG. pad oxide). Further initial processing
steps may include a dry etch of the oxide (e.g., 120 .ANG.), at
Block 363, a sulfuric/peroxide mixture (SPM)/RCA clean (Block 364),
an SC1/HF pre-clean (Block 365), superlattice 225'' deposition
(Block 366), and an incoming clean, at Block 367.
[0090] The method further illustratively includes forming a thin
oxide/nitride hard mask 215'' over the superlattice 225'', along
with an undersized reverse active area (AA) photoresist mask 211'',
as shown in FIGS. 28A-28B. Portions of the superlattice 225''
outside of the photoresist mask 211'' may then be etched away,
e.g., using a plasma etch (Block 370), and the photoresist mask may
then be stripped away, at Block 371, as seen in FIG. 29. The amount
of over-etch to clear the amorphous film on the STI region 201''
may be set to zero, as the subsequent ring oxidation step will
convert unmasked residual superlattice 225'' silicon to oxide.
[0091] An active area ring oxide 216'' may then be formed
surrounding the AA region, at Block 372 (see FIG. 30), followed by
stripping of the oxide/nitride hard mask 215'' (Block 373), a
pre-gate clean (Block 374), and gate dielectric 217'' formation
(e.g., 20 .ANG.), at Block 375 (see FIG. 31). A step height between
the gate dielectric layer 217'' and the top of the STI region 201''
is set by the conditions of the masked oxidation step, amount of
pre-gate clean, and initial STI protrusion/recess. A polysilicon
gate electrode layer 218'' may then be formed, at Block 376 (see
FIGS. 32A, 32B), followed by N+/P+ polysilicon masking and N+/P+
gate implantation (Blocks 377-380). FIG. 32A is a cross-sectional
view perpendicular to the gate, while FIG. 32B is a cross-sectional
view along the gate at the edge of the STI region 201''.
[0092] The method may further include a hard mask CVD oxide
deposition, at Block 381, gate patterning and etching (Block 382),
and spacer 219'' formation (e.g., 125 .ANG. oxide), at Block 383.
Halo implants 221'' and source/drain extension implants 220'' may
then be formed, at Block 384 (see FIG. 33), followed by nitride or
oxide spacer 222'' formation (Block 385), which may optionally be
performed if the notch depth at the edge of the STI region 201'' is
excessive. The superlattice 225'' may optionally be etched in the
source/drain regions if necessary, at Block 386, followed by a
screen oxide formation (Block 387) and source/drain implant 223''
formation, at Block 388.
[0093] Further processing steps illustratively includes a wet etch
of the cap oxide (Block 389), an RTA/spike anneal (Block 400), and
a silicide module 401 to form source/drain and gate silicide
regions 226'', 227'' (see FIG. 34). More particularly, FIG. 34 is a
cross-sectional view taken perpendicular to the gate and showing
the edge of the STI region 201'', in which the dashed arrow
represents a smaller silicide-to-junction distance due to the
present approach (.about.355 .ANG. smaller), as will be discussed
further below.
[0094] Care may be taken to avoid the notch depth at the STI 201''
edge, which may otherwise potentially result in a source/drain
junction-to-well short (vertical). This should not be as much of a
concern vertically, although the diagonal angle may be the biggest
risk after silicide formation. Generally speaking, the junction is
assumed to be .about.1000 .ANG.. Moreover, care may be taken to
avoid silicide in the notch area shorting underneath the gate (from
source-to-drain underneath the thick oxide region). Dopant
diffusion under the gate from source-to-drain may advantageously be
reduced.
[0095] The table 350 (FIG. 35) includes exemplary surface locations
relative to the original surface for the above-described approach,
although it will be appreciated that different dimensions may be
used in different embodiments. As noted above, the net result in
the present example is an approximate 355 A (vertical) thinning in
the source/drain surface-to-junction position along the STI 201''
edge using this approach.
[0096] The above-described approach advantageously produces a
relatively thick oxide under the gate at the STI edge. Moreover,
this approach may also be exploited in a dual gate process, as the
dual gate step may be used for the oxidized ring step above.
Benefits of this approach may be that it allows for the avoidance
of the amorphous silicon tab when desired, avoidance of CS
implants, and the potential for fewer superlattice 225'' film
etches (i.e., one instead of two if the superlattice film is left
in the source/drain regions).
[0097] This application is related to copending patent application
entitled, "METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING
NON-MONOCRYSTALLINE STRINGER ADJACENT A SUPERLATTICE-STI
INTERFACE," which is filed on the same date and by the same
assignee and inventors, the disclosure which is hereby incorporated
by reference.
[0098] Many modifications and other embodiments will come to the
mind of one skilled in the art having the benefit of the teachings
presented in the foregoing descriptions and the associated
drawings. Therefore, it is understood that such modifications and
embodiments are intended to be included within the scope of the
appended claims.
* * * * *