U.S. patent application number 15/642349 was filed with the patent office on 2019-01-10 for semiconductor structure.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Chun-Hung Chen, Teng-Chuan Hu, Chung-Hsing Kuo, Chu-Fu Lin, Ming-Tse Lin, Chun-Ting Yeh.
Application Number | 20190013259 15/642349 |
Document ID | / |
Family ID | 64903458 |
Filed Date | 2019-01-10 |
United States Patent
Application |
20190013259 |
Kind Code |
A1 |
Hu; Teng-Chuan ; et
al. |
January 10, 2019 |
SEMICONDUCTOR STRUCTURE
Abstract
A semiconductor structure includes a substrate having a
frontside surface and a backside surface. A through-substrate via
extends into the substrate from the frontside surface. The
through-substrate via comprises a top surface. A metal cap covers
the top surface of the through-substrate via. A plurality of
cylindrical dielectric plugs is embedded in the metal cap. The
cylindrical dielectric plugs are distributed only within a central
area of the metal cap. The central area is not greater than a
surface area of the top surface of the through-substrate via.
Inventors: |
Hu; Teng-Chuan; (Tainan
City, TW) ; Chen; Chun-Hung; (Tainan City, TW)
; Lin; Chu-Fu; (Kaohsiung City, TW) ; Yeh;
Chun-Ting; (Taipei City, TW) ; Kuo; Chung-Hsing;
(Taipei City, TW) ; Lin; Ming-Tse; (Hsinchu City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
64903458 |
Appl. No.: |
15/642349 |
Filed: |
July 6, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/528 20130101;
H01L 21/7685 20130101; H01L 21/76898 20130101; H01L 21/76831
20130101; H01L 21/3212 20130101; H01L 23/53238 20130101; H01L
23/481 20130101; H01L 21/7684 20130101; H01L 23/522 20130101 |
International
Class: |
H01L 23/48 20060101
H01L023/48; H01L 23/528 20060101 H01L023/528; H01L 21/768 20060101
H01L021/768; H01L 23/532 20060101 H01L023/532 |
Claims
1. A semiconductor structure, comprising: a substrate having a
frontside surface and a backside surface; a through-substrate via
extending into the substrate from the frontside surface, wherein
the through-substrate via comprises a top surface; a metal cap
covering the top surface of the through-substrate via; and a
plurality of cylindrical dielectric plugs embedded in the metal
cap, wherein the cylindrical dielectric plugs are distributed only
within a central area of the metal cap, and wherein the central
area is not greater than a surface area of the top surface of the
through-substrate via, wherein the metal cap is made of metallic
material and is of a perforated screen structure with a plurality
of rectangular openings filled by dielectric material, and wherein
all of the cylindrical dielectric plugs are surrounded by the metal
cap material.
2. The semiconductor structure according to claim 1 further
comprising a plurality of circuit elements disposed on the
frontside surface.
3. The semiconductor structure according to claim 2 further
comprising an inter-layer dielectric (ILD) layer covering the
plurality of circuit elements.
4. The semiconductor structure according to claim 3, wherein the
through-substrate via penetrates through the ILD layer.
5. The semiconductor structure according to claim 3, wherein the
top surface of the through-substrate via is a flat top surface and
is flush with a top surface of the ILD layer.
6. The semiconductor structure according to claim 5, wherein the
metal cap is embedded in a first inter-metal dielectric (IMD) layer
on the ILD layer.
7. The semiconductor structure according to claim 6 further
comprising a second inter-metal dielectric (IMD) layer on the first
IMD layer and on the metal cap.
8. The semiconductor structure according to claim 7 further
comprising an interconnection structure in the second IMD layer,
wherein the interconnection structure is electrically connected to
the metal cap through a conductive via in the second IMD layer.
9. The semiconductor structure according to claim 1, wherein the
metal cap has a rectangular outline.
10. The semiconductor structure according to claim 9, wherein the
metal cap has a dimension of about 7 .mu.m.times.7 .mu.m.
11. The semiconductor structure according to claim 1, wherein the
plurality of cylindrical dielectric plugs is arranged within the
central area of the metal cap in a staggered manner.
12. A semiconductor structure, comprising: a substrate having a
frontside surface and a backside surface; a through-substrate via
extending into the substrate from the frontside surface, wherein
the through-substrate via comprises a top surface; a metal cap
covering the top surface of the through-substrate via; a plurality
of first cylindrical dielectric plugs embedded in the metal cap and
distributed within a central area of the metal cap; and a plurality
of second cylindrical dielectric plugs embedded in the metal cap
and distributed within a peripheral area outside the central area
of the metal cap, wherein the metal cap is made of metallic
material and is of a perforated screen structure with a plurality
of rectangular openings filled by dielectric material.
13. The semiconductor structure according to claim 12, wherein a
dimension of each of the first cylindrical dielectric plugs is
smaller than that of each of the second cylindrical dielectric
plugs.
14. The semiconductor structure according to claim 13, wherein the
dimension of each of the first cylindrical dielectric plugs ranges
between 0.13 .mu.m and 0.25 .mu.m.
15. The semiconductor structure according to claim 13, wherein the
dimension of each of the second cylindrical dielectric plugs ranges
between 0.13 .mu.m and 0.25 .mu.m.
16. The semiconductor structure according to claim 12, wherein the
metal cap has a rectangular outline.
17. The semiconductor structure according to claim 16, wherein the
metal cap has a dimension of about 7 .mu.m.times.7 .mu.m.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The present invention relates generally to the field of
semiconductor technology. More particularly, the present invention
relates to an improved metal cap structure over a
through-substrate-via (TSV).
2. Description of the Prior Art
[0002] Three-dimensional (3D) packaging technology has been
developed to enable vertical integration of multiple semiconductor
chips. The 3D packaging technology may employ wafer-level package
technology, in which the stacked substrates may be full wafers
typically having integrated circuits fabricated thereon. The 3D
stacked wafers can be diced into individual units after wafer
bonding, each unit having two or more chips vertically bonded
together through through-substrate vias (TSVs).
[0003] The TSVs are usually made by forming vertical through holes
in a semiconductor wafer and filling the through holes with
insulating materials and metallic materials. Copper is a preferable
interconnect material for TSVs due to its high conductivity and
lower specific resistance, which may reduce the interconnect
resistance to achieve faster operation of a device.
[0004] However, conventional Cu TSV structures may suffer serious
Cu protrusion issues. The Cu protrusion of the TSV may lower the
flatness of the substrate and affect the following manufacturing
processes. To reduce Cu protrusion, a metal cap is typically formed
on the TSV. However, Cu dishing effect may occur when forming the
large-area metal cap on the TSV.
SUMMARY OF THE INVENTION
[0005] In view of the foregoing, embodiments of the invention
provide an improved metal cap structure over a
through-substrate-via (TSV).
[0006] According to one as aspect of the invention, a semiconductor
structure is disclosed. The semiconductor structure includes a
substrate having a frontside surface and a backside surface. A
through-substrate via extends into the substrate from the frontside
surface. The through-substrate via comprises a top surface. A metal
cap covers the top surface of the through-substrate via. A
plurality of cylindrical dielectric plugs is embedded in the metal
cap. The cylindrical dielectric plugs are distributed only within a
central area of the metal cap. The central area is not greater than
a surface area of the top surface of the through-substrate via.
[0007] According to one as aspect of the invention, a semiconductor
structure is disclosed. The semiconductor structure includes a
substrate having a frontside surface and a backside surface. A
through-substrate via extends into the substrate from the frontside
surface. The through-substrate via comprises a top surface. A metal
cap covers the top surface of the through-substrate via. A
plurality of first cylindrical dielectric plugs is embedded in the
metal cap and distributed within a central area of the metal cap. A
plurality of second cylindrical dielectric plugs is embedded in the
metal cap and distributed within a peripheral area outside the
central area of the metal cap.
[0008] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a schematic, top view of a semiconductor structure
according to one embodiment of the invention.
[0010] FIG. 2 is a schematic, cross-sectional view taken along line
I-I' in FIG. 1.
[0011] FIG. 3 is a schematic, top view showing the shape of each
cylindrical dielectric plug in the metal cap according to another
embodiment of the invention.
[0012] FIG. 4 is a schematic, top view showing the layout of the
cylindrical dielectric plugs in the metal cap according to another
embodiment of the invention.
DETAILED DESCRIPTION
[0013] The present invention has been particularly shown and
described with respect to certain embodiments and specific features
thereof. The embodiments set forth herein below are to be taken as
illustrative rather than limiting. It should be readily apparent to
those of ordinary skill in the art that various changes and
modifications in form and detail may be made without departing from
the spirit and scope of the invention.
[0014] Before the further description of the preferred embodiment,
the specific terms used throughout the text will be described
below.
[0015] The term "etch" is used herein to describe the process of
patterning a material layer so that at least a portion of the
material layer after etching is retained. For example, it is to be
understood that the method of etching silicon involves patterning a
mask layer (e.g., photoresist or hard mask) over silicon and then
removing silicon from the area that is not protected by the mask
layer. Thus, during the etching process, the silicon protected by
the area of the mask will remain.
[0016] In another example, however, the term "etch" may also refer
to a method that does not use a mask, but leaves at least a portion
of the material layer after the etch process is complete. The above
description is used to distinguish between "etching" and "removal".
When "etching" a material layer, at least a portion of the material
layer is retained after the end of the treatment. In contrast, when
the material layer is "removed", substantially all the material
layer is removed in the process. However, in some embodiments,
"removal" is considered to be a broad term and may include
etching.
[0017] The terms "forming", "depositing" or the term "disposing"
are used hereinafter to describe the behavior of applying a layer
of material to the substrate. Such terms are intended to describe
any possible layer forming techniques including, but not limited
to, thermal growth, sputtering, evaporation, chemical vapor
deposition, epitaxial growth, electroplating, and the like.
[0018] According to various embodiments, for example, deposition
may be carried out in any suitable known manner. For example,
deposition may include any growth, plating, or transfer of material
onto the substrate. Some known techniques include physical vapor
deposition (PVD), chemical vapor deposition (CVD), electrochemical
deposition (ECD), molecular beam epitaxy (MBE), atomic layer
deposition (ALD), and plasma enhanced CVD (PECVD).
[0019] The term "substrate" described in the text is commonly
referred to as a silicon substrate. However, the substrate may also
be any semiconductor material, such as germanium, gallium arsenide,
indium phosphide and the like. In other embodiments, the substrate
may be non-conductive, such as glass or sapphire wafers.
[0020] Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic,
top view of a semiconductor structure according to one embodiment
of the invention. FIG. 2 is a schematic, cross-sectional view taken
along line I-I' in FIG. 1.
[0021] As shown in FIG. 1 and FIG. 2, the semiconductor structure 1
comprises a substrate 10 such as a silicon substrate, but is not
limited thereto. The substrate 10 has a frontside surface 10a and a
backside surface 10b. A plurality of circuit elements 101 are
formed on the frontside surface 10a. For example, the plurality of
circuit elements 101 may comprise field effect transistors or
memory cells, but is not limited thereto.
[0022] An inter-layer dielectric (ILD) layer 110 is deposited on
the frontside surface 10a. The ILD layer 110 covers the plurality
of circuit elements 101. For example, the ILD layer 110 may
comprises silicon oxide, silicon nitride, BPSG, PSG, or low-k
dielectric materials, but is not limited thereto. The ILD layer 110
has a top surface 110a.
[0023] A through-substrate via (TSV) 12 extends into the substrate
10 from the frontside surface 10a. According to the embodiment of
the invention, the through-substrate via 12 penetrates through the
ILD layer 110. The through-substrate via 12 comprises a top surface
12a. The top surface 12a of the through-substrate via 12 is a flat
top surface and is flush with the top surface 110a of the ILD layer
110. It is understood that multiple TSVs may be formed in the
substrate 10 although only one TSV is shown in the figures.
[0024] According to the embodiment of the invention, the
through-substrate via 12 may comprise an insulating layer 121 such
as a silicon oxide layer, and a conductive layer 122 such as a
copper layer. The insulating layer 121 insulates the conductive
layer 122 from the substrate 10.
[0025] A metal cap 20 is situated directly on the top surface 12a
of the through-substrate via 12. The metal cap 20 covers the top
surface 12a of the through-substrate via 12. According to the
embodiment of the invention, the metal cap 20 is embedded in a
first inter-metal dielectric (IMD) layer 130 on the ILD layer
110.
[0026] According to the embodiment of the invention, the metal cap
20 is fabricated by using a copper damascene process. According to
the embodiment of the invention, the metal cap 20 comprises a
diffusion barrier metal layer 201 and a copper layer 202. For
example, the metal cap 20 is fabricated in the first metal level or
M.sub.1.
[0027] According to the embodiment of the invention, the metal cap
20 may have a rectangular outline. For example, the metal cap 20
may have a dimension of about 7 .mu.m.times.7 .mu.m. The metal cap
20 is typically used to prevent copper extrusion of the
through-substrate via 12. However, the metal cap 20 is prone to
dishing during the chemical mechanical polishing (CMP) process. The
present invention addresses this issue.
[0028] To cope with the copper dishing effect, a plurality of
cylindrical dielectric plugs 230 is embedded in the metal cap 20.
The cylindrical dielectric plugs 230 are distributed only within a
central area 300 of the metal cap 20, where the copper dishing
would mostly likely to occur. The cylindrical dielectric plugs 230
and the first inter-metal dielectric (IMD) layer 130 are composed
of the same dielectric layer. Each of the cylindrical dielectric
plugs 230 is isolated and is not in direct contact with the
surrounding first inter-metal dielectric (IMD) layer 130.
[0029] As can be best seen in FIG. 1, the plurality of cylindrical
dielectric plugs 230 is arranged only within the central area 300
of the metal cap 20 in a staggered manner. According to the
embodiment of the invention, the central area 300 is not greater
than the surface area 12a of the top surface of the
through-substrate via 12.
[0030] By disposing the cylindrical dielectric plugs 230 within the
central area 300 of the metal cap 20 in a staggered manner, the
copper dishing effect is avoided or alleviated.
[0031] According to one embodiment, each of the cylindrical
dielectric plugs 230 may have a rectangular outline when viewed
from the above, as shown in FIG. 1. However, it is understood that,
in another embodiment, each of the cylindrical dielectric plugs 230
may have other shapes, for example, a circular-shaped cylindrical
dielectric plug 230', as shown in FIG. 3.
[0032] As shown in FIG. 2, a second inter-metal dielectric (IMD)
layer 140 may be deposited on the first IMD layer 130 and on the
metal cap 20. According to the embodiment of the invention, prior
to the deposition of the second IMD layer 140, an etch stop layer
132 may be deposited on the first IMD layer 130 and on the metal
cap 20.
[0033] An interconnection structure 240 may be formed in the second
IMD layer 140. The interconnection structure 240 may be
electrically connected to the metal cap 20 through a conductive via
240a in the second IMD layer 140. The interconnection structure 240
may be formed by using a copper dual damascene process, but is not
limited thereto. For example, the interconnection structure 240 may
be formed in the second metal layer M.sub.2 and via layer
V.sub.1.
[0034] FIG. 4 is a schematic, top view showing the layout of the
cylindrical dielectric plugs in the metal cap according to another
embodiment of the invention, wherein like numeral numbers designate
like regions, layers, or elements.
[0035] As shown in FIG. 4, likewise, a through-substrate via 12
extends into the substrate 10 from the frontside surface 10a. The
through-substrate via 12 comprises a top surface 12a. A metal cap
20 covers the top surface 12a of the through-substrate via 12.
[0036] A plurality of first cylindrical dielectric plugs 230a is
embedded in the metal cap 20 and is distributed within a central
area 300 of the metal cap 20. A plurality of second cylindrical
dielectric plugs 230b is embedded in the metal cap 20 and is
distributed within a peripheral area 300p outside the central area
300 of the metal cap 20.
[0037] According to one embodiment, the metal cap 20 has a
rectangular outline. For example, the metal cap 20 may have a
dimension of about 7 .mu.m.times.7 .mu.m.
[0038] According to one embodiment, a dimension of each of the
first cylindrical dielectric plugs 230a is smaller than that of
each of the second cylindrical dielectric plugs 230b. According to
one embodiment, the dimension of each of the first cylindrical
dielectric plugs 230a ranges between 0.13 .mu.m and 0.25 .mu.m.
According to one embodiment, the dimension of each of the second
cylindrical dielectric plugs 230b ranges between 0.13 .mu.m and
0.25 .mu.m.
[0039] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *