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LIN; Chu-Fu Patent Filings

LIN; Chu-Fu

Patent Applications and Registrations

Patent applications and USPTO patent grants for LIN; Chu-Fu.The latest application filed is for "capacitor structure and method for manufacturing the same".

Company Profile
9.15.21
  • LIN; Chu-Fu - Kaohsiung City TW
  • Lin; Chu-Fu - Kaohsiung TW
  • Lin; Chu Fu - Yongkang City TW
  • Lin; Chu-Fu - YongKang TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Capacitor Structure And Method For Manufacturing The Same
App 20220208958 - HU; Teng-Chuan ;   et al.
2022-06-30
Semiconductor Package Structure
App 20210005559 - Chen; Chun-Hung ;   et al.
2021-01-07
Semiconductor package structure
Grant 10,886,241 - Chen , et al. January 5, 2
2021-01-05
Semiconductor package structure and method for forming the same
Grant 10,818,616 - Chen , et al. October 27, 2
2020-10-27
Method For Fabricating Semiconductor Device
App 20200243386 - LIN; CHU-FU ;   et al.
2020-07-30
Through-silicon via structure
Grant 10,504,821 - Lin , et al. Dec
2019-12-10
Semiconductor Package Structure And Method For Forming The Same
App 20190221528 - Chen; Chun-Hung ;   et al.
2019-07-18
Semiconductor package structure and method for forming the same
Grant 10,340,231 - Chen , et al.
2019-07-02
Semiconductor structure
Grant 10,192,808 - Hu , et al. Ja
2019-01-29
Semiconductor Structure
App 20190013259 - Hu; Teng-Chuan ;   et al.
2019-01-10
Semiconductor Package Structure And Method For Forming The Same
App 20180269167 - Chen; Chun-Hung ;   et al.
2018-09-20
Through-silicon Via Structure
App 20170221796 - Lin; Chu-Fu ;   et al.
2017-08-03
Method of forming chip with through silicon via electrode
Grant 9,437,491 - Lin , et al. September 6, 2
2016-09-06
Fan-out Wafer Level Package
App 20160064300 - Lin; Chu-Fu ;   et al.
2016-03-03
Fan-out wafer level package
Grant 9,269,645 - Lin , et al. February 23, 2
2016-02-23
Method Of Forming Chip With Through Silicon Via Electrode
App 20150311117 - Lin; Ming-Tse ;   et al.
2015-10-29
Chip with through silicon via electrode and method of forming the same
Grant 9,123,789 - Lin , et al. September 1, 2
2015-09-01
Substrate with integrated passive devices and method of manufacturing the same
Grant 9,035,457 - Lin , et al. May 19, 2
2015-05-19
Anti-fuse structure and programming method thereof
Grant 8,884,398 - Lin , et al. November 11, 2
2014-11-11
Anti-fuse Structure And Programming Method Thereof
App 20140291801 - Lin; Chu-Fu ;   et al.
2014-10-02
Chip With Through Silicon Via Electrode And Method Of Forming The Same
App 20140203394 - Lin; Ming-Tse ;   et al.
2014-07-24
Substrate With Integrated Passive Devices And Method Of Manufacturing The Same
App 20140145326 - Lin; Chu-Fu ;   et al.
2014-05-29
Wafer Edge Trimming Method
App 20140113452 - LIN; Chu-Fu ;   et al.
2014-04-24
Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer
Grant 8,674,507 - Chou , et al. March 18, 2
2014-03-18
Chip structure with bumps and testing pads
Grant 7,977,803 - Kuo , et al. July 12, 2
2011-07-12
Chip Structure With Bumps And Testing Pads
App 20110049515 - Kuo; Nick ;   et al.
2011-03-03
Chip structure with bumps and testing pads
Grant 7,855,461 - Kuo , et al. December 21, 2
2010-12-21
Centrifugal driving electricity generation system for energy conservation
App 20090146427 - Lin; Chu Fu
2009-06-11
Method For Dicing Wafer
App 20090137097 - Lin; Chu-Fu ;   et al.
2009-05-28
Chip structure with bumps and testing pads
App 20080224326 - Kuo; Nick ;   et al.
2008-09-18
Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
Grant 7,394,161 - Kuo , et al. July 1, 2
2008-07-01
Counter weight flywheel
App 20080083298 - Lin; Chu-Fu
2008-04-10
Energy-saving Environmentally Friendly Generating System
App 20060237969 - Lin; Chu-Fu
2006-10-26
Chip structure with bumps and testing pads
App 20050121804 - Kuo, Nick ;   et al.
2005-06-09
Water level processing method and structure to manufacture two kinds of bumps, gold and solder, on one wafer
App 20050017355 - Chou, Chien-Kang ;   et al.
2005-01-27

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