U.S. patent application number 17/023967 was filed with the patent office on 2021-01-07 for semiconductor package structure.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Chun-Hung Chen, Chu-Fu Lin, Ming-Tse Lin.
Application Number | 20210005559 17/023967 |
Document ID | / |
Family ID | |
Filed Date | 2021-01-07 |
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United States Patent
Application |
20210005559 |
Kind Code |
A1 |
Chen; Chun-Hung ; et
al. |
January 7, 2021 |
SEMICONDUCTOR PACKAGE STRUCTURE
Abstract
A semiconductor package structure and a method for forming the
same are disclosed. The semiconductor package structure includes a
semiconductor die, a molding layer and an inductor. The
semiconductor die includes an active surface, a back surface and a
sidewall surface between the active surface and the back surface.
The molding layer covers the back surface and the sidewall surface
of the semiconductor die. The inductor is in the molding layer. The
sidewall surface of the semiconductor die faces toward the
inductor.
Inventors: |
Chen; Chun-Hung; (Tainan
City, TW) ; Lin; Chu-Fu; (Kaohsiung City, TW)
; Lin; Ming-Tse; (Hsinchu City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsinchu |
|
TW |
|
|
Appl. No.: |
17/023967 |
Filed: |
September 17, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16361880 |
Mar 22, 2019 |
10818616 |
|
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17023967 |
|
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|
15486521 |
Apr 13, 2017 |
10340231 |
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16361880 |
|
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Current U.S.
Class: |
1/1 |
International
Class: |
H01L 23/64 20060101
H01L023/64; H01L 23/31 20060101 H01L023/31 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 15, 2017 |
TW |
106108470 |
Claims
1. A semiconductor package structure, comprising: a molding layer
having a first molding surface and a second molding surface
opposing to the first molding surface; a semiconductor die having
an active surface and being embedded in the molding layer, wherein
the active surface of the semiconductor die has a contact pad
therein; an inductor extending through the molding layer from the
first molding surface to the second molding surface of the molding
layer, wherein a lower surface of the molding layer is coplanar
with a lower surface of the inductor, and wherein an upper surface
of the contact pad is coplanar with an upper surface of the
inductor; and a redistribution layer extending from the active
surface of the semiconductor die and the second molding surface of
the molding layer in a direction away from the first molding
surface of the molding layer, wherein a layout region of the
redistribution layer and a layout region of the inductor are
overlapping, and wherein a layout pattern of the inductor and a
layout pattern of the semiconductor die are non-overlapping.
2. The semiconductor package structure of claim 1, wherein a
pattern of the inductor surrounds the semiconductor die.
3. The semiconductor package structure of claim 1, wherein a
pattern of the inductor is disposed outside of the semiconductor
die.
4. The semiconductor package structure of claim 1, wherein the
layout region of the redistribution layer is larger than a layout
region of the semiconductor die.
5. The semiconductor package structure of claim 1, wherein the
inductor is electrically connected to the semiconductor die through
the redistribution layer and the contact pad.
6. The semiconductor package structure of claim 1, wherein the
upper surface of the contact pad is coplanar with the active
surface of the semiconductor die.
7. The semiconductor package structure of claim 1, wherein the
semiconductor die comprises a logic IC die or a power IC die.
8. The semiconductor package structure of claim 1, wherein the
molding layer comprises epoxy, polyimide, phenolic or silicone.
9. The semiconductor package structure of claim 1, wherein the
inductor is adjoined with the molding layer.
10. The semiconductor package structure of claim 1, wherein the
inductor has a thickness larger than a gap distance between the
active surface and a back surface of the semiconductor die.
11. The semiconductor package structure of claim 1, wherein a
thickness of the inductor is equal to a thickness of the molding
layer.
12. The semiconductor package structure of claim 1, wherein the
molding layer adjoined with the inductor is adjoined with both a
sidewall surface and a back surface of the semiconductor die.
Description
[0001] The application is a continuation application of U.S. patent
application Ser. No. 16/361,880, filed on Mar. 22, 2019, which is a
divisional application of U.S. application Ser. No. 15/486,521,
filed on Apr. 13, 2017, and claims the benefit of Taiwan
application Serial No. 106108470, filed on Mar. 15, 2017, the
subject matter of which is incorporated herein by reference.
BACKGROUND
Technical Field
[0002] The disclosure relates to a semiconductor package structure
and a method for forming the same, and more particularly to a
semiconductor package structure having an inductor and a method for
forming the same.
Description of the Related Art
[0003] A semiconductor package structure usually has a
semiconductor die comprising an active element and a passive
element such as an inductor disposed over the semiconductor die.
However, the inductor occupies and limits a layout region for a
redistribution layer electrically connected to the semiconductor
die. On the other hand, an inductance performance of the inductor
is limited due to the redistribution layer. A trade-off between the
layout regions for the elements is difficult. In addition, the
semiconductor die would be affected by a crosstalk from the
inductor.
SUMMARY
[0004] The present disclosure provides a semiconductor package
structure and a method for forming the same.
[0005] According to a concept of the present disclosure, a
semiconductor package structure is provided. The semiconductor
package structure comprises a semiconductor die, a molding layer
and an inductor. The semiconductor die comprises an active surface,
a back surface and a sidewall surface between the active surface
and the back surface. The molding layer covers the back surface and
the sidewall surface of the semiconductor die. The inductor is in
the molding layer. The sidewall surface of the semiconductor die
faces toward the inductor.
[0006] According to another concept of the present disclosure, a
semiconductor package structure is disclosed. The semiconductor
package structure comprises a molding layer, a semiconductor die,
an inductor, and a redistribution layer. The molding layer has a
first molding surface and a second molding surface opposing to the
first molding surface. The semiconductor die has an active surface
and is embedded in the molding layer. The inductor extends through
the molding layer from the first molding surface to the second
molding surface of the molding layer. The redistribution layer
extends from the active surface of the semiconductor die and the
second molding surface of the molding layer in a direction away
from the first molding surface of the molding layer.
[0007] According to yet another concept of the present disclosure,
a method for forming a semiconductor package structure is
disclosed. The method comprises the following steps. A molding
layer is formed to cover a semiconductor die. The molding layer has
a first molding surface and a second molding surface opposing to
the first molding surface. An inductor is formed to pass through
the molding layer from the first molding surface to the second
molding surface of the molding layer and is juxtaposed to a
sidewall surface of the semiconductor die.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 illustrates a cross-section view of a semiconductor
package structure according to an embodiment.
[0009] FIG. 2 illustrates a top view showing a molding layer, a
semiconductor die, and an inductor according to an embodiment.
[0010] FIG. 3 illustrates a top view showing a molding layer, a
semiconductor die, and an inductor according to another
embodiment.
[0011] FIG. 4 to FIG. 8 illustrate a manufacturing method for a
semiconductor package structure according to an embodiment.
[0012] In the following detailed description, for purposes of
explanation, numerous specific details are set forth in order to
provide a thorough understanding of the disclosed embodiments. It
will be apparent, however, that one or more embodiments may be
practiced without these specific details. In other instances,
well-known structures and devices are schematically shown in order
to simplify the drawing.
DETAILED DESCRIPTION
[0013] In embodiments, an inductor and a semiconductor die are
respectively disposed in non-overlapping regions of a molding
layer. Therefore, the inductor can have a big size to provide a
strong inductance performance, and the semiconductor die will not
be affected by a crosstalk from the inductor. In addition, the
redistribution layer is disposed in a level different from a level
where the inductor is formed, and thus the redistribution layer can
be arranged without considering a region area for the inductor, and
can have more layout flexibility.
[0014] Embodiments are provided hereinafter with reference to the
accompanying drawings for describing the related procedures and
configurations. It is noted that not all embodiments of the
invention are shown. The identical and/or similar elements of the
embodiments are designated with the same and/or similar reference
numerals. Also, it is noted that there may be other embodiments of
the present disclosure which are not specifically illustrated.
Modifications and variations can be made without departing from the
spirit of the disclosure to meet the requirements of the practical
applications. It is also important to point out that the
illustrations may not be necessarily be drawn to scale. Thus, the
specification and the drawings are to be regard as an illustrative
sense rather than a restrictive sense.
[0015] FIG. 1 illustrates a cross-section view of a semiconductor
package structure according to an embodiment. The semiconductor
package structure may comprise a semiconductor die 102, a molding
layer 104, an inductor 106 and a redistribution layer (RDL) 108.
The semiconductor die 102 has an active surface 110A, a back
surface 1108 opposing to the active surface 110A, and a sidewall
surface 110S between the active surface 110A and the back surface
1108. The active surface 110A may have a contact pad 112 thereon or
therein. The molding layer 104 covers the back surface 1108 and the
sidewall surface 110S of the semiconductor die 102.
[0016] In embodiments, the semiconductor die 102 and the inductor
106 are disposed in non-overlapping regions of the molding layer
104, respectively. As shown in FIG. 1, the inductor 106 is disposed
in the molding layer 104 on the sidewall surface 110S of the
semiconductor die 102. Thus the semiconductor die 102 will not be
affected by a crosstalk from the inductor 106. In addition, the
inductor 106 can be designed to have a layout capable of generating
a strong inductor performance. In an embodiment, for example, the
inductor 106 has a thickness bigger than a thickness of the
semiconductor die 102. The thickness of the semiconductor die 102
may be defined as a gap distance between the active surface 110A
and the back surface 1108. In an embodiment, the thickness of the
inductor 106 may be substantially equal to a thickness of the
molding layer 104. For example, the thickness of the molding layer
104 may be defined as a gap distance between a first molding
surface 114 and a second molding surface 116 opposing to the first
molding surface 114 of the molding layer 104. The inductor 106 may
extend between the first molding surface 114 and the second molding
surface 116 of the molding layer 104.
[0017] In embodiments, the inductor 106 can be arranged into an
arbitrary pattern relating to the semiconductor die 102. For
example, referring to FIG. 2 illustrating a top view of the
semiconductor die 102 and the inductor 106 in the molding layer 104
according to an embodiment, the inductor 106 has a spiral pattern
surrounding the semiconductor die 102. Alternatively, referring to
FIG. 3 illustrating a top view of the semiconductor die 102 and the
inductor 106 in the molding layer 104 according to an another
embodiment, the whole spiral pattern of the inductor 106 is
disposed outside of the semiconductor die 102. In other
embodiments, the inductor 106 may be designed with arbitrary
quantity or shape in a suitable region according to actual demand.
For example, the inductor 106 may have a circular spiral pattern,
an oval-shaped spiral pattern, a rectangular spiral pattern, a
hexagonal spiral pattern, an irregular-shaped spiral pattern, or
other suitable shapes.
[0018] Referring to FIG. 1, the redistribution layer 108 may be
disposed in an insulating layer 118 on the active surface 110A of
the semiconductor die 102 and the second molding surface 116 of the
molding layer 104. The redistribution layer 108 may be electrically
connected to the contact pad 112 of the semiconductor die 102. The
redistribution layer 108 may be electrically connected to the
inductor 106. For example, the redistribution layer 108 may be used
to electrically connect the semiconductor die 102 to the inductor
106 and electrically connect elements such as active devices formed
in the semiconductor die 102. The redistribution layer 108 also
have a contact end exposed on an upper surface 119 of the
insulating layer 118 and providing an electrical connection point
for an external device.
[0019] As shown in FIG. 1, the redistribution layer 108 and the
inductor 106 are disposed on and under the second molding surface
116 of the molding layer 104, respectively. Therefore, the
redistribution layer 108 can be arranged without considering the
inductor 106, and can have more layout flexibility. In an
embodiment, for example, the redistribution layer 108 may be
disposed in a layout region overlapping a layout region for the
inductor 106. In an embodiment, the redistribution layer 108 has a
layout region larger than a layout region for the semiconductor die
102, and has a fan-out arrangement.
[0020] In an embodiment, a solder material 120, such as a solder
ball, may be disposed on the contact end of the redistribution
layer 108 according to actual demand.
[0021] The semiconductor package structure may be manufactured by a
method comprising a process flow as shown in FIG. 4 to FIG. 8 and
FIG. 1 according to an embodiment.
[0022] Referring to FIG. 4, the semiconductor die 102 may be
disposed on a carrier 224 with an adhesive layer 222 therebetween
with the active surface 110A facing toward the carrier 224.
[0023] In an embodiment, for example, the semiconductor die 102 is
a die formed by forming various IC elements on a front surface of a
wafer as a semiconductor substrate by a semiconductor integrated
circuit (IC) process, and then dicing the wafer finally. In other
words, the sidewall surface 110S of the semiconductor die 102 may
be a cut surface formed by cutting along a scribe line of the
wafer. In embodiments, the semiconductor die 102 may be referred to
as a semiconductor IC die. In an embodiment, for example, the
semiconductor die 102 may comprise a logic IC die, a power IC die,
etc.
[0024] For example, FIG. 5 shows a cross-section view of the
semiconductor die 102. An IC manufacturing process may be performed
to form an active element 230 on a front substrate surface 228
opposing to the back surface 1108 of a semiconductor substrate 226.
For example, the active element 230 may comprise a MOS comprising a
source S, a drain D and a gate G. In addition, an interconnect
element 234 passing through a dielectric layer 232 is formed to
electrically connect to the active element 230 and the contact pad
112 exposed by the dielectric layer 232. The interconnect element
234 may comprise at least one contact via, a plurality of
conductive lines formed in interlayer/inter-metal dielectric films
of the dielectric layer 232, a contact plug, etc. Finally, the
wafer is diced into the semiconductor die 102.
[0025] Referring to FIG. 6, the molding layer 104 is formed to
cover the back surface 1108 and the sidewall surface 110S of the
semiconductor die 102. The carrier 224 may be covered by the
molding layer 104. For example, the molding layer 104 may comprise
epoxy, polyimide (PI), phenolic, silicone, or a combination
thereof.
[0026] Referring to FIG. 7, a portion of the molding layer 104 on
the sidewall surface 110S of the semiconductor die 102 is removed
to form a through hole 236. The through hole 236 for example has a
pattern for inductor when viewed in a top view such as the inductor
pattern shown in FIG. 2 or FIG. 3. For example, the molding layer
104 may be removed from the first molding surface 114 by a laser
method until the carrier 224 is exposed.
[0027] Referring to FIG. 8, next, the carrier 224 is removed. A
conductive layer 238 may be filled in the through hole 236 to form
the inductor 106 by an electrodeless plating method. However, the
present disclosure is not limited thereto. In other embodiments,
the conductive layer 238 may be formed in the through hole 236 by
other suitable methods. The carrier 224 may be removed after
forming the conductive layer 238. For example, the conductive layer
238 may comprise copper or other suitable conductive materials.
[0028] Referring to FIG. 8, the redistribution layer 108 is formed.
The redistribution layer 108 may extend from the active surface
110A of the semiconductor die 102 and the inductor 106 onto the
second molding surface 116 of the molding layer 104. The
redistribution layer 108 may extend from the active surface 110A of
the semiconductor die 102, the inductor 106 and the second molding
surface 116 of the molding layer 104, passing through the
insulating layer 118, and arranged on the upper surface 119 of the
insulating layer 118. The redistribution layer 108 may have a
contact end exposed by the upper surface 119 of the insulating
layer 118 and provided for an external device.
[0029] Referring to FIG. 1, in an embodiment, the solder material
120, such as a solder ball or other suitable contact structures,
may be disposed on the contact end of the redistribution layer 108
according to actual demand.
[0030] Accordingly, in embodiments, the inductor and the
semiconductor die are respectively disposed in non-overlapping
regions of the molding layer. Therefore, the inductor can have a
big size to provide a strong inductance performance, and the
semiconductor die will not be affected by a crosstalk from the
inductor. In addition, the redistribution layer is disposed in a
level different from a level where the inductor is formed, and thus
the redistribution layer can be arranged without considering a
region area for the inductor, and can have more layout
flexibility.
[0031] While the disclosure has been described by way of example
and in terms of the exemplary embodiment(s), it is to be understood
that the disclosure is not limited thereto. On the contrary, it is
intended to cover various modifications and similar arrangements
and procedures, and the scope of the appended claims therefore
should be accorded the broadest interpretation so as to encompass
all such modifications and similar arrangements and procedures.
* * * * *