U.S. patent application number 15/992223 was filed with the patent office on 2018-09-27 for manufacturing method of semiconductor device and semiconductor manufacturing apparatus.
This patent application is currently assigned to Toshiba Memory Corporation. The applicant listed for this patent is Toshiba Memory Corporation. Invention is credited to Akifumi GAWASE, Takahiko KAWASAKI, Yukiteru MATSUI, Kyoichi SUGURO.
Application Number | 20180277388 15/992223 |
Document ID | / |
Family ID | 55167297 |
Filed Date | 2018-09-27 |
United States Patent
Application |
20180277388 |
Kind Code |
A1 |
MATSUI; Yukiteru ; et
al. |
September 27, 2018 |
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR
MANUFACTURING APPARATUS
Abstract
A manufacturing method of a semiconductor device according to an
embodiment implants impurities into a central portion of a
polishing target film or an outer peripheral portion of the central
portion of the polishing target film to cause an impurity
concentration in the outer peripheral portion of the polishing
target film and an impurity concentration in the central portion
thereof to be different from each other, thereby modifying a
surface of the polishing target film. The modified surface of the
polishing target film is polished by a CMP method.
Inventors: |
MATSUI; Yukiteru; (Nagoya,
JP) ; SUGURO; Kyoichi; (Yokohama, JP) ;
GAWASE; Akifumi; (Kuwana, JP) ; KAWASAKI;
Takahiko; (Nagoya, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Toshiba Memory Corporation |
Tokyo |
|
JP |
|
|
Assignee: |
Toshiba Memory Corporation
Tokyo
JP
|
Family ID: |
55167297 |
Appl. No.: |
15/992223 |
Filed: |
May 30, 2018 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14643218 |
Mar 10, 2015 |
10008390 |
|
|
15992223 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
B81C 2201/0123 20130101;
H01L 21/30625 20130101; H01L 21/32115 20130101; H01L 21/31053
20130101; H01L 21/3215 20130101; H01L 21/304 20130101; H01J
2237/31711 20130101; H01L 21/3212 20130101; H01L 21/31155 20130101;
B81C 2201/0125 20130101; H01J 37/3171 20130101 |
International
Class: |
H01L 21/3115 20060101
H01L021/3115; H01L 21/3215 20060101 H01L021/3215; H01L 21/3105
20060101 H01L021/3105; H01J 37/317 20060101 H01J037/317; H01L
21/321 20060101 H01L021/321; H01L 21/306 20060101 H01L021/306; H01L
21/304 20060101 H01L021/304 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 25, 2014 |
JP |
2014-152285 |
Claims
1-11. (canceled)
12. A semiconductor manufacturing apparatus comprising: an
irradiator irradiating an ion beam to a central portion of a target
film formed on a wafer or an outer peripheral portion of the
central portion of the target film to cause an impurity
concentration in the outer peripheral portion of the target film
and an impurity concentration in the central portion thereof to be
different from each other; and an ion beam mask partially covering
the target film in order to shield a part of the ion beam from the
irradiator.
13. The apparatus of claim 12, wherein the ion beam mask comprises
a first ion beam mask covering the outer peripheral portion of the
target film, and the irradiator irradiates an ion beam containing
F, B, or N to the target film through the first ion beam mask.
14. The apparatus of claim 12, wherein the ion beam mask comprises
a second ion beam mask covering the central portion of the target
film, and the irradiator irradiates an ion beam containing C, N, or
Si to the target film through the second ion beam mask.
15. The apparatus of claim 12, wherein the ion beam mask comprises
a first ion beam mask covering the outer peripheral portion of the
target film, and a second ion beam mask covering the central
portion of the target film, the irradiator irradiates an ion beam
containing F, B, or N to the target film through the first ion beam
mask in order to increase a polishing rate of the target film, and
the irradiator irradiates an ion beam containing C, N, or Si to the
target film through the second ion beam mask in order to decrease a
polishing rate of the target film.
16. The apparatus of claim 12, wherein the irradiator irradiates an
ion beam containing F, B, or N to the target film a plurality of
times at a plurality of acceleration energies different from each
other.
17.-18. (canceled)
19. The apparatus of claim 12, wherein the ion beam mask blocks the
ion beam irradiated to a chip area of the target film and allows
the ion beam irradiated to an outer peripheral portion outside of
the chip area, patterns are formed in the chip area and not formed
in the outer peripheral portion.
20. A semiconductor manufacturing apparatus comprising: an
irradiator irradiating an ion beam to a central portion of a target
film formed on a wafer or an outer peripheral portion of the
central portion of the target film to cause an impurity
concentration in the outer peripheral portion of the target film
and an impurity concentration in the central portion thereof to be
different from each other; and an ion beam mask partially covering
the target film in order to shield a part of the ion beam from the
irradiator, wherein the ion beam mask comprises a first ion beam
mask covering the outer peripheral portion of the target film, and
a second ion beam mask covering the central portion of the target
film, the irradiator irradiates an ion beam containing a first-type
dopant to the target film through the first ion beam mask in order
to increase a polishing rate of the target film, and the irradiator
irradiates an ion beam containing a second-type dopant to the
target film through the second ion beam mask in order to decrease a
polishing rate of the target film.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2014-152285, filed on Jul. 25, 2014, the entire contents of which
are incorporated herein by reference.
FIELD
[0002] The embodiments of the present invention relate to a
manufacturing method of semiconductor device and a semiconductor
manufacturing apparatus.
BACKGROUND
[0003] A CMP (Chemical Mechanical Polishing) method is
conventionally used in a processing technique of a semiconductor
device as a technique to flatten a semiconductor wafer. In the CMP
method, improvement in productivity such as throughput or cost is
demanded and processing accuracy such as in-plane uniformity or
flatness of the semiconductor wafer is also demanded.
[0004] For example, in a solid memory having a three-dimensional
structure, a protection film or the like includes large concaves
and convexes and steps to be flattened are large. In such a case,
the film thickness of the protection film or the like to be
polished is increased, which prolongs the polishing time. As a
result, the throughput is adversely lowered.
[0005] In connection thereto, a method of implanting ions into a
polishing target film is known as means for increasing the
polishing rate. By polishing the polishing target film after
implanting ions into the entire surface of the polishing target
film or selectively implanting ions into convex portions of the
polishing target film, the polishing rate of portions of the
polishing target film into which the ions have been implanted can
be increased.
[0006] However, these methods have problems such as an insufficient
polishing rate and degradation in the in-plane uniformity of the
semiconductor wafer after polishing.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIGS. 1A to 1C are cross-sectional views showing a
manufacturing method of a semiconductor device according to a
reference example;
[0008] FIG. 2 is a graph showing a relation between dopants and
polishing rates;
[0009] FIG. 3 is a plan view showing a manufacturing method of a
semiconductor device according to a first embodiment;
[0010] FIG. 4 is a cross-sectional view enlargedly showing a framed
portion C in FIG. 1C;
[0011] FIG. 5 is a schematic configuration diagram showing an ion
implantation device 100 including an ion beam mask 120 according to
the first embodiment;
[0012] FIG. 6 is a plan view showing a manufacturing method of a
semiconductor device according to a second embodiment;
[0013] FIG. 7 is a schematic configuration diagram showing the ion
implantation device 100 including an ion beam mask 121 according to
the second embodiment;
[0014] FIG. 8 is a flowchart showing a manufacturing method of a
semiconductor device according to a third embodiment;
[0015] FIG. 9 is a graph showing the concentration of a dopant
contained in the polishing target film 20 formed by a manufacturing
method of a semiconductor device according to a fourth
embodiment;
[0016] FIG. 10 is a plan view showing a manufacturing method of a
semiconductor device according to a fifth embodiment; and
[0017] FIG. 11 is a schematic configuration diagram showing the ion
implantation device 100 including the ion beam mask 120 according
to the fifth embodiment.
DETAILED DESCRIPTION
[0018] Embodiments will now be explained with reference to the
accompanying drawings. The present invention is not limited to the
embodiments.
[0019] A manufacturing method of a semiconductor device according
to an embodiment implants impurities into a central portion of a
polishing target film or an outer peripheral portion of the central
portion of the polishing target film to cause an impurity
concentration in the outer peripheral portion of the polishing
target film and an impurity concentration in the central portion
thereof to be different from each other, thereby modifying a
surface of the polishing target film. The modified surface of the
polishing target film is polished by a CMP method.
Reference Example
[0020] FIGS. 1A to 1C are cross-sectional views showing a
manufacturing method of a semiconductor device according to a
reference example. Although not particularly limited thereto, the
semiconductor device can be, for example, a semiconductor memory, a
high-speed logic LSI, a system LSI, or a memory-logic mixed
LSI.
[0021] First, a semiconductor element (not shown) is formed on a
semiconductor substrate 10 and a polishing target film (a target
film) 20 is formed above the semiconductor element as shown in FIG.
1A. The polishing target film 20 is a protection film such as an
interlayer dielectric film made of a silicon dioxide film. Other
examples of the polishing target film 20 can include a film made of
silicon, tungsten, copper, or aluminum. Next, ions of a first-type
dopant are implanted into the polishing target film 20 as shown in
FIG. 1B. The first-type dopant can be, for example, fluorine (F),
boron (B or BF.sub.2), phosphorus (P), or nitrogen (N). The ion
implantation is performed with the dopant in a dose amount of about
5.00.times.10.sup.15/cm.sup.2 and at an acceleration voltage of
about 50 keV. The dopant is implanted into the entire surface of
the polishing target film 20. A concentration of the dopant in the
polishing target film 20 is, for example, equal to or higher than
10.sup.19 cm.sup.-3. The ion implantation of the dopant breaks
crystal binding in a surface area of the polishing target film 20
(binding between Si and O in a silicon dioxide film, for example)
and modifies the surface of the polishing target film 20.
[0022] Subsequently, the polishing target film 20 is polished by
the CMP method as shown in FIG. 1C. A CMP device 200 includes a
polishing pad 210, a retainer ring 220, a membrane 230, and a head
240. The semiconductor substrate 10 is interposed between the
polishing pad 210 and the membrane 230 and is pressed in a
direction shown by arrows. When the head 240 turns, the
semiconductor substrate 10 is turned on the polishing pad 210. At
this time, ceria slurry, silica slurry, alumina slurry, or the like
is supplied between the semiconductor substrate 10 and the
polishing pad 210. This enables the polishing target film 20 formed
on the underside of the semiconductor substrate 10 in FIG. 1C to be
polished. The polishing pad 210 is made of, for example, foamed
polyurethane. The retainer ring 220 is made of, for example,
ceramics.
[0023] At this time, because the surface area of the polishing
target film 20 is damaged by the ion implantation mentioned above,
the polishing rate thereof is higher than that of a polishing
target film undamaged. For example, FIG. 2 is a graph showing a
relation between dopants and polishing rates. The vertical axis
represents the polishing rate. The horizontal axis represents the
type of dopant. Gno denotes a graph showing a polishing rate of the
polishing target film 20 not subjected to ion implantation. Gf
denotes a graph showing a polishing rate of the polishing target
film 20 having fluorine ions implanted. From comparison between Gno
and Gf, it is understood that the polishing rate of the surface
area of the polishing target film 20 having fluorine ions implanted
is higher than that of the polishing target film 20 not subjected
to ion implantation by about 10%. This is because fluorine ion
implantation breaks crystal binding in the surface area of the
polishing target film 20 and damages the surface of the polishing
target film 20. The polishing rate can be increased also by
implanting a first-type dopant such as boron (B or BF.sub.2),
phosphorus (P), nitrogen (N), or the like, other than fluorine (F),
into the polishing target film 20.
[0024] As described above, according to the reference example, to
increase the polishing rate of the polishing target film 20, ions
of the first-type dopant are implanted into the surface area of the
polishing target film 20, thereby modifying the surface of the
polishing target film 20. The modified surface of the polishing
target film 20 is then polished by the CMP method. Accordingly, the
polishing time at the CMP step can be shortened and the
productivity can be improved. By setting the concentration of the
first-type dopant in the polishing target film 20 to 10.sup.19
cm.sup.-3 or higher, the effect of increasing the polishing rate
can be further improved.
First Embodiment
[0025] FIG. 3 is a plan view showing a manufacturing method of a
semiconductor device according to a first embodiment. In the first
embodiment, the first-type dopant mentioned above is implanted
selectively into an area (hereinafter, also "central portion Pin"),
which is the surface area of the polishing target film 20 except an
outer peripheral portion Pex of the semiconductor substrate 10.
That is, the outer peripheral portion Pex is a peripheral portion
of the central portion Pin of the semiconductor substrate 10.
[0026] In the CMP method, the polishing pad 210 abutting on the
polishing target film 20 at the outer peripheral portion Pex of the
semiconductor substrate 10 is undulated due to rebounding against
the pressure of the retainer ring 220. For example, FIG. 4 is a
cross-sectional view enlargedly showing a framed portion C in FIG.
1C. Directions and sizes of arrows in FIG. 4 indicate directions of
pressures between the semiconductor substrate 10 and the polishing
pad 210 and sizes of the pressures, respectively. Because the
undulated polishing pad 210 is pressed against harder at the outer
peripheral portion Pex of the semiconductor substrate 10 than at
the central portion Pin, the polishing rate is increased more at
the outer peripheral portion Pex of the semiconductor substrate 10
than that at the central portion Pin. This may degrade the flatness
in the surface of the polishing target film 20 after polishing.
[0027] In the first embodiment, ions of the first-type dopant are
thus implanted selectively into the polishing target film 20 at the
central portion Pin of the semiconductor substrate 10 except the
outer peripheral portion Pex. It suffices that the outer peripheral
portion Pex of the semiconductor substrate 10 includes an area in
which the polishing pad 210 is undulated due to the pressure of the
retainer ring 220. Therefore, for example, when the semiconductor
substrate 10 is a semiconductor wafer having a diameter of 300
millimeters, the outer peripheral portion Pex of the semiconductor
substrate 10 is, for example, an area on the outer edge side having
a width of about 1 millimeter to 30 millimeters. The central
portion Pin of the semiconductor substrate 10 is an area on the
center side having a diameter of about 299 millimeters to 270
millimeters except the outer peripheral portion Pex.
[0028] In this way, by selectively performing ion implantation of
the first-type dopant into the polishing target film 20 at the
central portion Pin of the semiconductor substrate 10, the
polishing rate of the polishing target film 20 at the central
portion Pin of the semiconductor substrate 10 can be set closer or
substantially equal to the polishing rate of the polishing target
film 20 at the outer peripheral portion Pex. That is, ion
implantation of the first-type dopant is performed into the central
portion Pin of the polishing target film 20 to cause an impurity
concentration of the outer peripheral portion Pex of the polishing
target film 20 and an impurity concentration of the central portion
Pin of the polishing target film 20 to be different from each
other. As a result, the flatness in the surface of the polishing
target film 20 after polishing is improved.
[0029] To implant ions selectively into the central portion Pin of
the semiconductor substrate 10, it suffices to form a resist mask
to cover the outer peripheral portion Pex of the polishing target
film 20 using a lithography technique before the ion implantation
step. Alternatively, an ion beam mask that blocks the dopant can be
arranged above the outer peripheral portion Pex of the polishing
target film 20 at the ion implantation step.
[0030] FIG. 5 is a schematic configuration diagram showing an ion
implantation device 100 including an ion beam mask 120 according to
the first embodiment.
[0031] The ion implantation device 100 includes an ion source 110,
an extraction electrode 111, an accelerator 115, a mass separator
116, a scanner 117, the ion beam mask 120, a substrate holder (a
susceptor) 130, and a mask transporter (not shown). The ion source
110 ionizes a dopant. The extraction electrode 111 extracts the
ionized dopant from the ion source 110. The accelerator 115
accelerates the ionized dopant to form an ion beam and irradiates
the ion beam toward the substrate holder 130. That is, the ion
source 110 and the accelerator 115 function as an ion beam
irradiator. The mass separator 116 is provided to select a desired
ion type according to a difference in mass and to irradiate the
selected ion to the semiconductor substrate 10. The mass separator
116 or the accelerator 115 can include a mass spectrometry magnet
or a mass spectrometry slit. The scanner 117 adjusts the direction
of irradiation of the ion beam. The substrate holder 130 has the
semiconductor substrate 10 mounted thereon.
[0032] The ion beam mask 120 is formed annularly to block the ion
beam to be irradiated to the outer peripheral portion Pex of the
semiconductor substrate 10 (the surface of the polishing target
film 20). For example, when the semiconductor substrate 10 is a
semiconductor wafer having a diameter of 300 millimeters, the ion
beam mask 120 can be an annular mask having an opening with a
diameter of about 260 millimeters and having a width of about 20
millimeters. By using the ion beam mask 120 thus formed, the ion
beam is irradiated selectively to the surface of the polishing
target film 20 at the central portion Pin of the semiconductor
substrate 10. Accordingly, ions of the dopant are implanted into
the polishing target film 20 at the central portion Pin of the
semiconductor substrate 10. The ion beam mask 120 is made of a
non-metallic material such as a semiconductor material, graphite,
diamond-like carbon (DLC), Si, or SiC. A semiconductor wafer (a
silicon wafer, for example) can be alternatively used as the ion
beam mask 120. In this way, the ion implantation device 100 used in
the first embodiment irradiates an ion beam to the polishing target
film 20 to increase the polishing rate of the polishing target film
20. At this time, the ion beam mask 120 partially covers the
polishing target film 20 to shield a part of the ion beam. This
enables ions of the first-type dopant to be implanted selectively
into the polishing target film 20 at the central portion Pin of the
semiconductor substrate 10 not through the lithography
technique.
[0033] When the ion implantation device 100 emits a ribbon-like ion
beam or a spot-like ion beam, it suffices that the ion beam mask
120 and the wafer holder 130 move in a direction perpendicular to
the direction of irradiation of the ion beam (either in a vertical
direction or a horizontal direction) synchronously with each other.
Accordingly, even when the ribbon-like ion beam or the spot-like
ion beam is used, the ion implantation device 100 can implant ions
of the first-type dopant into the polishing target film 20 at the
central portion Pin substantially uniformly.
[0034] Alternatively, ions of the dopant can be implanted
selectively into the central portion Pin of the polishing target
film 20 using a scan technique of an ion beam. In this case, an ion
implantation device causes an ion beam to scan the semiconductor
substrate 10 while changing the concentration of the ion beam. The
ion implantation device then turns the semiconductor substrate 10
and causes the ion beam to scan the semiconductor substrate 10
again while changing the concentration of the ion beam. In this
way, the ion implantation device can selectively modify the
polishing target film 20 at the central portion Pin of the
semiconductor substrate 10 without using the ion beam mask 120.
[0035] In the first embodiment, a certain amount of the dopant can
be implanted into the outer peripheral portion Pex covered by the
ion beam mask 120. In this case, it suffices that more ions of the
first-type dopant are implanted into the central portion Pin and
that the concentration of the dopant in the central portion Pin is
higher than that of the outer peripheral portion Pex by 10.sup.19
cm.sup.-3 or more. This is because the polishing rate of the
polishing target film 20 at the central portion Pin of the
semiconductor substrate 10 thus can be set closer to the polishing
rate of the polishing target film 20 at the outer peripheral
portion Pex.
Second Embodiment
[0036] FIG. 6 is a plan view showing a manufacturing method of a
semiconductor device according to a second embodiment. In the
second embodiment, a second-type dopant is implanted selectively
into the outer peripheral portion Pex of the semiconductor
substrate 10 in the surface area of the polishing target film 20.
The second-type dopant can be, for example, carbon (c), nitrogen
(N), or silicon (Si). The ion implantation is performed with the
dopant in a dose amount of about 1 to 5.00.times.10.sup.15/cm.sup.2
and at an acceleration voltage of about 50 keV. The second-type
dopant is an element that suppresses a reaction between slurry and
the polishing target film 20. Therefore, the ion implantation of
the second-type dopant is performed to decrease the polishing rate
of the polishing target film 20 at the outer peripheral portion Pex
of the semiconductor substrate 10.
[0037] Next, the polishing target film 20 is thermally treated to
repair crystal defects caused by the ion implantation. The thermal
treatment can be RTA (Rapid Thermal Anneal), furnace anneal,
microwave anneal, or the like. For example, when an electric
furnace, a hot plate, or a lamp (a halogen lamp, for example) is
used, the crystal defects caused by the ion implantation can be
repaired through thermal treatment at a temperature equal to or
higher than 900.degree. C. When microwave irradiation at 5.8
gigahertz is used, the crystal defects caused by the ion
implantation can be repaired even at a temperature equal to or
lower than 800.degree. C. This thermal treatment enables the
crystal binding of the polishing target film 20 broken by the ion
implantation to be rebound. That is, the polishing target film 20
damaged by the ion implantation is recovered. Because the quality
of the polishing target film 20 is restored, decrease in the
polishing rate due to the second-type dopant becomes noticeable.
For example, FIG. 2 is referred back to. Gsi indicates a polishing
rate of the polishing target film 20 thermally treated after
silicon ions are implanted. Gc indicates a polishing rate of the
polishing target film 20 thermally treated after carbon ions are
implanted. From comparison between Gno and Gsi (or Gc), it is
understood that the polishing rate of the surface area of the
polishing target film 20 having silicon or carbon implanted thereto
becomes lower than that of the polishing target film 20 having no
ions implanted. This is because silicon or carbon suppresses a
reaction between the polishing target film 20 and slurry at the CMP
step and decreases the polishing rate of the polishing target film
20. Nitrogen (N) can be used as the first-type dopant and the
second-type dopant. This is for the following reason. That is, when
the polishing target film 20 is a silicon dioxide film, binding
between Si and O that constitute the silicon dioxide film in the
polishing target film 20 having nitrogen ions implanted thereto is
broken by implantation of the nitrogen ions. Such a silicon dioxide
film is in a state easily reacting with ions in a CMP solution
during the period of the CMP step, that is, a state being easily
etched. On the other hand, when the thermal treatment mentioned
above is performed after nitrogen ions are implanted, binding
defects in the polishing target film 20 are repaired. Binding
between Si and N with a higher binding energy than that in binding
between Si and O is thus formed in the polishing target film 20.
Accordingly, the polishing target film 20 during the period of the
CMP step is in a state not easily reacting with ions in the CMP
solution, that is, a state being not easily etched. For the reason
mentioned above, nitrogen (N) can be used as the first-type dopant
and the second-type dopant.
[0038] In the second embodiment, ions of the second-type dopant are
implanted selectively into the polishing target film 20 at the
outer peripheral portion Pex of the semiconductor substrate 10.
That is, ions of the second-type dopant are implanted into the
outer peripheral portion Pex of the polishing target film 20 to
cause an impurity concentration in the outer peripheral portion Pex
of the polishing target film 20 and an impurity concentration in
the central portion Pin of the polishing target film 20 to be
different from each other. Accordingly, the polishing rate of the
polishing target film 20 at the outer peripheral portion Pex of the
semiconductor substrate 10 can be set closer or substantially equal
to the polishing rate of the polishing target film 20 at the
central portion Pin of the semiconductor substrate 10. As a result,
the flatness in the surface of the polishing target film 20 after
polishing is improved. Furthermore, when the concentration of the
second-type dopant in the polishing target film 20 is set to
10.sup.19 cm.sup.-3 or higher, the effect of decreasing the
polishing rate can be further improved.
[0039] To implant ions selectively into the outer peripheral
portion Pex of the semiconductor substrate 10, it suffices to form
a resist mask to cover the central portion Pin of the polishing
target film 20 using the lithography technique before the ion
implantation step. Alternatively, an ion beam mask that blocks the
dopant can be arranged above the central portion Pin of the
polishing target film 20 at the ion implantation step.
[0040] To realize the ion implantation according to the second
embodiment, it suffices to change the shape of the ion beam mask
120 of the ion implantation device 100 shown in FIG. 4. For
example, FIG. 7 is a schematic configuration diagram showing the
ion implantation device 100 including an ion beam mask 121
according to the second embodiment. The ion implantation device 100
in FIG. 7 is different from the ion implantation device 100 in FIG.
5 in the shape of the ion beam mask 121. Other configurations of
the ion implantation device 100 in FIG. 7 can be identical to the
corresponding configurations of the ion implantation device 100 in
FIG. 5. The ion beam mask 121 is formed in a shape to block an ion
beam to be irradiated to the central portion Pin of the
semiconductor substrate 10 (the surface of the polishing target
film 20). For example, when the semiconductor substrate 10 is a
semiconductor wafer having a diameter of 300 millimeters, the ion
beam mask 121 can be a circular mask having a diameter of about 260
millimeters. By using the ion beam mask 121 as mentioned above, the
ion beam can be selectively irradiated to the surface of the
polishing target film 20 at the outer peripheral portion Pex of the
semiconductor substrate 10. Accordingly, ions of the second-type
dopant are implanted into the polishing target film 20 at the outer
peripheral portion Pex of the semiconductor substrate 10. The ion
beam mask 121 can be formed of the same material as that of the ion
beam mask 120. A semiconductor wafer (a silicon wafer, for example)
can be used as the ion beam mask 121.
[0041] As described above, the ion implantation device 100 used in
the second embodiment irradiates an ion beam to the polishing
target film 20 to decrease the polishing rate of the polishing
target film 20. At this time, the ion beam mask 121 partially
covers the polishing target film 20 to shield a part of the ion
beam. Accordingly, ions of the second-type dopant can be implanted
selectively into the polishing target film 20 at the outer
peripheral portion Pex of the semiconductor substrate 10 not
through the lithography technique.
[0042] When the ion implantation device 100 emits a ribbon-like ion
beam, it suffices that the ion beam mask 121 and the wafer holder
130 move in a direction perpendicular to the direction of
irradiation of the ion beam (either in a vertical direction or a
horizontal direction) synchronously with each other. Accordingly,
even when the ribbon-like ion beam is used, the ion implantation
device 100 can implant ions of the second-type dopant into the
polishing target film 20 at the outer peripheral portion Pex
substantially uniformly.
[0043] Alternatively, the ion implantation device according to the
second embodiment can selectively implant ions of the dopant into
the central portion Pin of the polishing target film 20 using a
scan technique of an ion beam, similarly to the first embodiment.
This enables the ion implantation device to selectively modify the
polishing target film 20 at the outer peripheral portion Pex of the
semiconductor substrate 10 without using an ion beam mask.
[0044] In the second embodiment, a certain amount of dopants can be
implanted into the central portion Pin covered by the ion beam mask
121. In this case, it suffices that more ions of the second-type
dopant are implanted into the outer peripheral portion Pex and that
the concentration of the dopant in the outer peripheral portion Pex
is higher than that of the central portion Pin by 10.sup.19
cm.sup.-3 or more. This is because the polishing rate of the
polishing target film 20 at the outer peripheral portion Pex of the
semiconductor substrate 10 thus can be set closer to the polishing
rate of the polishing target film 20 at the central portion
Pin.
[0045] Furthermore, the thermal treatment in the second embodiment
can be performed at the same time as the ion implantation. For
example, the ion implantation can be performed under a situation of
a high temperature of 450.degree. C. to 500.degree. C. The ion
implantation step and the thermal treatment step can be thus
shortened. In a case where heating is performed during the ion
implantation, the heating can be performed at a temperature
100.degree. C. to 400.degree. C. lower than that in a case where
the heating is performed after the ion implantation in
consideration of heating by ions. This can also repair the crystal
binding of the polishing target film 20.
Third Embodiment
[0046] FIG. 8 is a flowchart showing a manufacturing method of a
semiconductor device according to a third embodiment. The third
embodiment is a combination of the first and second embodiments.
That is, the first-type dopant is implanted selectively into the
central portion Pin of the semiconductor substrate 10 in the
surface area of the polishing target film 20 and also the
second-type dopant is implanted selectively into the outer
peripheral portion Pex of the semiconductor substrate 10.
[0047] By implanting ions of the first-type dopant selectively into
the polishing target film 20 at the central portion Pin of the
semiconductor substrate 10, the polishing rate of the polishing
target film 20 at the central portion Pin of the semiconductor
substrate 10 can be set closer to that of the polishing target film
20 at the outer peripheral portion Pex thereof. By further
implanting ions of the second-type dopant selectively into the
polishing target film 20 at the outer peripheral portion Pex of the
semiconductor substrate 10, the polishing rate of the polishing
target film 20 at the outer peripheral portion Pex of the
semiconductor substrate 10 can be set more closer to that of the
polishing target film 20 at the central portion Pin of the
semiconductor substrate 10. As a result, the polishing rate of the
polishing target film 20 can be set substantially uniform in the
surface of the polishing target film 20 and thus the flatness in
the surface of the polishing target film 20 after polishing is
improved.
[0048] The ion implantation step of the first-type dopant and the
ion implantation step of the second-type dopant can be obtained by
combining those in the first embodiment and the second embodiment.
However, in the first embodiment, the polishing target film 20 is
not thermally treated after ion implantation of the first-type
dopant. On the other hand, the polishing target film 20 is
thermally treated after ion implantation of the second-type dopant
in the second embodiment. Therefore, in the third embodiment, the
ion implantation step of the second-type dopant, the thermal
treatment step, and the ion implantation step of the first-type
dopant are performed in this order. In this manner, the first and
second embodiments can be combined.
[0049] For example, when the ion implantation device 100 is used,
the ion implantation device 100 includes both the ion beam masks
121 and 120 and implants ions of both the second-type dopant and
the first-type dopant using these masks.
[0050] First, to implant ions of the second-type dopant selectively
into the outer peripheral portion Pex of the semiconductor
substrate 10, the ion implantation device 100 covers the central
portion Pin of the polishing target film 20 with the ion beam mask
121 and shields a part of the ion beam. The ion implantation device
100 thus implants ions of the second-type dopant selectively into
the polishing target film 20 at the outer peripheral portion Pex of
the semiconductor substrate 10 without implanting ions into the
central portion Pin of the semiconductor substrate 10 (S10).
[0051] Next, the polishing target film 20 is thermally treated
(S20). This thermal treatment recovers the polishing target film 20
damaged by the ion implantation.
[0052] Subsequently, to implant ions of the first-type dopant
selectively into the central portion Pin of the semiconductor
substrate 10, the ion implantation device 100 covers the outer
peripheral portion Pex of the polishing target film 20 with the ion
beam mask 120 and shields a part of the ion beam. The ion
implantation device 100 thus implants ions of the first-type dopant
selectively into the polishing target film 20 at the central
portion Pin of the semiconductor substrate 10 without implanting
ions into the outer peripheral portion Pex of the semiconductor
substrate 10 (S30).
[0053] In this way, the polishing rate of the polishing target film
20 at the outer peripheral portion Pex of the semiconductor
substrate 10 can be decreased and also the polishing rate of the
polishing target film 20 at the central portion Pin of the
semiconductor substrate 10 can be increased. Accordingly, the
polishing rate in the entire surface of the polishing target film
20 can be set substantially uniform and the flatness in the surface
of the polishing target film 20 after polishing can be
improved.
Fourth Embodiment
[0054] FIG. 9 is a graph showing the concentration of a dopant
contained in the polishing target film 20 formed by a manufacturing
method of a semiconductor device according to a fourth embodiment.
The vertical axis represents the concentration of the dopant and
the horizontal axis represents the depth from the surface of the
polishing target film 20.
[0055] In the fourth embodiment, to improve the increasing effect
on the polishing rate or the decreasing effect on the polishing
rate, the ion implantation device 100 implants ions of a dopant
into the polishing target film 20 a plurality of times at a
plurality of acceleration energies different from each other
(multistage ion implantation). The dopant subjected to ion
implantation in the fourth embodiment is the first-type dopant
and/or the second-type dopant. Accordingly, the fourth embodiment
can be applied to any of the first to third embodiments described
above.
[0056] For example, the ion implantation device 100 implants ions
of the first-type dopant at acceleration energies of 10 keV, 30
keV, and 50 keV. The concentration of the dopant thus has three
peaks P1 to P3 in the depth direction of the polishing target film
20 as shown in FIG. 9. P1 indicates a concentration peak of the
dopant in a case where the acceleration energy is 10 keV. P2
indicates a concentration peak of the dopant in a case where the
acceleration energy is 30 key. P3 indicates a concentration peak of
the dopant in a case where the acceleration energy is 50 key.
Between P1 and P2 in the graph, the dopant in the case where the
acceleration energy is 10 keV and the dopant in the case where the
acceleration energy is 30 keV overlap. Between P2 and P3 of the
graph, the dopant in the case where the acceleration energy is 30
keV and the dopant in the case where the acceleration energy is 50
keV overlap. Therefore, by implanting ions of the dopant at the
acceleration energies of 10 keV, 30 keV, and 50 keV, the
concentration of the first-type dopant becomes high (10.sup.19
cm.sup.-3 or higher, for example) entirely in the depths from D1 to
D3 as shown by a solid line Ltotal in FIG. 9. That is, the
concentration profile of the first-type dopant has a so-called
box-type flat profile in a range of the depths from D1 to D3 from
the surface of the polishing target film 20. Accordingly, the
polishing rate can be increased in the range of the depths from D1
to D3 of the polishing target film 20. That is, according to the
fourth embodiment, because the polishing rate is increased in a
wide range (D1 to D3) in the width direction of the polishing
target film 20, the polishing time at the CMP step can be
shortened. Furthermore, when ions of the first-type dopant are
implanted, the fourth embodiment can also achieve the effects of
the reference example and the first embodiment mentioned above. To
increase the polishing rate from the surface of the polishing
target film 20, it suffices to adjust the acceleration energies of
the ion implantation device 100 to meet D1=0.
[0057] Similarly, when ions of the second-type dopant are implanted
into the polishing target film 20 a plurality of times at a
plurality of acceleration energies different from each other, the
concentration profile of the second-type dopant has a so-called
box-type flat profile in a range of the depths from D1 to D3 of the
polishing target film 20. Accordingly, the polishing rate of the
polishing target film 20 can be decreased more effectively. In this
case, the fourth embodiment can also achieve the effects of the
second embodiment.
[0058] It is also possible that the concentration profiles of both
the first and second types of dopant in the third embodiment have
box-type flat profiles. Accordingly, the effects of the third
embodiment can be further improved.
[0059] The acceleration energies in the multistage ion implantation
are not limited to three stages, but can be also two stages or four
or more stages. The acceleration energy can be continuously
changed, for example, in a range from 1 keV to 60 keV. Furthermore,
the dose amount can be adjusted in a range from
4.00.times.10.sup.14/cm.sup.2 to 1.00.times.10.sup.16/cm.sup.2 to
cause the dopant concentration to have a box-type flat profile in
the depth direction of the polishing target film 20.
Fifth Embodiment
[0060] FIG. 10 is a plan view showing a manufacturing method of a
semiconductor device according to a fifth embodiment. Shots at a
lithography step are denoted by solid line frames SHd or SHnd in a
plane of the semiconductor substrate 10 shown in FIG. 10. The shot
areas SHnd denoted by the frames in which x is shown are areas
having patterns (or patterns) not formed. The shot areas SHd
denoted by the frames in which x is not shown are areas having
patterns (or dummy patterns) formed. Production chips CH are formed
in a thick line frame B of the semiconductor substrate 10. The
production chips CH are shown by broken line frames. No production
chips CH are formed on the semiconductor substrate 10 outside the
thick line frame B. Therefore, dummy patterns are formed in parts
of the shot areas SHd outside the thick line frame B. Patterns (or
dummy patterns) are not formed in an area outside the thick line
frame B corresponding to the shot areas SHnd.
[0061] Generally, the semiconductor substrate 10 has an outer
peripheral portion in which patterns of production chips are not
formed as shown in FIG. 10. To shorten throughput at the
lithography step, photolithography shots are in some cases not
performed on the outer peripheral portion in which no production
chips are formed. In these cases, the areas SHd to which shots are
performed and in which patterns (or dummy patterns) are formed and
the areas SHnd to which no shots are performed and in which
patterns (or dummy patterns) are not formed are mixed in the outer
peripheral portion of the semiconductor substrate 10. If the
semiconductor substrate 10 is polished by the CMP method in such a
state, the polishing rates differ between the areas SHd and the
areas SHnd. Because patterns (or dummy patterns) are not formed in
the shot areas SHnd, a material layer remains as it is. Therefore,
in the shot areas SHnd, it is preferable to increase the polishing
rate to suppress occurrence of layer remaining. On the other hand,
because patterns (or dummy patterns) are formed in the areas SHd,
the areas SHd are polished more easily than the areas SHnd.
Therefore, if the polishing rate is increased, excessive polishing
may occur in the areas SHd.
[0062] In the CMP method, the polishing is progressed by turning a
semiconductor wafer on a polishing pad. Therefore, the profile of
the polishing rate is concentric in a plane of the semiconductor
substrate 10. However, the polishing rate varies in the outer
peripheral portion of the semiconductor substrate 10 depending on
the presence or absence of the patterns (or dummy patterns).
[0063] In the fifth embodiment, the first-type dopant is thus
implanted selectively into the shot areas SHnd of the surface area
of the polishing target film 20 on the semiconductor substrate 10.
No dopant is implanted to the shot areas SHd.
[0064] Accordingly, the polishing rate of the shot areas SHnd is
increased to set the polishing rate of the shot areas SHnd closer
to the polishing rate of the shot areas SHd.
[0065] FIG. 11 is a schematic configuration diagram showing the ion
implantation device 100 including the ion beam mask 120 according
to the fifth embodiment. The ion implantation device 100 is
basically the same as that of the first embodiment except the shape
of the ion beam mask 120. Therefore, the ion source 110, the
extraction electrode 111, the accelerator 115, the mass separator
116, the scanner 117, and the like are omitted in FIG. 11.
[0066] The ion beam mask 120 is formed to block an ion beam
irradiated to the chips CH and the shot areas SHd of the
semiconductor substrate 10 and to allow an ion beam irradiated to
the shot areas SHnd to pass. Accordingly, ions of the dopant are
implanted into the shot areas SHnd not having patterns (or dummy
patterns). In FIG. 11, the ions of the dopant are implanted into a
hatched portion of the semiconductor substrate 10. The material of
the ion beam mask 120 can be identical to that of the first
embodiment.
[0067] In this way, the polishing rate in the shot areas SHnd can
be increased to be closer or equal to the polishing rate in the
shot areas SHd. This prevents excessive polishing of the polishing
target film 20 in the shot areas SHd among edge portions of the
semiconductor substrate 10 and achieves sufficient removal of the
polishing target film 20 in the shot areas SHnd. Accordingly,
variations in the film thickness (film reduction) at the edge
portions of the semiconductor substrate 10 can be suppressed.
[0068] Furthermore, the type of dopant to be implanted into the
shot areas SHnd and the dose amount thereof can be changed
according to an occupancy rate of the production chips CH in the
plane of the semiconductor substrate 10. The type of dopant to be
implanted into the shot areas SHnd or the dose amount thereof can
be changed according to an occupancy rate of convex portions (or
concave portions) in the production chips CH. In this way, the
polishing rate of the shot areas SHnd can be controlled similarly
to the polishing rate of the shot areas SHd in various
semiconductor products.
[0069] While certain embodiments have been described, these
embodiments have been presented by way of example only, and are not
intended to limit the scope of the inventions. Indeed, the novel
methods and systems described herein may be embodied in a variety
of other forms; furthermore, various omissions, substitutions and
changes in the form of the methods and systems described herein may
be made without departing from the spirit of the inventions. The
accompanying claims and their equivalents are intended to cover
such forms or modifications as would fall within the scope and
spirit of the inventions.
* * * * *