U.S. patent application number 15/414011 was filed with the patent office on 2018-07-26 for nanosheet capacitor.
The applicant listed for this patent is INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Ruqiang Bao, Zhenxing Bi, Kangguo Cheng, Zheng Xu.
Application Number | 20180212017 15/414011 |
Document ID | / |
Family ID | 62874355 |
Filed Date | 2018-07-26 |
United States Patent
Application |
20180212017 |
Kind Code |
A1 |
Bao; Ruqiang ; et
al. |
July 26, 2018 |
NANOSHEET CAPACITOR
Abstract
A capacitive device includes a first electrode comprising a
nanosheet stack, and a second electrode comprising a nanosheet
stack, the second electrode arranged substantially parallel to the
first electrode. A first conductive contact is arranged on a basal
end of the first electrode, and a second conductive contact
arranged on a basal end of the second electrode.
Inventors: |
Bao; Ruqiang; (Wappingers
Falls, NY) ; Bi; Zhenxing; (Niskayuna, NY) ;
Cheng; Kangguo; (Schenectady, NY) ; Xu; Zheng;
(Wappingers Falls, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
Armonk |
NY |
US |
|
|
Family ID: |
62874355 |
Appl. No.: |
15/414011 |
Filed: |
January 24, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 28/60 20130101;
H01L 28/86 20130101; H01L 21/76224 20130101; H01L 29/41725
20130101; H01L 29/0673 20130101; H01L 29/401 20130101; H01L 29/775
20130101; B82Y 10/00 20130101; H01L 29/66439 20130101 |
International
Class: |
H01L 49/02 20060101
H01L049/02; H01L 21/02 20060101 H01L021/02; H01L 21/265 20060101
H01L021/265; H01L 21/324 20060101 H01L021/324; H01L 21/283 20060101
H01L021/283; H01L 21/311 20060101 H01L021/311; H01L 21/306 20060101
H01L021/306; H01L 21/762 20060101 H01L021/762; H01L 21/8238
20060101 H01L021/8238; H01L 27/092 20060101 H01L027/092; H01L 27/06
20060101 H01L027/06 |
Claims
1. A method for forming a capacitive device, the method comprising:
forming a nanosheet stack on a substrate, the nanosheet stack
including a first nanosheet layer comprising a first material and a
second nanosheet layer arranged on the first nanosheet layer, the
second nanosheet layer comprising a second material; removing
portions of the nanosheet stack to form a first fin and a second
fin; depositing a first insulator layer on the substrate;
implanting ions in the first fin and the second fin and annealing
to form a first electrode and a second electrode; removing the
first insulator layer; removing the first nanosheet layer from the
first electrode and the second electrode to form voids between the
first electrode and the substrate and the second electrode and the
substrate; depositing a second insulator layer on the substrate and
in the void under the first electrode and the void under the second
electrode; and forming a first conductive contact on a basal end of
the first electrode and a second metallic conductive contact on a
basal end of the second electrode, wherein the first nanosheet
material includes a first semiconductor material and they second
nanosheet material includes a second semiconductor material.
2. The method of claim 1, wherein the first insulator layer
includes a dielectric material.
3. The method of claim 1, wherein the second insulator layer
includes a dielectric material.
4. The method of claim 1, wherein the first conductive contact is
formed by: removing portions of the second insulator layer to form
a cavity that exposes portions of the first electrode; and
depositing a conductive material in the cavity.
5. The method of claim 1, wherein the first electrode is arranged
substantially in parallel with the second electrode.
6. (canceled)
7. The method of claim 1, wherein the first semiconductor material
includes silicon germanium.
8. The method of claim 7, wherein the second semiconductor material
includes silicon.
9. A method for forming a capacitive device, the method comprising:
forming a nanosheet stack on a substrate, the nanosheet stack
includes alternating layers of a first material and a second
material; removing portions of the nanosheet stack to form a first
fin and a second fin; depositing a first insulator layer on the
substrate; implanting ions in the first fin and the second fin and
annealing to form a first electrode and a second electrode;
removing the first insulator layer; removing the second material of
the first fin and the second fin to form voids between the second
electrode and the substrate, and the first electrode and the
substrate; and depositing a second insulator layer on the substrate
and in the voids under the first electrode and the void under the
second electrode, wherein first material includes a first
semiconductor material and the second material includes a second
semiconductor material.
10. The method of claim 9, wherein the first insulator layer
includes a dielectric material.
11. The method of claim 9, wherein the second insulator layer
includes a dielectric material.
12. The method of claim 9, further comprising forming a conductive
contact on a distal end of the first electrode.
13. The method of claim 9, wherein the first electrode is arranged
substantially in parallel with the second electrode.
14. (canceled)
15. The method of claim 9, wherein the first semiconductor material
includes silicon germanium.
16. The method of claim 14, wherein the second semiconductor
material includes silicon.
17-20. (canceled)
Description
BACKGROUND
[0001] The present invention generally relates to semiconductor
devices, and more specifically, to nanosheet capacitors.
[0002] Nanosheets often include thin layers (sheets) of
semiconductor material that are arranged in a stack. A nanosheet
stack often includes alternating layers of dissimilar materials. In
semiconductor device fabrication, the nanosheets are often
patterned into nanosheet fins. Once the fins are patterned, a gate
stack is formed over a channel region of the fins, and source/drain
regions are formed adjacent to the gate stack.
[0003] In some devices, once the gate stack or the source/drain
regions have been formed, an etching process is performed to
selectively remove nanosheet layers of one of the dissimilar
materials from the fins. The etching process results in the
undercutting and suspension of the layers of the nanosheet fin to
form nanowires. The nanowires can be used to form gate-all-around
devices.
[0004] Electronic circuits often include capacitive devices.
Capacitive devices often include substantially planar electrodes
that are arranged in parallel with a dielectric material disposed
between the electrodes. Capacitive devices are operative to store a
charge and are often included in CMOS circuit designs.
SUMMARY
[0005] According to an embodiment of the present invention, a
method for forming a capacitive device includes forming a nanosheet
stack on a substrate, the nanosheet stack including a first
nanosheet layer having a first material and a second nanosheet
layer arranged on the first nanosheet layer, the second nanosheet
layer comprising a second material, and removing portions of the
nanosheet stack to form a first fin and a second fin. A first
insulator layer is deposited on the substrate. Ions are implanted
in the first fin and the second fin and annealing to form a first
electrode and a second electrode. The first insulator layer is
removed. The first nanosheet layer is removed from the first
electrode and the second electrode is removed to form voids between
the first electrode and the substrate and the second electrode and
the substrate. A second insulator layer is deposited on the
substrate and in the void under the first electrode and the void
under the second electrode. A first conductive contact is formed on
a basal end of the first electrode and a second metallic conductive
contact is formed on a basal end of the second electrode.
[0006] According to another embodiment of the present invention, a
method for forming a capacitive device includes forming a nanosheet
stack on a substrate, the nanosheet stack includes alternating
layers of a first material and a second material, and removing
portions of the nanosheet stack to form a first fin and a second
fin. A first insulator layer is deposited on the substrate. Ions
are implanted in the first fin and the second fin and annealing to
form a first electrode and a second electrode. The first insulator
layer is removed. The second material of the nanosheet fin is
removed to form voids between the second electrode and the
substrate, and the first electrode and the substrate. A second
insulator layer is deposited on the substrate and in the voids
under the first electrode and the void under the second
electrode.
[0007] According to yet another embodiment of the present
invention, a capacitive device includes a first electrode having a
nanosheet stack, and a second electrode comprising a nanosheet
stack, the second electrode arranged substantially parallel to the
first electrode. A first conductive contact is arranged on a basal
end of the first electrode, and a second conductive contact
arranged on a basal end of the second electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIGS. 1-14C illustrate an exemplary method for forming a
capacitive device.
[0009] FIG. 1 illustrates a cut-away view of a semiconductor
substrate.
[0010] FIG. 2 illustrates a cut-away view following the formation
of a nanosheet stack on the substrate.
[0011] FIG. 3A illustrates a cut-away view along the line A-A (of
FIG. 3B) following the patterning of electrodes from the nanosheet
stack.
[0012] FIG. 3B illustrates a top view of the fins arranged on the
substrate.
[0013] FIG. 4A illustrates a cut-away view along the line A-A (of
FIG. 4B) following the formation of a shallow trench isolation
(STI) region on exposed portions of the substrate.
[0014] FIG. 4B illustrates a top view following the formation of
the shallow trench isolation region.
[0015] FIG. 5 illustrates a cut-away view following an ion
implantation and annealing process that implants dopants into the
fins to form electrodes.
[0016] FIG. 6A illustrates a cut-away view along the line A-A (of
FIG. 6D) following the removal of portions of the shallow trench
isolation region (of FIG. 5) and an etching process that removes
portions of the first doped nanosheet layer.
[0017] FIG. 6B illustrates a cut-away view along the line B-B (of
FIG. 6D) following the selective anisotropic etching process that
removes portions of the first doped nanosheet layer.
[0018] FIG. 6C illustrates a cut-away view along the line C-C (of
FIG. 6D).
[0019] FIG. 6D illustrates a top view following the removal of the
shallow trench isolation region (of FIG. 5).
[0020] FIG. 7 illustrates a top view following the deposition of an
inter-level dielectric layer over exposed portions of the substrate
(of FIG. 5).
[0021] FIG. 8A illustrates a cut-away view along the line A-A (of
FIG. 8C) following the patterning of a mask over portions of the
inter-level dielectric layer.
[0022] FIG. 8B illustrates a cut-away view along the line B-B (of
FIG. 8C) of the mask.
[0023] FIG. 8C illustrates a top view of the mask.
[0024] FIG. 9A illustrates a cut-away view along the line A-A (of
FIG. 9C) following a selective etching process that removes exposed
portions of the inter-level dielectric layer to form a cavity that
exposes portions of the electrode.
[0025] FIG. 9B illustrates a cut-away view along the line B-B (of
FIG. 9C) following the selective etching process that forms the
cavity that exposes portions of the electrode.
[0026] FIG. 9C illustrates a top view following the formation of
the cavities.
[0027] FIG. 10A illustrates a cut-away view along the line A-A (of
FIG. 10C) following the removal of the mask (of FIG. 9A) and the
formation of contacts in the cavity (of FIG. 9A).
[0028] FIG. 10B illustrates a cut-away view along the line B-B (of
FIG. 10C) following the formation of the conductive contact.
[0029] FIG. 10C illustrates a top view of the conductive contacts
and the electrodes.
[0030] FIG. 11A illustrates a cut-away view along the line A-A (of
FIG. 11C) following the patterning of a mask over portions of the
inter-level dielectric layer and an etching process that removes
portions of the inter-level dielectric layer, and the portions of
the electrodes to form cavities in the inter-level dielectric layer
that expose a distal portion of the electrode.
[0031] FIG. 11B illustrates a cut-away view along the line B-B (of
FIG. 11C) following the patterning of the mask.
[0032] FIG. 11C illustrates a top view following the patterning of
the mask.
[0033] FIG. 12A illustrates a cut-away view along the line A-A (of
FIG. 12C) following the formation of conductive contacts in the
cavities (of FIGS. 11A, 11B, and 11C).
[0034] FIG. 12B illustrates a cut-away view along the line B-B (of
FIG. 12C) following the formation of conductive contacts in the
cavities (of FIGS. 11A, 11B, and 11C).
[0035] FIG. 12C illustrates a top view following the formation of
conductive contacts in the cavities (of FIGS. 11A, 11B, and
11C).
[0036] FIG. 13A illustrates a cut-away view along the line A-A (of
FIG. 13C) following the deposition of a second inter-level
dielectric layer, the patterning of a mask over the second
inter-level dielectric layer and a selective anisotropic etching
process that forms cavities.
[0037] FIG. 13B illustrates a cut-away view along the line B-B (of
FIG. 13C) following the deposition of a second inter-level
dielectric layer, the patterning of a mask over the second
inter-level dielectric layer and a selective anisotropic etching
process that forms cavities.
[0038] FIG. 13C illustrates a top view following the deposition of
a second inter-level dielectric layer, the patterning of a mask
over the second inter-level dielectric layer and a selective
anisotropic etching process that forms cavities.
[0039] FIG. 14A illustrates a cut-away view along the line A-A (of
FIG. 14C) following the removal of the mask (of FIGS. 13A, 13B, and
13C) and the formation of conductive contacts in the cavities.
[0040] FIG. 14B illustrates a cut-away view along the line B-B (of
FIG. 14C) following the removal of the mask (of FIGS. 13A, 13B, and
13C) and the formation of conductive contacts in the cavities.
[0041] FIG. 14C illustrates a top view following the removal of the
mask (of FIGS. 13A, 13B, and 13C) and the formation of conductive
contacts in the cavities.
[0042] FIG. 15 illustrates a top view of an alternate exemplary
embodiment of a capacitive device.
DETAILED DESCRIPTION
[0043] As discussed above, nanosheets and nanosheet fins can be
used to form active semiconductor devices. It is desirable to form
capacitive devices using methods and materials that integrate into
process flows that are used to form active devices that are formed
using nanosheets.
[0044] The methods and resultant structures described herein
provide for forming capacitive devices using fins formed from
nanosheets. The illustrated methods can be efficiently integrated
into field effect transistor (FET) fabrication process flows that
form FET devices from nanosheets. The capacitive devices include
two or more electrodes that are arranged on a substrate. The number
of electrodes and the length of the electrodes among other
parameters affect the external capacitance of the capacitive
devices.
[0045] FIGS. 1-10C illustrate an exemplary method for forming a
capacitive device.
[0046] FIG. 1 illustrates a cut-away view of a semiconductor
substrate 102.
[0047] Non-limiting examples of suitable materials for the
semiconductor substrate (substrate) 102 include Si (silicon),
strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon
germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys,
III-V materials (e.g., GaAs (gallium arsenide), InAs (indium
arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)),
II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium
sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc
selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any
combination thereof. Other non-limiting examples of semiconductor
materials include III-V materials, for example, indium phosphide
(InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), or any
combination thereof. The III-V materials can include at least one
"III element," such as aluminum (Al), boron (B), gallium (Ga),
indium (In), and at least one "V element," such as nitrogen (N),
phosphorous (P), arsenic (As), antimony (Sb).
[0048] FIG. 2 illustrates a cut-away view following the formation
of a nanosheet stack 201 on the substrate 102.
[0049] A stack of nanosheet material layers (nanosheet stack) 201
is arranged on the substrate 102. The nanosheet material layers in
the illustrated embodiment include a first nanosheet material layer
204 and a second nanosheet material layer 202 arranged on the first
nanosheet material layer 204. The stack of nanosheet material
layers 201 can include any number of alternating nanosheet material
layers 202 and 204. In the illustrated embodiment, the first
nanosheet material layer 204 includes a silicon germanium material
and the second nanosheet material layer 202 includes a silicon
material. In alternate exemplary embodiments, the first nanosheet
material layer 204 can be a silicon material while the second
nanosheet material layer 202 can be silicon germanium. The stack of
nanosheet material layers 201 can be formed by any suitable
process. The germanium concentration (atomic concentration) in the
SiGe layer ranges from about 15% to 99% and more preferably from
about 25% to 60%. The Si/SiGe stack can be formed by epitaxial
growth by using the semiconductor layer 102 as the seed layer.
[0050] The epitaxial growth can be performed by any suitable
techniques such as ultrahigh vacuum chemical vapor deposition
(UHVCVD) rapid thermal chemical vapor deposition (RTCVD),
Metalorganic Chemical Vapor Deposition (MOCVD), low-pressure
chemical vapor deposition (LPCVD), limited reaction processing CVD
(LRPCVD), molecular beam epitaxy (MBE). Each layer is stacked,
nanosheet has a non-limiting thickness ranging from about 3-20 nm,
more preferably about 5-10 nm.
[0051] FIG. 3A illustrates a cut-away view along the line A-A (of
FIG. 3B) following the patterning of electrodes 302 from the
nanosheet stack 201. The electrodes 302 can be formed by, for
example, a photolithographic patterning and etching process that
removes portions of the nanosheet stack 201 to expose portions of
the substrate 102. Any suitable etching process can be used such
as, for example, reactive ion etching.
[0052] FIG. 3B illustrates a top view of the fins 302a and 302b
arranged on the substrate 102. The electrode 302 generally refers
to the fins 302a and 302b.
[0053] FIG. 4A illustrates a cut-away view along the line A-A (of
FIG. 4B) following the formation of an inter-level dielectric (ILD)
region 402 on exposed portions of the substrate 102. The ILD region
402 can be formed by, any suitable process including, for example,
lithography or etching to form trenches, and then filling the
trenches with an insulating material, such as silicon dioxide.
[0054] In the illustrated embodiment, at least one isolation region
can be an inter-level dielectric However, the isolation region 402
can be a trench isolation region, a field oxide isolation region
(not shown), or any other type of isolation region. The isolation
region 402 provides isolation between neighboring gate structure
regions, and can be used when the neighboring devices have opposite
conductivities, e.g., nFETs and pFETs. As such, the isolation
region 402 separates an nFET device region from a pFET device
region.
[0055] FIG. 4B illustrates a top view following the formation of
the inter-level dielectric region 402.
[0056] FIG. 5 illustrates a cut-away view following an ion
implantation and annealing process that implants dopants into the
fins 302 to form electrodes 501. The ion implantation process
implants ions in the fins 302 and the annealing process drives or
activates the ions through the fins 302. The resulting structure
includes a first doped nanosheet layer 502 and a second doped
nanosheet layer 504.
[0057] FIG. 6A illustrates a cut-away view along the line A-A (of
FIG. 6D) following the removal of portions of the inter-level
dielectric region 402 (of FIG. 5) and an etching process that
removes the exposed portions of the first doped nanosheet layer 504
to form voids 601 and 603 (in FIG. 6B). With respect to fin 302a,
removal of portions of the first doped nanosheet layer 504 results
in electrode 501a. In this regard, the inter-level dielectric
region 402 can be removed by a selective isotropic or anisotropic
etching process. Any suitable selective etching process can be used
such as, for example, a H.sub.2O.sub.2 or an isotropic dry etching
process to remove portions of the first doped nanosheet layer
504.
[0058] FIG. 6B illustrates a cut-away view along the line B-B (of
FIG. 6D) following the selective anisotropic etching process. With
respect to fin 302b, removal of portions of the first doped
nanosheet layer 504 results in electrode 501b. FIG. 6C illustrates
a cut-away view along the line C-C (of FIG. 6D).
[0059] FIG. 6D illustrates a top view following the removal of the
inter-level dielectric region 402 (of FIG. 5), and the removal of
the doped nanosheet layers 502.
[0060] FIG. 7 illustrates a top view following the deposition of
another inter-level dielectric layer 702 over exposed portions of
the substrate 102 (of FIG. 5).
[0061] The inter-level dielectric layer 702 is formed from, for
example, a low-k dielectric material (with k<4.0), including but
not limited to, silicon oxide, spin-on-glass, a flowable oxide, a
high density plasma oxide, borophosphosilicate glass (BPSG), or any
combination thereof. The inter-level dielectric layer 702 is
deposited by a deposition process, including, but not limited to
CVD, PVD, plasma enhanced CVD, atomic layer deposition (ALD),
evaporation, chemical solution deposition, or like processes.
Following the deposition of the inter-level dielectric layer 702, a
planarization process such as, for example, chemical mechanical
polishing is performed.
[0062] FIG. 8A illustrates a cut-away view along the line A-A (of
FIG. 8C) following the patterning of a mask 802 over portions of
the inter-level dielectric layer 702. The mask 802 can include, for
example, an organic planarizing layer, or a photolithographic
resist material. FIG. 8B illustrates a cut-away view along the line
B-B (of FIG. 8C) of the mask 802. FIG. 8C illustrates a top view of
the mask 802.
[0063] FIG. 9A illustrates a cut-away view along the line A-A (of
FIG. 9C) following a selective etching process that removes exposed
portions of the inter-level dielectric layer 702 and the electrode
501a to form a cavity 902a that exposes portions of the electrode
501a.
[0064] FIG. 9B illustrates a cut-away view along the line B-B (of
FIG. 9C) following the selective etching process that forms the
cavity 902b that removes a portion of the electrode 501b and
exposes portions of the electrode 501b. FIG. 9C illustrates a top
view following the formation of the cavities 902a and 902b.
[0065] FIG. 10A illustrates a cut-away view along the line A-A (of
FIG. 10C) following the removal of the mask 802 (of FIG. 9A) and
the formation of contacts 1004 in the cavity 902a (of FIG. 9A). The
mask 802 can be removed by a suitable process such as, for example,
ashing. Following the removal of the mask 802, a liner layer 1002
that can include, for example, a nitride or an oxide material is
deposited in the cavity 902a and a portion of the liner layer is
removed to expose a portion of the electrode 501a, a conductive
material is deposited in the cavities 902a and 902b (of FIG. 9B). A
planarization process can be performed to remove overburdened
conductive contact material.
[0066] The ashing process can be used to remove a photoresist
material, amorphous carbon, or organic planarization (OPL) layer.
Ashing is performed using a suitable reaction gas, for example,
O.sub.2, N.sub.2, H2/N2, O.sub.3, CF.sub.4, or any combination
thereof.
[0067] The conductive material can include any suitable conductive
material including, for example, polycrystalline or amorphous
silicon, germanium, silicon germanium, a metal (e.g., tungsten,
titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum,
lead, platinum, tin, silver, gold), a conducting metallic compound
material (e.g., tantalum nitride, titanium nitride, tantalum
carbide, titanium carbide, titanium aluminum carbide, tungsten
silicide, tungsten nitride, ruthenium oxide, cobalt silicide,
nickel silicide), carbon nanotube, conductive carbon, graphene, or
any suitable combination of these materials. The conductive
material can further include dopants that are incorporated during
or after deposition.
[0068] FIG. 10B illustrates a cut-away view along the line B-B (of
FIG. 10C) following the formation of the conductive contact 1004 as
described above.
[0069] FIG. 10C illustrates a top view of the conductive contacts
1004 and the electrodes 501a and 501b.
[0070] FIG. 11A illustrates a cut-away view along the line A-A (of
FIG. 11C) following the patterning of a mask 1102 over portions of
the inter-level dielectric layer 702 and an etching process that
removes portions of the inter-level dielectric layer 702, and the
portions of the electrodes 501a and 501b to form cavities 1101 in
the inter-level dielectric layer 702 that expose a distal portion
of the electrode 501a. The mask 1102 can include, for example, an
organic planarizing layer, or a photolithographic resist material.
FIG. 11B illustrates a cut-away view along the line B-B (of FIG.
11C) of the mask 1102. FIG. 11C illustrates a top view of the mask
1102.
[0071] FIG. 12A illustrates a cut-away view along the line A-A (of
FIG. 12C), FIG. 12B illustrates a cut-away view along the line B-B
(of FIG. 12C), and FIG. 12C illustrates a top view following the
formation of conductive contacts 1204 in the cavities 1101 (of
FIGS. 11A, 11B, and 11C).
[0072] FIG. 13A illustrates a cut-away view along the line A-A (of
FIG. 13C), FIG. 13B illustrates a cut-away view along the line B-B
(of FIG. 13C), and FIG. 13C illustrates a top view following the
deposition of a second inter-level dielectric layer 1302, the
patterning of a mask 1304 over the second inter-level dielectric
layer 1302 and a selective anisotropic etching process that forms
cavities 1301 that exposes portions of the conductive contacts 1204
and 1004.
[0073] FIG. 14A illustrates a cut-away view along the line A-A (of
FIG. 14C), FIG. 14B illustrates a cut-away view along the line B-B
(of FIG. 14C), and FIG. 14C illustrates a top view following the
removal of the mask 1304 (of FIGS. 13A, 13B, and 13C) and the
formation of conductive contacts 1402 in the cavities 1301.
[0074] FIG. 14C illustrates the top view of the resultant
capacitive device 1401.
[0075] FIG. 15 illustrates a top view of an alternate exemplary
embodiment of a capacitive device 1501. The capacitive device 1501
is similar to the capacitive device 1401 described above. The
capacitive device 1501 includes a plurality of electrodes 501a and
501b.
[0076] The methods and resultant structures described herein
provide for forming capacitive devices having electrodes formed
from nanowire sheets. Any number of electrodes having a variety of
lengths can be formed to form capacitive devices that have desired
performance parameters.
[0077] The methods described herein provide for forming capacitive
devices in a process flow that can be integrated into process flows
used to form active semiconductor devices.
[0078] The descriptions of the various embodiments of the present
invention have been presented for purposes of illustration, but are
not intended to be exhaustive or limited to the embodiments
described. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the
embodiments, the practical application or technical improvement
over technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments described
herein.
* * * * *