U.S. patent application number 15/926127 was filed with the patent office on 2018-07-26 for embedded stacked die packages and related methods.
This patent application is currently assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC. The applicant listed for this patent is SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC. Invention is credited to Azhar ARIPIN, Francis J. CARNEY, Chee Hiong CHEW, Yusheng LIN, Yenting WEN.
Application Number | 20180211939 15/926127 |
Document ID | / |
Family ID | 59009225 |
Filed Date | 2018-07-26 |
United States Patent
Application |
20180211939 |
Kind Code |
A1 |
LIN; Yusheng ; et
al. |
July 26, 2018 |
EMBEDDED STACKED DIE PACKAGES AND RELATED METHODS
Abstract
Forming a semiconductor package includes coupling electrically
conductive elements with a substrate, coupling a first die with one
or more of the electrically conductive elements, and at least
partially encapsulating the first die and electrically conductive
elements in a first mold layer. A first redistribution layer (RDL)
is placed over the first mold layer and electrically coupled with
the first die. A second die is coupled with the first RDL, and the
second die and first RDL are at least partially encapsulated in a
second mold layer. A second RDL is formed over the second mold
layer and is electrically coupled with the second die. A third mold
layer at least partially encapsulates the second RDL. A portion of
the substrate is removed to expose (and a solder mask is applied
to) surfaces of the electrically conductive elements and of the
first mold layer to form a stacked embedded package.
Inventors: |
LIN; Yusheng; (Phoenix,
AZ) ; CARNEY; Francis J.; (Mesa, AZ) ; WEN;
Yenting; (Chandler, AZ) ; CHEW; Chee Hiong;
(Seremban, MY) ; ARIPIN; Azhar; (Subang Jaya,
MY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC |
Phoenix |
AZ |
US |
|
|
Assignee: |
SEMICONDUCTOR COMPONENTS
INDUSTRIES, LLC
Phoenix
AZ
|
Family ID: |
59009225 |
Appl. No.: |
15/926127 |
Filed: |
March 20, 2018 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
15612971 |
Jun 2, 2017 |
9941257 |
|
|
15926127 |
|
|
|
|
15221464 |
Jul 27, 2016 |
9679878 |
|
|
15612971 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/16227
20130101; H01L 2924/181 20130101; H01L 21/76877 20130101; H01L
21/0273 20130101; H01L 24/16 20130101; H01L 21/76802 20130101; H01L
2224/04105 20130101; H01L 2224/24145 20130101; H01L 23/367
20130101; H01L 24/19 20130101; H01L 24/81 20130101; H01L 21/568
20130101; H01L 2224/92244 20130101; H01L 25/074 20130101; H01L
2224/81191 20130101; H01L 2224/131 20130101; H01L 24/82 20130101;
H01L 21/4853 20130101; H01L 24/24 20130101; H01L 23/3675 20130101;
H01L 2224/32245 20130101; H01L 2224/73267 20130101; H01L 2224/16245
20130101; H01L 21/565 20130101; H01L 25/50 20130101; H01L 23/5389
20130101; H01L 2924/181 20130101; H01L 2924/00012 20130101; H01L
2224/131 20130101; H01L 2924/014 20130101; H01L 2924/00014
20130101 |
International
Class: |
H01L 25/07 20060101
H01L025/07; H01L 23/367 20060101 H01L023/367; H01L 21/56 20060101
H01L021/56; H01L 23/00 20060101 H01L023/00; H01L 21/027 20060101
H01L021/027; H01L 21/768 20060101 H01L021/768; H01L 25/00 20060101
H01L025/00 |
Claims
1. A semiconductor package, comprising: a first semiconductor die
at least partially encapsulated in a first mold layer; a first
redistribution layer (RDL) coupled with the first mold layer, the
first redistribution layer electrically coupled with the first
semiconductor die; a second semiconductor die coupled with the
first redistribution layer; the second semiconductor die and the
first redistribution layer at least partially encapsulated in a
second mold layer; and a second redistribution layer (RDL) coupled
with the second mold layer, the second redistribution layer
electrically coupled with the second semiconductor die and the
second redistribution layer at least partially encapsulated in a
third mold layer.
2. The package of claim 1, wherein the first redistribution layer
is coupled with one or more of a plurality of electrically
conductive elements.
3. The package of claim 1, wherein the first mold layer, the second
mold layer, and the third mold layer are formed using compression
molding.
4. The package of claim 1, further comprising a third semiconductor
die coupled at least partially encapsulated in the first mold
layer.
5. The package of claim 1, wherein the package does not comprise a
sequential build-up (SBU) laminate substrate.
6. The package of claim 1, wherein the package comprises no
bondwires and no electrically conductive clips.
7. The package of claim 1, wherein the first redistribution layer
is electrically coupled with the first semiconductor die through
one or more electrically conductive pillars, the second
redistribution layer is electrically coupled with the second
semiconductor die through one or more electrically conductive
pillars, and the second redistribution layer is electrically
coupled with the first redistribution layer through one or more
electrically conductive pillars.
8. The package of claim 1, further comprising a heat dissipation
device coupled with the second redistribution layer, the heat
dissipation device at least partially encapsulated in the third
mold layer, wherein a portion of the heat dissipation device is
exposed on an outer surface of the package through an opening in
the third mold layer.
9. A semiconductor package, comprising: a first semiconductor die
at least partially encapsulated in a first mold layer; one or more
first vias through the first mold layer at least partially filled
with an electrically conductive material to form one or more first
pillars; a first redistribution layer (RDL) coupled with the first
mold layer, the first redistribution layer electrically coupled
with the first semiconductor die through the one or more first
pillars; a second semiconductor die coupled with the first
redistribution layer; the second semiconductor die and the first
redistribution layer at least partially encapsulated in a second
mold layer; one or more second vias through the second mold layer
at least partially filled with an electrically conductive material
to form one or more second pillars; and a second redistribution
layer (RDL) coupled with the second mold layer, the second
redistribution layer electrically coupled with the second
semiconductor die through the one or more second pillars.
10. The method of claim 9, further comprising electrically coupling
the first redistribution layer with one or more of a plurality of
electrically conductive elements.
11. The package of claim 9, wherein the first mold layer, the
second mold layer, and the third mold layer are formed using
compression molding.
12. The package of claim 9, further comprising a third
semiconductor die coupled at least partially encapsulated in the
first mold layer.
13. The package of claim 9, wherein the package does not comprise a
sequential build-up (SBU) laminate substrate.
14. The package of claim 9, wherein the package comprises no
bondwires and no electrically conductive clips.
15. The package of claim 9, wherein the second redistribution layer
is electrically coupled with the first redistribution layer through
the one or more second pillars.
16. The package of claim 9, further comprising a heat dissipation
device coupled with the second redistribution layer, the heat
dissipation device at least partially encapsulated in the third
mold layer, wherein a portion of the heat dissipation device is
exposed on an outer surface of the package through an opening in
the third mold layer.
17. A semiconductor package, comprising: a first semiconductor die
coupled with a third semiconductor die, the first semiconductor die
and the third semiconductor die at least partially encapsulated in
a first mold layer; a first redistribution layer (RDL) coupled with
the first mold layer, the first redistribution layer electrically
coupled with the first semiconductor die; a second semiconductor
die coupled with the first redistribution layer; the second
semiconductor die and the first redistribution layer at least
partially encapsulated in a second mold layer; and a second
redistribution layer (RDL) coupled with the second mold layer, the
second redistribution layer electrically coupled with the second
semiconductor die and the second redistribution layer at least
partially encapsulated in a third mold layer.
18. The package of claim 17, wherein the first redistribution layer
is electrically coupled with one or more of a plurality of
electrically conductive elements.
19. The package of claim 17, wherein the stacked embedded package
comprises no sequential build-up (SBU) laminate substrates, no
bondwires, and no electrically conductive clips.
20. The method of claim 17, further comprising a heat dissipation
device coupled with the second redistribution layer.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation application of the
earlier U.S. Utility patent application to Lin entitled "Embedded
Stacked Die Packages and Related Methods," application Ser. No.
15/612,971, filed Jun. 2, 2017, now pending, which is a
continuation application of the earlier U.S. Utility patent
application to Lin entitled "Embedded Stacked Die Packages and
Related Methods," application Ser. No. 15/221,464, filed Jul. 27,
2016, now pending, the disclosures of each which are hereby
incorporated entirely herein by reference.
BACKGROUND
1. Technical Field
[0002] Aspects of this document relate generally to semiconductor
packages. More specific implementations involve embedded stacked
die semiconductor packages.
2. Background
[0003] Semiconductor devices, such as integrated circuits and the
like, are often encased in one or more protective elements, such as
a mold compound, protect the die and/or other elements from damage,
moisture, contamination, and so forth. An (at least partially)
encased semiconductor device, including the encasing or
encapsulating compound, together with any electrical contacts
exposed outside or through the encapsulating compound, is often
called a package. In some cases, multiple die may be included in a
single package.
SUMMARY
[0004] Implementations of methods of forming a semiconductor
package (package) may include: coupling a plurality of electrically
conductive elements with a substrate; coupling a first
semiconductor die with one or more of the plurality of electrically
conductive elements; at least partially encapsulating the first
semiconductor die and the plurality of electrically conductive
elements in a mold compound to form a first mold layer; forming a
first redistribution layer (RDL) over the first mold layer, the
first redistribution layer electrically coupled with the first
semiconductor die; coupling a second semiconductor die with the
first redistribution layer; at least partially encapsulating the
second semiconductor die and the first redistribution layer in a
mold compound to form a second mold layer; forming a second
redistribution layer (RDL) over the second mold layer, the second
redistribution layer electrically coupled with the second
semiconductor die; at least partially encapsulating the second
redistribution layer in a mold compound to form a third mold layer;
removing at least a portion of the substrate from the plurality of
electrically conductive elements and from the first mold layer,
thereby exposing surfaces of the plurality of electrically
conductive elements and surfaces of the first mold layer, and;
applying a solder mask to portions of the exposed surfaces of the
plurality of electrically conductive elements and to portions of
the exposed surfaces of the first mold layer to form a stacked
embedded package.
[0005] Implementations of methods of forming a semiconductor
package (package) may include one, all, or any of the
following:
[0006] Electrically coupling the first redistribution layer with
one or more of the plurality of electrically conductive
elements.
[0007] The first mold layer, the second mold layer, and the third
mold layer may be formed using compression molding.
[0008] Coupling a third semiconductor die with one or more of the
plurality of electrically conductive elements and at least
partially encapsulating the third semiconductor die in the first
mold layer.
[0009] The stacked embedded package may not include a sequential
build-up (SBU) laminate substrate.
[0010] The stacked embedded package may include no bondwires and no
electrically conductive clips.
[0011] Electrically coupling the first redistribution layer with
the first semiconductor die through one or more electrically
conductive pillars, electrically coupling the second redistribution
layer with the second semiconductor die through one or more
electrically conductive pillars, and electrically coupling the
second redistribution layer with the first redistribution layer
through one or more electrically conductive pillars.
[0012] Coupling a heat dissipation device with the second
redistribution layer and at least partially encapsulating the heat
dissipation device in the third mold layer, wherein a portion of
the heat dissipation device is exposed on an outer surface of the
package through an opening in the third mold layer.
[0013] Implementations of methods of forming a semiconductor
package (package) may include: coupling a plurality of electrically
conductive elements with a substrate; coupling a first
semiconductor die with one or more of the plurality of electrically
conductive elements; at least partially encapsulating the first
semiconductor die and the plurality of electrically conductive
elements in a mold compound to form a first mold layer; forming one
or more first vias through the first mold layer to expose one or
more surfaces of the first semiconductor die; at least partially
filling the one or more first vias with an electrically conductive
material to form one or more first pillars; forming a first
redistribution layer (RDL) over the first mold layer, the first
redistribution layer electrically coupled with the first
semiconductor die through the one or more first pillars; coupling a
second semiconductor die with the first redistribution layer; at
least partially encapsulating the second semiconductor die and the
first redistribution layer in a mold compound to form a second mold
layer; forming one or more second vias through the second mold
layer to expose one or more surfaces of the second semiconductor
die; at least partially filling the one or more second vias with an
electrically conductive material to form one or more second
pillars; forming a second redistribution layer (RDL) over the
second mold layer, the second redistribution layer electrically
coupled with the second semiconductor die through the one or more
second pillars; at least partially encapsulating the second
redistribution layer in a mold compound to form a third mold layer;
removing at least a portion of the substrate from the plurality of
electrically conductive elements and from the first mold layer,
thereby exposing surfaces of the plurality of electrically
conductive elements and surfaces of the first mold layer, and;
applying a solder mask to portions of the exposed surfaces of the
plurality of electrically conductive elements and to portions of
the exposed surfaces of the first mold layer to form a stacked
embedded package.
[0014] Implementations of methods of forming a semiconductor
package (package) may include one, all, or any of the
following:
[0015] Electrically coupling the first redistribution layer with
one or more of the plurality of electrically conductive
elements.
[0016] The first mold layer, the second mold layer, and the third
mold layer may be formed using compression molding.
[0017] Coupling a third semiconductor die with one or more of the
plurality of electrically conductive elements and at least
partially encapsulating the third semiconductor die in the first
mold layer.
[0018] The stacked embedded package may include no sequential
build-up (SBU) laminate substrates, no bondwires, and no
electrically conductive clips.
[0019] Forming one or more second vias through the second mold
layer may expose one or more surfaces of the first redistribution
layer and the second redistribution layer may be electrically
coupled with the first redistribution layer through the one or more
second pillars.
[0020] Coupling a heat dissipation device with the second
redistribution layer and at least partially encapsulating the heat
dissipation device in the third mold layer, wherein a portion of
the heat dissipation device is exposed on an outer surface of the
package through an opening in the third mold layer.
[0021] Implementations of methods of forming a semiconductor
package (package) may include: coupling a plurality of electrically
conductive elements with a substrate; coupling a first
semiconductor die with one or more of the plurality of electrically
conductive elements; at least partially coating the first
semiconductor die and the plurality of electrically conductive
elements with a photoresist material to form a first photoresist
layer; patterning the first photoresist layer to form one or more
first vias exposing one or more surfaces of the first semiconductor
die; at least partially filling the one or more first vias with an
electrically conductive material to form one or more first pillars;
removing the first photoresist layer; at least partially
encapsulating the first semiconductor die, the plurality of
electrically conductive elements, and the one or more first pillars
in a mold compound to form a first mold layer; forming a first
redistribution layer (RDL) over the first mold layer, the first
redistribution layer electrically coupled with the first
semiconductor die; coupling a second semiconductor die with the
first redistribution layer; at least partially coating the second
semiconductor die and the first redistribution layer with a
photoresist material to form a second photoresist layer; patterning
the second photoresist layer to form one or more second vias
exposing one or more surfaces of the second semiconductor die; at
least partially filling the one or more second vias with an
electrically conductive material to form one or more second
pillars; removing the second photoresist layer; at least partially
encapsulating the second semiconductor die, the first
redistribution layer, and the one or more second pillars in a mold
compound to form a second mold layer; forming a second
redistribution layer (RDL) over the second mold layer, the second
redistribution layer electrically coupled with the second
semiconductor die through the one or more second pillars; at least
partially encapsulating the second redistribution layer in a mold
compound to form a third mold layer; removing at least a portion of
the substrate from the plurality of electrically conductive
elements and from the first mold layer, thereby exposing surfaces
of the plurality of electrically conductive elements and surfaces
of the first mold layer, and; applying a solder mask to portions of
the exposed surfaces of the plurality of electrically conductive
elements and to portions of the exposed surfaces of the first mold
layer to form a stacked embedded package.
[0022] Implementations of methods of forming a semiconductor
package (package) may include one, all, or any of the
following:
[0023] Electrically coupling the first redistribution layer with
one or more of the plurality of electrically conductive
elements.
[0024] The first mold layer, the second mold layer, and the third
mold layer may be formed using compression molding.
[0025] Coupling a third semiconductor die with one or more of the
plurality of electrically conductive elements and at least
partially encapsulating the third semiconductor die in the first
mold layer.
[0026] The stacked embedded package may include no sequential
build-up (SBU) laminate substrates, no bondwires, and no
electrically conductive clips.
[0027] Forming the one or more second vias through the second
photoresist layer may expose one or more surfaces of the first
redistribution layer, and the method may further include
electrically coupling the second redistribution layer with the
first redistribution layer through the one or more second
pillars.
[0028] The second redistribution layer may be coupled with one or
more of the plurality of electrically conductive elements through
the one or more second pillars and through the first redistribution
layer.
[0029] Coupling a heat dissipation device with the second
redistribution layer and at least partially encapsulating the heat
dissipation device in the third mold layer, wherein a portion of
the heat dissipation device is exposed on an outer surface of the
package through an opening in the third mold layer.
[0030] The foregoing and other aspects, features, and advantages
will be apparent to those artisans of ordinary skill in the art
from the DESCRIPTION and DRAWINGS, and from the CLAIMS.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Implementations will hereinafter be described in conjunction
with the appended drawings, where like designations denote like
elements, and:
[0032] FIG. 1 representatively illustrates a processing step used
in a first method of forming the semiconductor package of FIGS. 14
and 31;
[0033] FIG. 2 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0034] FIG. 3 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0035] FIG. 4 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0036] FIG. 5 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0037] FIG. 6 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0038] FIG. 7 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0039] FIG. 8 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0040] FIG. 9 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0041] FIG. 10 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0042] FIG. 11 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0043] FIG. 12 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0044] FIG. 13 representatively illustrates another processing step
used in the first method of forming the semiconductor package of
FIGS. 14 and 31;
[0045] FIG. 14 shows a cross-section view of a semiconductor
package formed using the processing steps representatively
illustrated in FIGS. 1-13;
[0046] FIG. 15 representatively illustrates a processing step used
in a second method of forming the semiconductor package of FIGS. 14
and 31;
[0047] FIG. 16 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0048] FIG. 17 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0049] FIG. 18 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0050] FIG. 19 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0051] FIG. 20 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0052] FIG. 21 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0053] FIG. 22 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0054] FIG. 23 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0055] FIG. 24 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0056] FIG. 25 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0057] FIG. 26 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0058] FIG. 27 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0059] FIG. 28 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0060] FIG. 29 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0061] FIG. 30 representatively illustrates another processing step
used in the second method of forming the semiconductor package of
FIGS. 14 and 31;
[0062] FIG. 31 shows a cross-section view of a semiconductor
package formed using the processing steps representatively
illustrated in FIGS. 15-30;
[0063] FIG. 32 shows a cross-section view of elements of another
semiconductor package;
[0064] FIG. 33 shows cross-section views of three implementations
of heat dissipation devices, and;
[0065] FIG. 34 shows a cross-section view of an implementation of a
semiconductor package including a heat dissipation device.
DESCRIPTION
[0066] This disclosure, its aspects and implementations, are not
limited to the specific components, assembly procedures or method
elements disclosed herein. Many additional components, assembly
procedures and/or method elements known in the art consistent with
the intended embedded stacked die packages and related methods will
become apparent for use with particular implementations from this
disclosure. Accordingly, for example, although particular
implementations are disclosed, such implementations and
implementing components may comprise any shape, size, style, type,
model, version, measurement, concentration, material, quantity,
method element, step, and/or the like as is known in the art for
such embedded stacked die packages and related methods, and
implementing components and methods, consistent with the intended
operation and methods.
[0067] Referring now to FIGS. 1-14, an implementation of a process
for forming a semiconductor package (package) 2 is illustrated. The
completed package is shown in FIG. 14. The package is a stacked
embedded package 4 and includes a plurality of electrically
conductive elements 12 including horizontal members 14 and vertical
members 16. A first semiconductor die (die) 22 is coupled over one
of the horizontal members and electrically conductive pillars
(first pillars) 60 couple the first die with a first redistribution
layer (first RDL) 64. The first die, first pillars and horizontal
members are included within a first mold layer 50 of the package. A
second mold layer 66 atop the first mold layer includes a second
semiconductor die (die) 32 and electrically conductive pillars
(second pillars) 76 coupling the second die with a second
redistribution layer (second RDL)--the second RDL is included in a
third mold layer 82. A third semiconductor die (die) 42 is coupled
with one or more of the horizontal members and/or vertical members
and is within the first mold layer. The first RDL electrically
couples the first die with the third die through one of the
vertical members and electrically couples the first die with the
second die. The second die and third die are electrically coupled
through a path that includes the second redistribution layer, an
electrically conductive pillar (pillar) 79 between the second
redistribution layer and first redistribution layer, the first
redistribution layer, and one of the vertical members, and one of
the horizontal members. A number of solder masks 94 are coupled at
a bottom of the package over portions of the first mold layer and
portions of the horizontal members.
[0068] FIG. 31 shows a semiconductor package 2 which is similar to
package 2 shown in FIG. 14, but the package shown in FIG. 14 is
formed using a first process or method representatively illustrated
in FIGS. 1-14 while the package of FIG. 31 is formed using a second
process or method representatively illustrated in FIGS. 15-31, as
will now be described.
[0069] Referring to FIG. 1, a first method of forming a
semiconductor package 2 includes forming, on a first surface 8 of a
substrate 6, a number of electrically conductive elements 12. The
electrically conductive elements include horizontal members 14 and
vertical members 16. The substrate has a second surface 10 opposite
the first surface. The substrate could be formed of any material
and one or both of the substrate and electrically conductive
elements could be included in a pre-formed frame. The electrically
conductive elements could be formed of any metal or other
electrically conductive material. Various processing techniques may
be used to form the elements 12, including deposition, sputtering,
electroplating, electroless plating, etching, and related
photolithography and/or masking steps.
[0070] A first semiconductor die (die) (first die) 22 is coupled
over one of the horizontal members so that at least one electrical
contact of the first die is electrically coupled therewith. Any
type of die could be used, such as an insulated gate bipolar
transistor (IGBT), a field-effect transistor (FET), a
metal-oxide-semiconductor FET (MOSFET), a bipolar junction
transistor (BJT), and so forth, but in the implementation shown the
first die is a FET 24 and is configured in the package so that it
is a high-side FET (HSFET) relative to one or more other FETs. FET
24 has gate, source and drain contacts, with one of these three
contacts coupled with one of the horizontal members.
[0071] A second semiconductor die (die) (second die) will be
described hereafter, but in implementations a third semiconductor
die (die) (third die) 42 is coupled with one or more of the
horizontal and vertical members as shown in FIG. 2. As FIG. 2
shows, the third die is electrically coupled with three horizontal
members and two vertical members (the left and right vertical
members are in turn each integrally formed with one of the
horizontal members each). The third die 42 is a driver 44 and could
be formed using any type of die as described above with respect to
the first die. In FIG. 2 the third die is a FET driver. In the
implementation shown the third die has gate, source and drain
contacts all on one side or surface of the die, so that electrical
couplers 46 (all of which are solder bumps 48 in the representative
example) are all located on one side of the die to couple those
contacts with the electrically conductive elements 12. In other
configurations the third die could be flipped and coupled with the
electrically conductive elements 12 using wire bonds.
[0072] The different die configurations, such as the first die
having electrical contacts or pads on two sides of the die, and the
third die having electrical contacts or pads on only one side of
the die, are only representative examples to show that the
configuration of the electrically conductive elements 12 may be
configured to receive either type of die, and that any die of the
package could have either configuration. Thus, any of the first
die, third die, and (hereafter described) second die (along with
any other die included in the package) could have electrical
contacts/pads or the like on only one side/surface or could have
them on multiple surfaces/sides, including opposing surfaces/sides
as shown with respect to the representative example of the first
die.
[0073] In implementations the electrically conductive elements
could be glued, adhered using an adhesive, soldered, bonded, or
otherwise coupled with the substrate. The first die could be
coupled with its corresponding horizontal member using, by
non-limiting example, solder paste and a heating stage.
[0074] Once the first die and third die are in place, they are at
least partially encapsulated in a first mold layer (overmold) 50.
The first mold layer has a first surface 52 and a second surface 54
opposite the first surface, and is formed of a mold compound 56.
After the molding process a grinding/polishing process may be used
to grind down the encapsulant/mold to a desired level such as to
form exposed surfaces 18 of the vertical members and/or to make
them flush with the top of the first mold layer. One or more first
vias 58 are formed to expose surfaces 26 of electrical contacts 28
of the first die as shown in FIG. 4. As described previously, the
first die is only a representative example of one die
configuration, so in the instant case where the first die has
electrical contacts on its upper side vias may be formed to access
them, while if the first die were configured as the third die no
vias would be needed and instead the contacts could be formed using
one or more vertical members. The electrical contacts 28 of the
first die are pads 30, though in other implementations they could
have other configurations. The first vias could be formed using a
laser drill process, though other processes such as selective
etching could be used.
[0075] A plating or other deposition process is then used to form
electrically conductive pillars (first pillars) 60 in the first
mold layer coupled with the pads of the first die, as shown in FIG.
5. The first pillars fill the first vias. Any type of plating or
material deposition technique could be used, such as electroplating
or electroless plating, sputtering, chemical vapor deposition
(CVD), and so forth. The first pillars may be formed of any
electrically conductive material 62. A second grinding process may
then be done to level the upper surface of the first mold layer
with the upper surfaces of the vertical members and the first
pillars so that they are all flush with one another.
[0076] A first redistribution layer (first RDL) 64 is formed atop
the upper surface of the first mold layer as shown in FIG. 6. This
may be formed with any electrically conductive material using any
material deposition technique, and in the representative example is
formed of copper using a plating process (such as electroplating or
electroless plating). FIG. 6 shows that, in the representative
example, the first die and third die are coupled with one another
through a path including one of the first pillars, a portion of the
first RDL, and one of the vertical members. Thus, the first RDL may
be used to electrically couple the first and third die, and (as
will be shown hereafter) may also be utilized to couple the first
and second die and/or the second and third die.
[0077] FIG. 7 shows a second semiconductor die (die) (second die)
32 that is coupled with the first RDL so that it is electrically
coupled with the first die. The second die in the implementation
shown has electrical contacts 38 on two sides, similar to the
representative example of the first die, but in other
implementations it could have a configuration similar to the third
die where it has electrical contacts only on one side of the die
and other elements of the package (vias, RDLs, etc.) could be
configured to still make the appropriate electrical couplings
between the various die and/or other package elements. The
electrical contacts of the second die are pads 40 in the drawings,
but in other implementations they could have other configurations.
The second die could be any type of die as described previously
with respect to other die, but in the implementation shown it is a
FET 34 which is configured in the package to be a low side FET
(LSFET) relative to one or more other die of the package.
[0078] A second mold layer (overmold) 66 is used to at least
partially encapsulate the second die and the first RDL, as shown in
FIG. 8. The second mold layer is formed of a mold compound 72
(which may be the same or a different mold compound than the first
mold layer) and has a first surface 68 and a second surface 70
opposite the first surface.
[0079] One or more second vias 74 are formed in the second mold
layer, using any processes described above with respect to the
first vias, to expose surfaces 36 of the second die and/or the
first RDL. Three second vias 74 are shown in FIG. 9 though the
rightmost via is not labeled. Electrically conductive pillars
(second pillars) 76 and electrically conductive pillar 79 are
formed, using any of the methods described above for the first
pillars, and the pillars fill in the second vias as shown in FIG.
10. FIG. 10 also shows a second redistribution layer (second RDL)
80 which is later applied, but first the pillars 76 and 79 are
formed. After the pillars 76 and 79 are formed a third grinding
process may be used to level the top surface of the second mold
layer and the exposed upper surfaces of the pillars 76 and 79. The
pillars 76 and 79 are formed of an electrically conductive material
78.
[0080] The second RDL 80 may be formed using any of the processes
described above for the first RDL. FIG. 10 shows that the second
RDL electrically couples the second die with the third die through
a path including the pillars 76, the second RDL, pillar 79, the
first RDL, one of the vertical members, and one of the horizontal
members. Other couplings may be made, for instance the second RDL
may also couple the leftmost upper contact of the second die shown
in FIG. 10 with one or more other elements internal to or external
to the package.
[0081] FIG. 11 shows that a third mold layer (overmold) 82 is used
to at least partially encapsulate the second RDL. The third mold
layer is formed of a mold compound 88, which could be the same
material as the first and/or second mold layers or could be formed
of a different material. The third mold layer has a first surface
84 and a second surface 86 opposite the first surface.
[0082] FIG. 12 shows that material is removed from the substrate to
form a through hole 90, forming exposed surfaces 20 of the
horizontal members and vertical members and of the first mold
layer. This may be done using any material removal techniques, such
as laser drilling, etching, and so forth. In the representative
example an etching process is used. Strips 92 of the substrate are
left intact to facilitate further processing. Solder masks 94 are
applied, as shown in FIGS. 13-14, to cover some areas of the bottom
surface of the assembly and to prevent solder balls and/or solder
paste in different areas from contacting one another when the
horizontal and vertical members are later coupled with a
motherboard, printed circuit board (PCB), or some other element.
Any type of solder mask material may be used for the solder
masks.
[0083] In FIG. 14, the strips 92 have been removed, and the package
2 is fully formed. As is seen in FIG. 14, the package is a
three-dimensional (3D) stacked-die embedded package--with the first
and third die located within a first mold layer and the second die
located within a second mold layer atop the first mold layer. The
methods described herein are therefore used, at least in part, to
stack the die within the package. The pillars described above are,
in the representative example, copper pillars--though in other
implementations other electrically conductive materials could be
used. As described above, the package may be coupled with a PCB or
other element using solder or other coupling mechanisms. The
configuration of FIG. 14 shows that either side (top or bottom) of
any die may be coupled with either side (top or bottom) of any
other die using the RDLs, pillars, and/or the horizontal/vertical
members.
[0084] FIGS. 15-31 show a second method of forming semiconductor
package (package) 2. FIG. 31 shows the completed package which is
similar to FIG. 14 which has already been previously described.
[0085] Referring to FIG. 15, the substrate is provided and
electrically conductive elements including horizontal members and
vertical members are coupled therewith, as previously described.
FIG. 16 shows placement of the first and third die, which is
similar to the previously described process.
[0086] FIG. 17 shows a first photoresist layer 96 that has been
formed to at least partially encapsulate or cover the first and
third die and most of the electrically conductive elements. The
first photoresist layer is formed of a photoresist material 104 and
has a first surface 98 and a second surface 100 opposite the first
surface. FIG. 18 shows first vias 102 formed in the first
photoresist layer. These may be formed by patterning and exposing
portions of the photoresist layer and removing some of the
photoresist material after the exposure. FIG. 19 shows first
pillars formed using any of the methods previously described, which
fill the first vias, and in FIG. 20 the first photoresist layer is
fully removed using known processes.
[0087] In FIG. 21 the first mold layer is applied and then a
grinding process may be performed so that the upper surfaces of the
pillars, first mold layer, and vertical members are flush. Thus, at
the method stage shown in FIG. 21 the partially formed package may
have the same configuration as that shown in FIG. 5 of the previous
method. FIGS. 22-23 likewise show similar configurations and
processes as were described previously with respect to FIGS. 6-7,
respectively.
[0088] At FIG. 24 a second photoresist layer 106 is applied. The
second photoresist layer is formed of a photoresist material 114
and includes a first surface 108 and a second surface 110. Second
vias 112 are formed in the second photoresist layer, using any of
processes described above, as shown in FIG. 25. Three second vias
112 are shown in FIG. 25 though the rightmost via is not labeled.
The second vias expose the electrical contacts of the second die
and expose the first RDL (using the rightmost via). Pillars 76/79
are then formed, using any of the processes described above,
filling the second vias, as shown in FIG. 26. The second
photoresist layer is then fully removed and the second mold layer
is applied.
[0089] After this, processing continues as shown in FIGS. 27-31
similar to that already described above for FIGS. 10-14,
respectively. In FIG. 31 the completed package 2 is shown, which to
package 2 of FIG. 14, but made using a different process.
[0090] As described to some extent previously, in implementations
the first die is an HSFET and the second die is an LSFET. In other
implementations these could be reversed such as is shown with the
elements 116 of FIG. 32 with the top FET 118 being an HSFET 120 and
the bottom FET 128 being an LSFET 130. Electrical couplers 138 are
shown which will be coupled with the gate contact 132 and source
contact 134 of the LSFET. The drain contact 136 of the LSFET will
be coupled with the source contact 124 of the HSFET. The gate
contact 122 and drain contact 126 of the HSFET may be coupled with
other elements internal or external to the package. The couplings
between the electrical couplers 138, HSFET, and LSFET are not
shown, but may be formed using any of the previously described
techniques, such that the LSFET may be formed in a first mold
layer, the HSFET in a second mold layer, and so forth, with pillars
coupling the various elements--though these elements are not shown
in FIG. 32. In other implementations one or more of these elements
could be directly stacked and/or soldered together (or otherwise
mechanically/electrically coupled) without using pillars. The
electrical couplers 138 could be part of a molded interconnect
device (MID).
[0091] The methods described herein may be utilized to form an
embedded package within a PCB or may be used to form an
independent, stand-alone package. In various implementations, one
of the basic and novel aspects of the methods of forming a package
described herein is the formation of the package without any PCB
lamination steps/processes. In various implementations, one of the
basic and novel aspects of the methods of forming a package
described herein is the formation of the package without using any
sequential build-up (SBU) laminate substrate and without using SBU
lamination processes. An SBU laminate substrate as used herein is
defined as a multilayer core substrate configured to receive
laminated build-up layers on both a first side and a second side
opposite the first side. SBU lamination processes are defined
herein as coupling one or more die with a multilayer core substrate
and adding one or more build-up layers through a lamination process
to a first side of the multilayer core and adding one or more
build-up layers through a lamination process to a second side of
the multilayer core opposite the first side.
[0092] In implementations any of the solder masks described herein
could be excluded and the remaining elements (such as all elements
shown in FIG. 14 or 31 except the solder mask 94) may form the
completed package. Any of the mold layers described herein may be
formed using compression molding.
[0093] In implementations the packages described herein could
include one or more multi-chip modules (MCMs) instead of or in
addition to the HSFET/LSFET die described herein. In some cases,
multiple die and/or other elements could be mechanically and/or
electrically coupled using the same conductive pillar. The
electrically conductive material of any given pillar could be the
same or different as that of other pillar. The first and second
photoresist layers described above could be formed of the same or
of different photoresist materials.
[0094] In implementations, as may be seen in the drawings, no wires
and no clips are used in the formation of the package(s) described
herein, and there are no wires and no clips in the completed
package(s). As seen in the drawings, forming any of the vias
described herein may expose surfaces of the die and/or surfaces of
one or more of the RDLs.
[0095] Implementations of semiconductor packages may further
include one or more elements for heat dissipation. Referring now to
FIG. 34, a semiconductor package (package) 140 is shown which is a
stacked embedded package 142. Package 140 includes a heat
dissipation device 144 which is also shown at the top of FIG. 33.
Heat dissipation device 144 includes a direct bonded copper (DBC)
substrate 146 which includes a ceramic layer 148 sandwiched between
a first copper layer 150 and a second copper layer 152. The middle
image of FIG. 33 shows a heat dissipation device 154 that includes
the ceramic layer and the first copper layer but not the second
copper layer. The bottom image of FIG. 33 shows a heat dissipation
device 156 that includes the ceramic layer but no copper
layers.
[0096] The ceramic layer of any of the heat dissipation devices
could be formed of, by non-limiting example, Al.sub.2O.sub.3,
Si.sub.3N.sub.4, or AlN. The one or more copper layers could be
formed by plating, sintering, thick film deposition, or some other
material deposition/bonding technique.
[0097] FIG. 34 shows that the heat dissipation device may be
coupled with the second redistribution layer and at least partially
encapsulated in the third mold layer, though with a portion of the
heat dissipation device exposed at an outer surface of the package
through an opening in the third mold layer. In the representative
example shown in FIG. 34, an upper surface of the first copper
layer 150 is exposed through an opening 83 in the third mold layer.
Package 140 includes heat dissipation device 144, which is a DBC
substrate with two copper layers. When such a heat dissipation
device is used the second copper layer may be bonded with the
second redistribution layer through soldering or sintering or any
other method disclosed in this document. In implementations of
packages that include heat dissipation devices 154 or 156, there is
no second copper layer and the ceramic layer of the heat
dissipation device may be bonded with the second redistribution
layer using a thermally conductive adhesive, such as a thermally
conductive epoxy or paste or the like.
[0098] Packages which include heat dissipation devices may be
particularly useful when the second semiconductor die 32 is a
power/high voltage die 158 as in FIG. 34, since a power
semiconductor die may need greater heat dissipation than other
semiconductor die. In implementations the heat dissipation device
may act as a heat sink to draw heat away from the power
semiconductor die. In implementations the electrical couplers 46
(or other electrical couplers), instead of being solder bumps 48,
could be formed of electrically conductive pillars 160 as shown in
FIG. 34. These could be any shape, such as cylindrical or cuboidal,
and could be formed of any electrically conductive material, such
as copper. In implementations of forming semiconductor packages one
or more layers 162 may be formed between the electrically
conductive elements 12 and the substrate 6 as seen in FIG. 34, such
as an adhesive or the like, which may or may not be removed
thereafter during the processing steps shown in FIGS. 12 and 29,
respectively, though if the adhesive is electrically conductive
than portions of it may be removed while other portions (directly
below conductive elements 12) could remain, such as through one or
more additional processing steps which may or may not include
additional patterning/etching steps.
[0099] Any of the first vias 58 in the first mold layer, second
vias 74 in the second mold layer, and/or second vias 112 in the
second mold layer may be through-mold vias (TMVs) formed using, by
non-limiting examples, a mechanical process and/or a chemical
process, such as laser drilling, wet etching, plasma etching, or
the like.
[0100] In places where the description above refers to particular
implementations of embedded stacked die packages and related
methods and implementing components, sub-components, methods and
sub-methods, it should be readily apparent that a number of
modifications may be made without departing from the spirit thereof
and that these implementations, implementing components,
sub-components, methods and sub-methods may be applied to other
embedded stacked die packages and related methods.
* * * * *