U.S. patent application number 15/361842 was filed with the patent office on 2018-05-31 for three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof.
The applicant listed for this patent is SANDISK TECHNOLOGIES LLC. Invention is credited to Kengo Kajiwara, Raghuveer S. Makala, Masanori Tsutsumi.
Application Number | 20180151588 15/361842 |
Document ID | / |
Family ID | 62190471 |
Filed Date | 2018-05-31 |
United States Patent
Application |
20180151588 |
Kind Code |
A1 |
Tsutsumi; Masanori ; et
al. |
May 31, 2018 |
THREE-DIMENSIONAL MEMORY DEVICE WITH DISCRETE SELF-ALIGNED CHARGE
STORAGE ELEMENTS AND METHOD OF MAKING THEREOF
Abstract
A memory opening can be formed through an alternating stack of
insulating layers and sacrificial material layers over a substrate.
A material layer stack containing, from outside to inside, an
aluminum oxide tunneling dielectric layer, a silicon-containing
tunneling dielectric layer, and a vertical semiconductor channel is
formed within the memory opening. After forming backside recesses
by removing the sacrificial material layers, charge trapping
material portions are formed on physically exposed surfaces of the
aluminum oxide tunneling dielectric layer by employing a selective
silicon nitride deposition process. A backside blocking dielectric
layer and electrically conductive layers are formed in the backside
recesses. The charge trapping material portions are discrete
silicon nitride portions located at levels of the electrically
conductive layers and vertically spaced from one another by the
insulating layers.
Inventors: |
Tsutsumi; Masanori;
(Yokkaichi, JP) ; Kajiwara; Kengo; (Yokkaichi,
JP) ; Makala; Raghuveer S.; (Campbell, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SANDISK TECHNOLOGIES LLC |
Plano |
TX |
US |
|
|
Family ID: |
62190471 |
Appl. No.: |
15/361842 |
Filed: |
November 28, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/0847 20130101;
H01L 27/11582 20130101; H01L 21/0223 20130101; H01L 29/513
20130101; H01L 29/7827 20130101; H01L 27/11565 20130101; H01L
21/0217 20130101; H01L 27/11568 20130101; H01L 29/40117 20190801;
H01L 21/02236 20130101; H01L 29/4234 20130101; H01L 29/6656
20130101; H01L 21/0228 20130101; H01L 29/517 20130101; H01L 29/518
20130101; H01L 21/02164 20130101; H01L 27/11573 20130101; H01L
21/02178 20130101 |
International
Class: |
H01L 27/115 20060101
H01L027/115; H01L 29/51 20060101 H01L029/51; H01L 29/423 20060101
H01L029/423; H01L 29/08 20060101 H01L029/08; H01L 21/28 20060101
H01L021/28; H01L 21/02 20060101 H01L021/02; H01L 29/66 20060101
H01L029/66 |
Claims
1. A three-dimensional memory device comprising: an alternating
stack of insulating layers and electrically conductive layers
located over a substrate; a vertical semiconductor channel
vertically extending through the alternating stack; a tunneling
dielectric layer stack including a silicon-containing tunneling
dielectric layer and an aluminum oxide tunneling dielectric layer
and laterally surrounding the vertical semiconductor channel; and
charge trapping material portions located at each level of the
electrically conductive layers that are located at, or above a
horizontal plane including a bottom surface of the aluminum oxide
tunneling dielectric layer, comprising silicon nitride, directly
contacting portions of an outer sidewall of the aluminum oxide
tunneling dielectric layer, and vertically spaced from one another,
wherein the three-dimensional memory device comprises at least one
feature selected from: a first feature that an entirety of an inner
sidewall of the aluminum oxide tunneling dielectric layer directly
contacts an outer sidewall of the silicon containing tunneling
dielectric layer; a second feature that an entire inner sidewall of
each of the charge trapping material portions directly contacts a
respective portion of the outer sidewall of the aluminum oxide
tunneling dielectric layer; a third feature that an entirety of the
aluminum oxide tunneling dielectric layer is more proximal to the
vertical semiconductor channel than any of the insulating layers is
to the vertical semiconductor channel; and a fourth feature that
sidewalls of the insulating layers are not in direct contact with
any surface of the charge trapping material portions.
2. The three-dimensional memory device of claim 1, further
comprising discrete dielectric liner portions located at each level
of the insulating layers that are located at, or above the
horizontal plane including the bottom surface of the aluminum oxide
tunneling dielectric layer.
3. The three-dimensional memory device of claim 2, wherein: a set
of the discrete dielectric liner portions and the charge trapping
material portions contacts an entirety of the outer sidewall of the
aluminum oxide tunneling dielectric layer; one of the set of the
dielectric liner portions is be located between a pair of discrete,
nearest neighbor charge trapping material portions to vertically
separate the pair of nearest neighbor charge trapping material
portions; the insulating layers comprise a first silicon oxide
material; and the discrete dielectric liner portions comprise a
second silicon oxide material.
4. The three-dimensional memory device of claim 1, further
comprising a backside blocking dielectric layer located between
each vertically neighboring pair of an insulating layer and an
electrically conductive layer and contacting an outer sidewall of
each of the charge trapping material portions.
5. The three-dimensional memory device of claim 4, wherein: the
backside blocking dielectric layer comprises a layer stack of a
backside silicon oxide layer and a backside dielectric metal oxide
layer; the backside silicon oxide layer contacts horizontal
surfaces of the insulating layers; and the backside dielectric
metal oxide layer contacts horizontal surfaces of the electrically
conductive layers.
6. The three-dimensional memory device of claim 4, wherein the
backside blocking dielectric layer comprises backside blocking
dielectric spacers laterally surrounding, and contacting an outer
sidewall of, a respective one of the charge trapping material
portions, wherein the backside blocking dielectric spacers comprise
a dielectric material comprising silicon and oxygen.
7. The three-dimensional memory device of claim 1, further
comprising: an epitaxial channel portion underlying, and
contacting, the vertical semiconductor channel; and a tubular
dielectric spacer located at a level of a bottommost electrically
conductive layer of the alternating stack, laterally surrounding
the epitaxial channel portion, and comprising a dielectric oxide of
a semiconductor material of the epitaxial channel portion.
8. The three-dimensional memory device of claim 1, wherein each of
the charge trapping material portions has a tubular shape and has a
uniform thickness throughout.
9. The three-dimensional memory device of claim 1, further
comprising: a backside contact trench vertically extending through
the alternating stack; an insulating spacer located at a periphery
of the backside contact trench; a backside contact via structure
laterally surrounded by the insulating spacer; and a source region
located in a portion of the substrate underlying the backside
contact trench and contacting the backside contact via
structure.
10. The three-dimensional memory device of claim 1, wherein the
alternating stack comprises a terrace region in which each
electrically conductive layer other than a topmost electrically
conductive layer within the alternating stack laterally extends
farther than any overlying electrically conductive layers within
the alternating stack, and the terrace region includes stepped
surfaces of the alternating stack that continuously extend from a
bottommost layer within the alternating stack to a topmost layer
within the alternating stack.
11. The three-dimensional memory device of claim 1, wherein: the
three-dimensional memory device comprises a monolithic
three-dimensional NAND memory device; the electrically conductive
layers comprise, or are electrically connected to, a respective
word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate; the monolithic
three-dimensional NAND memory device comprises an array of
monolithic three-dimensional NAND strings over the silicon
substrate; at least one memory cell in a first device level of the
array of monolithic three-dimensional NAND strings is located over
another memory cell in a second device level of the array of
monolithic three-dimensional NAND strings; the silicon substrate
contains an integrated circuit comprising a driver circuit for the
memory device located thereon; the electrically conductive layers
comprise a plurality of control gate electrodes having a strip
shape extending substantially parallel to the top surface of the
substrate, the plurality of control gate electrodes comprise at
least a first control gate electrode located in the first device
level and a second control gate electrode located in the second
device level; and the array of monolithic three-dimensional NAND
strings comprises: a plurality of semiconductor channels, wherein
at least one end portion of each of the plurality of semiconductor
channels extends substantially perpendicular to a top surface of
the substrate, and a plurality of charge storage elements, each
charge storage element located adjacent to a respective one of the
plurality of semiconductor channels.
12.-22. (canceled)
23. The three-dimensional memory device of claim 1, wherein the
tunneling dielectric layer stack is located between the vertical
semiconductor channel and the charge trapping material
portions.
24. The three-dimensional memory device of claim 1, wherein each of
the charge trapping material portions is more distal from the
vertical semiconductor channel than the tunneling dielectric layer
is from the vertical semiconductor channel.
25. The three-dimensional memory device of claim 1, wherein the
three-dimensional memory device comprises the first feature.
26. The three-dimensional memory device of claim 1, wherein the
three-dimensional memory device comprises the second feature.
27. The three-dimensional memory device of claim 1, wherein one of
the charge trapping material portions includes a topmost surface
that is coplanar with a bottom surface of one of the insulating
layers and a bottommost surface that is coplanar with a top surface
of another of the insulating layers.
28. The three-dimensional memory device of claim 1, wherein the
three-dimensional memory device comprises the third feature.
29. The three-dimensional memory device of claim 1, wherein the
three-dimensional memory device comprises the fourth feature.
30. The three-dimensional memory device of claim 2, wherein each of
the discrete dielectric liner portions has an inner sidewall that
directly contacts portions of the outer sidewall of the aluminum
oxide tunneling dielectric layer.
31. The three-dimensional memory device of claim 2, wherein each
discrete dielectric liner portion that is located between a
vertically neighboring pair of charge trapping material portions
continuously extends between the vertically neighboring pair of
charge trapping material portions as a single continuous
structure.
32. A three-dimensional memory device comprising: an alternating
stack of insulating layers and electrically conductive layers
located over a substrate; a vertical semiconductor channel
vertically extending through the alternating stack; a tunneling
dielectric layer stack including a silicon-containing tunneling
dielectric layer and an aluminum oxide tunneling dielectric layer
and laterally surrounding the vertical semiconductor channel;
charge trapping material portions located at each level of the
electrically conductive lavers that are located at, or above a
horizontal plane including a bottom surface of the aluminum oxide
tunneling dielectric layer, comprising silicon nitride, directly
contacting portions of an outer sidewall of the aluminum oxide
tunneling dielectric layer, and vertically spaced from one another;
and discrete dielectric liner portions located at each level of the
insulating layers that are located at, or above the horizontal
plane including the bottom surface of the aluminum oxide tunneling
dielectric layer, wherein each charge trapping material portion
that is located between a vertically neighboring pair of discrete
dielectric liner portions includes an inner sidewall that
continuously extends between the vertically neighboring pair of
discrete dielectric liner portions such that an entirety of the
inner sidewall contacts a respective portion of the outer sidewall
of the aluminum oxide tunneling dielectric layer.
33. (canceled)
Description
FIELD
[0001] The present disclosure relates generally to the field of
three-dimensional memory devices and specifically to
three-dimensional memory devices employing self-aligned charge
storage elements and methods of making thereof.
BACKGROUND
[0002] Three-dimensional vertical NAND strings having one bit per
cell are disclosed in an article by T. Endoh et al., titled "Novel
Ultra High Density Memory With A Stacked-Surrounding Gate
Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36.
[0003] Charge leakage across different levels of control gate
electrodes in a charge storage material layer can degrade data
retention and data accuracy in a three-dimensional memory device.
Methods for improving charge retention and data accuracy in a
three-dimensional memory device are thus desired.
SUMMARY
[0004] According to an aspect of the present disclosure, a
three-dimensional memory device is provided, which comprises: an
alternating stack of insulating layers and electrically conductive
layers located over a substrate; a vertical semiconductor channel
vertically extending through a predominant subset of layers within
the alternating stack; a tunneling dielectric layer stack including
a silicon-containing tunneling dielectric layer and an aluminum
oxide tunneling dielectric layer and laterally surrounding the
vertical semiconductor channel; and charge trapping material
portions located at each level of the electrically conductive
layers that are located at, or above a horizontal plane including a
bottom surface of the aluminum oxide tunneling dielectric layer,
comprising silicon nitride, contacting portions of an outer
sidewall of the aluminum oxide tunneling dielectric layer, and
vertically spaced from one another.
[0005] According to another aspect of the present disclosure, a
method of forming a three-dimensional memory device is provided. An
alternating stack of insulating layers and sacrificial material
layers is formed over a substrate. A memory opening is formed
through the alternating stack. A material layer stack comprising,
from outside to inside, an aluminum oxide tunneling dielectric
layer, a silicon-containing tunneling dielectric layer, and a
vertical semiconductor channel is formed within the memory opening.
Backside recesses are formed by removing the sacrificial material
layers selective to the insulating layers. Charge trapping material
portions are formed on physically exposed surfaces of the aluminum
oxide tunneling dielectric layer by employing a selective silicon
nitride deposition process in which silicon nitride grows from the
physically exposed surfaces of the aluminum oxide tunneling
dielectric layer while not growing from surfaces of the insulating
layers. A backside blocking dielectric layer is formed over the
charge trapping material portions. Electrically conductive layers
are formed in remaining volumes of the backside recesses.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a schematic vertical cross-sectional view of a
first exemplary structure after formation of at least one
peripheral device, a semiconductor material layer, and a gate
dielectric layer according to a first embodiment of the present
disclosure.
[0007] FIG. 2 is a schematic vertical cross-sectional view of the
first exemplary structure after formation of an alternating stack
of insulating layers and sacrificial material layers according to
the first embodiment of the present disclosure.
[0008] FIG. 3 is a schematic vertical cross-sectional view of the
first exemplary structure after formation of stepped terraces and a
retro-stepped dielectric material portion according to the first
embodiment of the present disclosure.
[0009] FIG. 4A is a schematic vertical cross-sectional view of the
first exemplary structure after formation of memory openings and
support openings according to the first embodiment of the present
disclosure.
[0010] FIG. 4B is a top-down view of the first exemplary structure
of FIG. 4A. The vertical plane A-A' is the plane of the
cross-section for FIG. 4A.
[0011] FIGS. 5A-5H are sequential schematic vertical
cross-sectional views of a memory opening during formation of a
memory opening fill structure according to the first embodiment of
the present disclosure.
[0012] FIG. 6 is a schematic vertical cross-sectional view of the
first exemplary structure after formation of the memory opening
fill structures according to the first embodiment of the present
disclosure.
[0013] FIG. 7A is a schematic vertical cross-sectional view of the
first exemplary structure after formation of backside trenches
according to the first embodiment of the present disclosure.
[0014] FIG. 7B is a top-down view of the first exemplary structure
of FIG. 7A. The vertical plane A-A' is the plane of the
cross-section for FIG. 7A.
[0015] FIGS. 8A-8F are sequential vertical cross-sectional views of
a memory opening within the first exemplary structure during
various processing steps employed to form discrete charge trapping
material portions, a backside blocking dielectric layer, and
electrically conductive layers according to the first embodiment of
the present disclosure.
[0016] FIG. 9 is a vertical cross-sectional view of the first
exemplary structure after formation of electrically conductive
layers according to the first embodiment of the present
disclosure.
[0017] FIG. 10 is a vertical cross-sectional view of the first
exemplary structure after removal of a deposited conductive
material from within the backside trenches according to the first
embodiment of the present disclosure.
[0018] FIG. 11 is a vertical cross-sectional view of the first
exemplary structure after formation of an insulating spacer, a
source region, and a backside contact trench according to the first
embodiment of the present disclosure.
[0019] FIG. 12A is a vertical cross-sectional view of the first
exemplary structure after formation of additional contact via
structures according to the first embodiment of the present
disclosure.
[0020] FIG. 12B is a top-down view of the first exemplary structure
of FIG. 12A. The vertical plane A-A' is the plane of the
cross-section for FIG. 12A.
[0021] FIGS. 13A-13D are sequential vertical cross-sectional views
of a memory opening within a second exemplary structure during
various processing steps employed to form discrete charge trapping
material portions, blocking dielectric spacers, a backside blocking
dielectric layer, and electrically conductive layers according to a
second embodiment of the present disclosure.
DETAILED DESCRIPTION
[0022] As discussed above, the present disclosure is directed to
three-dimensional memory devices employing discrete self-aligned
charge storage elements and methods of making thereof, the various
aspects of which are described below. The embodiments of the
disclosure can be employed to form various structures including a
multilevel memory structure, non-limiting examples of which include
semiconductor devices such as three-dimensional monolithic memory
array devices comprising a plurality of NAND memory strings. The
drawings are not drawn to scale. Multiple instances of an element
may be duplicated where a single instance of the element is
illustrated, unless absence of duplication of elements is expressly
described or clearly indicated otherwise. Ordinals such as "first,"
"second," and "third" are employed merely to identify similar
elements, and different ordinals may be employed across the
specification and the claims of the instant disclosure. As used
herein, a first element located "on" a second element can be
located on the exterior side of a surface of the second element or
on the interior side of the second element. As used herein, a first
element is located "directly on" a second element if there exist a
physical contact between a surface of the first element and a
surface of the second element.
[0023] As used herein, a "layer" refers to a material portion
including a region having a thickness. A layer may extend over the
entirety of an underlying or overlying structure, or may have an
extent less than the extent of an underlying or overlying
structure. For example, a layer may be located between any pair of
horizontal planes between, or at, a top surface and a bottom
surface of the continuous structure. A layer may extend
horizontally, vertically, and/or along a tapered surface. A
substrate may be a layer, may include one or more layers therein,
or may have one or more layer thereupon, thereabove, and/or
therebelow.
[0024] A monolithic three-dimensional memory array is one in which
multiple memory levels are formed above a single substrate, such as
a semiconductor wafer, with no intervening substrates. The term
"monolithic" means that layers of each level of the array are
directly deposited on the layers of each underlying level of the
array. In contrast, two dimensional arrays may be formed separately
and then packaged together to form a non-monolithic memory device.
For example, non-monolithic stacked memories have been constructed
by forming memory levels on separate substrates and vertically
stacking the memory levels, as described in U.S. Pat. No. 5,915,167
titled "Three-dimensional Structure Memory." The substrates may be
thinned or removed from the memory levels before bonding, but as
the memory levels are initially formed over separate substrates,
such memories are not true monolithic three-dimensional memory
arrays. The various three-dimensional memory devices of the present
disclosure include a monolithic three-dimensional NAND string
memory device, and can be fabricated employing the various
embodiments described herein.
[0025] Referring to FIG. 1, a first exemplary structure according
to an embodiment of the present disclosure is illustrated, which
can be employed, for example, to fabricate a device structure
containing vertical NAND memory devices. The first exemplary
structure includes a substrate, which can be a semiconductor
substrate (9, 10). The substrate can include a substrate
semiconductor layer 9. The substrate semiconductor layer 9 maybe a
semiconductor wafer or a semiconductor material layer, and can
include at least one elemental semiconductor material (e.g., single
crystal silicon wafer or layer), at least one III-V compound
semiconductor material, at least one II-VI compound semiconductor
material, at least one organic semiconductor material, or other
semiconductor materials known in the art. The substrate can have a
major surface 7, which can be, for example, a topmost surface of
the substrate semiconductor layer 9. The major surface 7 can be a
semiconductor surface. In one embodiment, the major surface 7 can
be a single crystalline semiconductor surface, such as a single
crystalline semiconductor surface.
[0026] As used herein, a "semiconducting material" refers to a
material having electrical conductivity in the range from
1.0.times.10.sup.-6 S/cm to 1.0.times.10.sup.5 S/cm. As used
herein, a "semiconductor material" refers to a material having
electrical conductivity in the range from 1.0.times.10.sup.-6 S/cm
to 1.0.times.10.sup.5 S/cm in the absence of electrical dopants
therein, and is capable of producing a doped material having
electrical conductivity in a range from 1.0 S/cm to
1.0.times.10.sup.5 S/cm upon suitable doping with an electrical
dopant. As used herein, an "electrical dopant" refers to a p-type
dopant that adds a hole to a valence band within a band structure,
or an n-type dopant that adds an electron to a conduction band
within a band structure. As used herein, a "conductive material"
refers to a material having electrical conductivity greater than
1.0.times.10.sup.5 S/cm. As used herein, an "insulator material" or
a "dielectric material" refers to a material having electrical
conductivity less than 1.0.times.10.sup.-6 S/cm. As used herein, a
"heavily doped semiconductor material" refers to a semiconductor
material that is doped with electrical dopant at a sufficiently
high atomic concentration to become a conductive material, i.e., to
have electrical conductivity greater than 1.0.times.10.sup.5 S/cm.
A "doped semiconductor material" may be a heavily doped
semiconductor material, or may be a semiconductor material that
includes electrical dopants (i.e., p-type dopants and/or n-type
dopants) at a concentration that provides electrical conductivity
in the range from 1.0.times.10.sup.-6 S/cm to 1.0.times.10.sup.5
S/cm. An "intrinsic semiconductor material" refers to a
semiconductor material that is not doped with electrical dopants.
Thus, a semiconductor material may be semiconducting or conductive,
and may be an intrinsic semiconductor material or a doped
semiconductor material. A doped semiconductor material can be
semiconducting or conductive depending on the atomic concentration
of electrical dopants therein. As used herein, a "metallic
material" refers to a conductive material including at least one
metallic element therein. All measurements for electrical
conductivities are made at the standard condition.
[0027] At least one semiconductor device 700 for a peripheral
circuitry can be formed on a portion of the substrate semiconductor
layer 9. The at least one semiconductor device can include, for
example, field effect transistors. For example, at least one
shallow trench isolation structure 120 can be formed by etching
portions of the substrate semiconductor layer 9 and depositing a
dielectric material therein. A gate dielectric layer, at least one
gate conductor layer, and a gate cap dielectric layer can be formed
over the substrate semiconductor layer 9, and can be subsequently
patterned to form at least one gate structure (150, 152, 154, 158),
each of which can include a gate dielectric 150, a gate electrode
(152, 154), and a gate cap dielectric 158. The gate electrode (152,
154) may include a stack of a first gate electrode portion 152 and
a second gate electrode portion 154. At least one gate spacer 156
can be formed around the at least one gate structure (150, 152,
154, 158) by depositing and anisotropically etching a dielectric
liner. Active regions 130 can be formed in upper portions of the
substrate semiconductor layer 9, for example, by introducing
electrical dopants employing the at least one gate structure (150,
152, 154, 158) as masking structures. Additional masks may be
employed as needed. The active region 130 can include source
regions and drain regions of field effect transistors. A first
dielectric liner 161 and a second dielectric liner 162 can be
optionally formed. Each of the first and second dielectric liners
(161, 162) can comprise a silicon oxide layer, a silicon nitride
layer, and/or a dielectric metal oxide layer. As used herein,
silicon oxide includes silicon dioxide as well as
non-stoichiometric silicon oxides having more or less than two
oxygen atoms for each silicon atoms. Silicon dioxide is preferred.
In an illustrative example, the first dielectric liner 161 can be a
silicon oxide layer, and the second dielectric liner 162 can be a
silicon nitride layer. The least one semiconductor device for the
peripheral circuitry can contain a driver circuit for memory
devices to be subsequently formed, which can include at least one
NAND device.
[0028] A dielectric material such as silicon oxide can be deposited
over the at least one semiconductor device, and can be subsequently
planarized to form a planarization dielectric layer 170. In one
embodiment the planarized top surface of the planarization
dielectric layer 170 can be coplanar with a top surface of the
dielectric liners (161, 162). Subsequently, the planarization
dielectric layer 170 and the dielectric liners (161, 162) can be
removed from an area to physically expose a top surface of the
substrate semiconductor layer 9. As used herein, a surface is
"physically exposed" if the surface is in physical contact with
vacuum, or a gas phase material (such as air).
[0029] An optional semiconductor material layer 10 can be formed on
the top surface of the substrate semiconductor layer 9 by
deposition of a single crystalline semiconductor material, for
example, by selective epitaxy. The deposited semiconductor material
can be the same as, or can be different from, the semiconductor
material of the substrate semiconductor layer 9. The deposited
semiconductor material can be any material that can be employed for
the semiconductor substrate layer 9 as described above. The single
crystalline semiconductor material of the semiconductor material
layer 10 can be in epitaxial alignment with the single crystalline
structure of the substrate semiconductor layer 9. Portions of the
deposited semiconductor material located above the top surface of
the planarization dielectric layer 170 can be removed, for example,
by chemical mechanical planarization (CMP). In this case, the
semiconductor material layer 10 can have a top surface that is
coplanar with the top surface of the planarization dielectric layer
170.
[0030] The region (i.e., area) of the at least one semiconductor
device 700 is herein referred to as a peripheral device region 200.
The region in which a memory array is subsequently formed is herein
referred to as a memory array region 100. A contact region 300 for
subsequently forming stepped terraces of electrically conductive
layers can be provided between the memory array region 100 and the
peripheral device region 200. Optionally, a gate dielectric layer
12 can be formed above the semiconductor material layer 10 and the
planarization dielectric layer 170. The gate dielectric layer 12
can be, for example, silicon oxide layer. The thickness of the gate
dielectric layer 12 can be in a range from 3 nm to 30 nm, although
lesser and greater thicknesses can also be employed.
[0031] Referring to FIG. 2, a stack of an alternating plurality of
first material layers (which can be insulating layers 32) and
second material layers (which can be sacrificial material layer 42)
is formed over the top surface of the substrate, which can be, for
example, on the top surface of the gate dielectric layer 12. As
used herein, a "material layer" refers to a layer including a
material throughout the entirety thereof. As used herein, an
alternating plurality of first elements and second elements refers
to a structure in which instances of the first elements and
instances of the second elements alternate. Each instance of the
first elements that is not an end element of the alternating
plurality is adjoined by two instances of the second elements on
both sides, and each instance of the second elements that is not an
end element of the alternating plurality is adjoined by two
instances of the first elements on both ends. The first elements
may have the same thickness thereamongst, or may have different
thicknesses. The second elements may have the same thickness
thereamongst, or may have different thicknesses. The alternating
plurality of first material layers and second material layers may
begin with an instance of the first material layers or with an
instance of the second material layers, and may end with an
instance of the first material layers or with an instance of the
second material layers. In one embodiment, an instance of the first
elements and an instance of the second elements may form a unit
that is repeated with periodicity within the alternating
plurality.
[0032] Each first material layer includes a first material, and
each second material layer includes a second material that is
different from the first material. In one embodiment, each first
material layer can be an insulating layer 32, and each second
material layer can be a sacrificial material layer. In this case,
the stack can include an alternating plurality of insulating layers
32 and sacrificial material layers 42, and constitutes a prototype
stack of alternating layers comprising insulating layers 32 and
sacrificial material layers 42. As used herein, a "prototype"
structure or an "in-process" structure refers to a transient
structure that is subsequently modified in the shape or composition
of at least one component therein.
[0033] The stack of the alternating plurality is herein referred to
as an alternating stack (32, 42). In one embodiment, the
alternating stack (32, 42) can include insulating layers 32
composed of the first material, and sacrificial material layers 42
composed of a second material different from that of insulating
layers 32. The first material of the insulating layers 32 can be at
least one insulating material. As such, each insulating layer 32
can be an insulating material layer. Insulating materials that can
be employed for the insulating layers 32 include, but are not
limited to, silicon oxide (including doped or undoped silicate
glass), silicon nitride, silicon oxynitride, organosilicate glass
(OSG), spin-on dielectric materials, dielectric metal oxides that
are commonly known as high dielectric constant (high-k) dielectric
oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates
thereof, dielectric metal oxynitrides and silicates thereof, and
organic insulating materials. In one embodiment, the first material
of the insulating layers 32 can be silicon oxide.
[0034] The second material of the sacrificial material layers 42 is
a sacrificial material that can be removed selective to the first
material of the insulating layers 32. As used herein, a removal of
a first material is "selective to" a second material if the removal
process removes the first material at a rate that is at least twice
the rate of removal of the second material. The ratio of the rate
of removal of the first material to the rate of removal of the
second material is herein referred to as a "selectivity" of the
removal process for the first material with respect to the second
material.
[0035] The sacrificial material layers 42 may comprise an
insulating material, a semiconductor material, or a conductive
material. The second material of the sacrificial material layers 42
can be subsequently replaced with electrically conductive
electrodes which can function, for example, as control gate
electrodes of a vertical NAND device. Non-limiting examples of the
second material include silicon nitride, an amorphous semiconductor
material (such as amorphous silicon), and a polycrystalline
semiconductor material (such as polysilicon). In one embodiment,
the sacrificial material layers 42 can be spacer material layers
that comprise silicon nitride or a semiconductor material including
at least one of silicon and germanium.
[0036] In one embodiment, the insulating layers 32 can include
silicon oxide, and sacrificial material layers can include silicon
nitride sacrificial material layers. The first material of the
insulating layers 32 can be deposited, for example, by chemical
vapor deposition (CVD). For example, if silicon oxide is employed
for the insulating layers 32, tetraethyl orthosilicate (TEOS) can
be employed as the precursor material for the CVD process. The
second material of the sacrificial material layers 42 can be
formed, for example, CVD or atomic layer deposition (ALD).
[0037] The sacrificial material layers 42 can be suitably patterned
so that conductive material portions to be subsequently formed by
replacement of the sacrificial material layers 42 can function as
electrically conductive electrodes, such as the control gate
electrodes of the monolithic three-dimensional NAND string memory
devices to be subsequently formed. The sacrificial material layers
42 may comprise a portion having a strip shape extending
substantially parallel to the major surface 7 of the substrate.
[0038] The thicknesses of the insulating layers 32 and the
sacrificial material layers 42 can be in a range from 20 nm to 50
nm, although lesser and greater thicknesses can be employed for
each insulating layer 32 and for each sacrificial material layer
42. The number of repetitions of the pairs of an insulating layer
32 and a sacrificial material layer (e.g., a control gate electrode
or a sacrificial material layer) 42 can be in a range from 2 to
1,024, and typically from 8 to 256, although a greater number of
repetitions can also be employed. The top and bottom gate
electrodes in the stack may function as the select gate electrodes.
In one embodiment, each sacrificial material layer 42 in the
alternating stack (32, 42) can have a uniform thickness that is
substantially invariant within each respective sacrificial material
layer 42.
[0039] While the present disclosure is described employing an
embodiment in which the spacer material layers are sacrificial
material layers 42 that are subsequently replaced with electrically
conductive layers, embodiments are expressly contemplated herein in
which the sacrificial material layers are formed as electrically
conductive layers. In this case, steps for replacing the spacer
material layers with electrically conductive layers can be
omitted.
[0040] Optionally, an insulating cap layer 70 can be formed over
the alternating stack (32, 42). The insulating cap layer 70
includes a dielectric material that is different from the material
of the sacrificial material layers 42. In one embodiment, the
insulating cap layer 70 can include a dielectric material that can
be employed for the insulating layers 32 as described above. The
insulating cap layer 70 can have a greater thickness than each of
the insulating layers 32. The insulating cap layer 70 can be
deposited, for example, by chemical vapor deposition. In one
embodiment, the insulating cap layer 70 can be a silicon oxide
layer.
[0041] Referring to FIG. 3, a stepped cavity can be formed within
the contact region 300 which is located between the memory array
region 100 and the peripheral device region 200 containing the at
least one semiconductor device for the peripheral circuitry. The
stepped cavity can have various stepped surfaces such that the
horizontal cross-sectional shape of the stepped cavity changes in
steps as a function of the vertical distance from the top surface
of the substrate (9, 10). In one embodiment, the stepped cavity can
be formed by repetitively performing a set of processing steps. The
set of processing steps can include, for example, an etch process
of a first type that vertically increases the depth of a cavity by
one or more levels, and an etch process of a second type that
laterally expands the area to be vertically etched in a subsequent
etch process of the first type. As used herein, a "level" of a
structure including alternating plurality is defined as the
relative position of a pair of a first material layer and a second
material layer within the structure.
[0042] After formation of the stepped cavity, a peripheral portion
of the alternating stack (32, 42) can have stepped surfaces after
formation of the stepped cavity. As used herein, "stepped surfaces"
refer to a set of surfaces that include at least two horizontal
surfaces and at least two vertical surfaces such that each
horizontal surface is adjoined to a first vertical surface that
extends upward from a first edge of the horizontal surface, and is
adjoined to a second vertical surface that extends downward from a
second edge of the horizontal surface. A "stepped cavity" refers to
a cavity having stepped surfaces.
[0043] A terrace region is formed by patterning the alternating
stack (32, 42). Each sacrificial material layer 42 other than a
topmost sacrificial material layer 42 within the alternating stack
(32, 42) laterally extends farther than any overlying sacrificial
material layer 42 within the alternating stack (32, 42). The
terrace region includes stepped surfaces of the alternating stack
(32, 42) that continuously extend from a bottommost layer within
the alternating stack (32, 42) to a topmost layer within the
alternating stack (32, 42). Each sacrificial material layer 42
other than the topmost sacrificial material layer 42 within the
alternating stack (32, 42) laterally extends farther than any
overlying sacrificial material layer 42 within the alternating
stack (32, 42).
[0044] A retro-stepped dielectric material portion 65 (i.e., an
insulating fill material portion) can be formed in the stepped
cavity by deposition of a dielectric material therein. For example,
a dielectric material such as silicon oxide can be deposited in the
stepped cavity. Excess portions of the deposited dielectric
material can be removed from above the top surface of the
insulating cap layer 70, for example, by chemical mechanical
planarization (CMP). The remaining portion of the deposited
dielectric material filling the stepped cavity constitutes the
retro-stepped dielectric material portion 65. As used herein, a
"retro-stepped" element refers to an element that has stepped
surfaces and a horizontal cross-sectional area that increases
monotonically as a function of a vertical distance from a top
surface of a substrate on which the element is present. If silicon
oxide is employed for the retro-stepped dielectric material portion
65, the silicon oxide of the retro-stepped dielectric material
portion 65 may, or may not, be doped with dopants such as B, P,
and/or F.
[0045] Optionally, drain select level isolation structures 72
(shown in FIG. 12B) can be formed through the insulating cap layer
70 and a subset of the sacrificial material layers 42 located at
drain select levels, either at this stage of the process or in a
later stage of the process. The drain select level isolation
structures 72 can be formed, for example, by forming drain select
level isolation trenches and filling the drain select level
isolation trenches with a dielectric material such as silicon
oxide. Excess portions of the dielectric material can be removed
from above the top surface of the insulating cap layer 70.
[0046] Referring to FIGS. 4A and 4B, a lithographic material stack
(not shown) including at least a photoresist layer can be formed
over the insulating cap layer 70 and the retro-stepped dielectric
material portion 65, and can be lithographically patterned to form
openings therein. The openings include a first set of openings
formed over the memory array region 100 and a second set of
openings formed over the contact region 300. The pattern in the
lithographic material stack can be transferred through the
insulating cap layer 70 or the retro-stepped dielectric material
portion 65, and through the alternating stack (32, 42) by at least
one anisotropic etch that employs the patterned lithographic
material stack as an etch mask. Portions of the alternating stack
(32, 42) underlying the openings in the patterned lithographic
material stack are etched to form memory openings 49 and support
openings 19. As used herein, a "memory opening" refers to a
structure in which memory elements, such as a memory stack
structure, is subsequently formed. As used herein, a "support
opening" refers to a structure in which a support structure (such
as a support pillar structure) that mechanically supports other
elements is subsequently formed. The memory openings 49 are formed
through the insulating cap layer 70 and the entirety of the
alternating stack (32, 42) in the memory array region 100. The
support openings 19 are formed through the retro-stepped dielectric
material portion 65 and the portion of the alternating stack (32,
42) that underlie the stepped surfaces in the contact region
300.
[0047] The memory openings 49 extend through the entirety of the
alternating stack (32, 42). The support openings 19 extend through
a subset of layers within the alternating stack (32, 42). The
chemistry of the anisotropic etch process employed to etch through
the materials of the alternating stack (32, 42) can alternate to
optimize etching of the first and second materials in the
alternating stack (32, 42). The anisotropic etch can be, for
example, a series of reactive ion etches. The sidewalls of the
memory openings 49 and the support openings 19 can be substantially
vertical, or can be tapered. The patterned lithographic material
stack can be subsequently removed, for example, by ashing.
[0048] The memory openings 49 and the support openings 19 can be
formed through the gate dielectric layer 12 so that the memory
openings 49 and the support openings 19 extend from the top surface
of the alternating stack (32, 42) to at least the horizontal plane
including the topmost surface of the semiconductor material layer
10. In one embodiment, an overetch into the semiconductor material
layer 10 may be optionally performed after the top surface of the
semiconductor material layer 10 is physically exposed at a bottom
of each memory opening 49 and each support opening 19. The overetch
may be performed prior to, or after, removal of the lithographic
material stack. In other words, the recessed surfaces of the
semiconductor material layer 10 may be vertically offset from the
undressed top surfaces of the semiconductor material layer 10 by a
recess depth. The recess depth can be, for example, in a range from
1 nm to 50 nm, although lesser and greater recess depths can also
be employed. The overetch is optional, and may be omitted. If the
overetch is not performed, the bottom surfaces of the memory
openings 49 and the support openings 19 can be coplanar with the
topmost surface of the semiconductor material layer 10.
[0049] Each of the memory openings 49 and the support openings 19
may include a sidewall (or a plurality of sidewalls) that extends
substantially perpendicular to the topmost surface of the
substrate. A two-dimensional array of memory openings 49 can be
formed in the memory array region 100. A two-dimensional array of
support openings 19 can be formed in the contact region 300. The
substrate semiconductor layer 9 and the semiconductor material
layer 10 collectively constitutes a substrate (9, 10), which can be
a semiconductor substrate. Alternatively, the semiconductor
material layer 10 may be omitted, and the memory openings 49 and
the support openings 19 can be extend to a top surface of the
substrate semiconductor layer 9.
[0050] FIGS. 5A-5H illustrate structural changes in a memory
opening 49, which is one of the memory openings 49 in the first
exemplary structure of FIGS. 4A and 4B. The same structural change
occurs simultaneously in each of the other memory openings 49 and
in each support opening 19.
[0051] Referring to FIG. 5A, a memory opening 49 in the first
exemplary structure of FIGS. 4A and 4B is illustrated. The memory
opening 49 extends through the insulating cap layer 70, the
alternating stack (32, 42), the gate dielectric layer 12, and
optionally into an upper portion of the semiconductor material
layer 10. At this processing step, each support opening 19 can
extend through the retro-stepped dielectric material portion 65, a
subset of layers in the alternating stack (32, 42), the gate
dielectric layer 12, and optionally through the upper portion of
the semiconductor material layer 10. The recess depth of the bottom
surface of each memory opening with respect to the top surface of
the semiconductor material layer 10 can be in a range from 0 nm to
30 nm, although greater recess depths can also be employed.
Optionally, the sacrificial material layers 42 can be laterally
recessed partially to form lateral recesses (not shown), for
example, by an isotropic etch.
[0052] Referring to FIG. 5B, an optional epitaxial channel portion
(e.g., an epitaxial channel portion) 11 can be formed at the bottom
portion of each memory opening 49 and each support openings 19, for
example, by selective epitaxy. Each epitaxial channel portion 11
comprises a single crystalline semiconductor material in epitaxial
alignment with the single crystalline semiconductor material of the
semiconductor material layer 10. In one embodiment, the epitaxial
channel portion 11 can be doped with electrical dopants of the same
conductivity type as the semiconductor material layer 10. In one
embodiment, the top surface of each epitaxial channel portion 11
can be formed above a horizontal plane including the top surface of
a sacrificial material layer 42. In this case, at least one source
select gate electrode can be subsequently formed by replacing each
sacrificial material layer 42 located below the horizontal plane
including the top surfaces of the epitaxial channel portions 11
with a respective conductive material layer. The epitaxial channel
portion 11 can be a portion of a transistor channel that extends
between a source region to be subsequently formed in the substrate
(9, 10) and a drain region to be subsequently formed in an upper
portion of the memory opening 49. A cavity 49' is present in the
unfilled portion of the memory opening 49 above the epitaxial
channel portion 11. In one embodiment, the epitaxial channel
portion 11 can comprise single crystalline silicon. In one
embodiment, the epitaxial channel portion 11 can have a doping of
the first conductivity type, which is the same as the conductivity
type of the semiconductor material layer 10 that the epitaxial
channel portion contacts. If a semiconductor material layer 10 is
not present, the epitaxial channel portion 11 can be formed
directly on the substrate semiconductor layer 9, which can have a
doping of the first conductivity type.
[0053] Referring to FIG. 5C, a material layer stack including a
continuous dielectric liner layer 53, an aluminum oxide tunneling
dielectric layer 57, a silicon-containing tunneling dielectric
layer 56, and an optional first semiconductor channel layer 601 can
be sequentially deposited in the memory openings 49.
[0054] The continuous dielectric liner layer 53 includes a
dielectric material that is different from the material of the
sacrificial material layers 42 and the aluminum oxide tunneling
dielectric layer 57. In one embodiment, the continuous dielectric
liner layer 53 can include a dielectric semiconductor compound such
as silicon oxide or silicon oxynitride. In this case, the
continuous dielectric liner layer 53 can be formed by a conformal
deposition method such as low pressure chemical vapor deposition,
atomic layer deposition, or a combination thereof. The thickness of
the continuous dielectric liner layer 53 can be in a range from 1
nm to 20 nm (such as from 2 nm to 6 nm), although lesser and
greater thicknesses can also be employed. Alternatively, the
continuous dielectric liner layer 53 can be omitted.
[0055] Subsequently, the aluminum oxide tunneling dielectric layer
57 can be formed. In one embodiment, the aluminum oxide tunneling
dielectric layer 57 can be formed by a conformal deposition process
such as atomic layer deposition (ALD). The aluminum oxide tunneling
dielectric layer 57 can be deposited as an amorphous material
layer, and can be transformed into a polycrystalline material layer
in a subsequent annealing step. The thickness of the aluminum oxide
tunneling dielectric layer 57 can be in a range from 1 nm to 4 nm,
although lesser and greater thicknesses can also be employed. In
one embodiment, the sacrificial material layers 42 and the
insulating layers 32 can have vertically coincident sidewalls, and
the aluminum oxide tunneling dielectric layer 57 can be formed as a
single continuous layer.
[0056] The silicon-containing tunneling dielectric layer 56
includes a silicon-containing dielectric material. Charge tunneling
can be performed through the dielectric material of the
silicon-containing tunneling dielectric layer 56 under suitable
electrical bias conditions. The charge tunneling may be performed
through hot-carrier injection or by Fowler-Nordheim tunneling
induced charge transfer depending on the mode of operation of the
monolithic three-dimensional NAND string memory device to be
formed. The silicon-containing tunneling dielectric layer 56 can
include silicon oxide, silicon nitride, silicon oxynitride, and/or
combinations thereof. In one embodiment, the silicon-containing
tunneling dielectric layer 56 can include a stack of a first
silicon oxide layer, a silicon oxynitride layer, and a second
silicon oxide layer, which is commonly known as an ONO stack. In
one embodiment, the silicon-containing tunneling dielectric layer
56 can include a silicon oxide layer that is substantially free of
carbon or a silicon oxynitride layer that is substantially free of
carbon. The thickness of the silicon-containing tunneling
dielectric layer 56 can be in a range from 2 nm to 20 nm (such as
from 3 nm to 10 nm), although lesser and greater thicknesses can
also be employed.
[0057] The optional first semiconductor channel layer 601 includes
a semiconductor material such as at least one elemental
semiconductor material, at least one III-V compound semiconductor
material, at least one II-VI compound semiconductor material, at
least one organic semiconductor material, or other semiconductor
materials known in the art. In one embodiment, the first
semiconductor channel layer 601 includes amorphous silicon or
polysilicon. The first semiconductor channel layer 601 can be
formed by a conformal deposition method such as low pressure
chemical vapor deposition (LPCVD). The thickness of the first
semiconductor channel layer 601 can be in a range from 2 nm to 10
nm, although lesser and greater thicknesses can also be employed. A
cavity 49' is formed in the volume of each memory opening 49 that
is not filled with the deposited material layers (53, 57, 56,
601).
[0058] Referring to FIG. 5D, the optional first semiconductor
channel layer 601, the silicon-containing tunneling dielectric
layer 56, the aluminum oxide tunneling dielectric layer 57, the
continuous dielectric liner layer 53 are sequentially
anisotropically etched employing at least one anisotropic etch
process. The portions of the first semiconductor channel layer 601,
the silicon-containing tunneling dielectric layer 56, the aluminum
oxide tunneling dielectric layer 57, and the continuous dielectric
liner layer 53 located above the top surface of the insulating cap
layer 70 can be removed by the at least one anisotropic etch
process. Further, the horizontal portions of the first
semiconductor channel layer 601, the silicon-containing tunneling
dielectric layer 56, the aluminum oxide tunneling dielectric layer
57, and the continuous dielectric liner layer 53 at a bottom of
each cavity 49' can be removed to form openings in remaining
portions thereof Each of the first semiconductor channel layer 601,
the silicon-containing tunneling dielectric layer 56, the aluminum
oxide tunneling dielectric layer 57, and the continuous dielectric
liner layer 53 can be etched by a respective anisotropic etch
process employing a respective etch chemistry, which may, or may
not, be the same for the various material layers. Each remaining
portion of the first semiconductor channel layer 601 can have a
tubular configuration.
[0059] A surface of the epitaxial channel portion 11 (or a surface
of the semiconductor substrate layer 10 in case the epitaxial
channel portions 11 are not employed) can be physically exposed
underneath the opening through the first semiconductor channel
layer 601, the silicon-containing tunneling dielectric layer 56,
the aluminum oxide tunneling dielectric layer 57, and the
continuous dielectric liner layer 53. Optionally, the physically
exposed semiconductor surface at the bottom of each cavity 49' can
be vertically recessed so that the recessed semiconductor surface
underneath the cavity 49' is vertically offset from the topmost
surface of the epitaxial channel portion 11 (or of the
semiconductor substrate layer 10 in case epitaxial channel portions
11 are not employed) by a recess distance. A silicon-containing
tunneling dielectric layer 56 is located over the aluminum oxide
tunneling dielectric layer 57. A set of a continuous dielectric
liner layer 53, an aluminum oxide tunneling dielectric layer 57,
and a silicon-containing tunneling dielectric layer 56 in a memory
opening 49 constitutes a dielectric material layer stack 250. In
one embodiment, the first semiconductor channel layer 601, the
silicon-containing tunneling dielectric layer 56, the aluminum
oxide tunneling dielectric layer 57, and the continuous dielectric
liner layer 53 can have vertically coincident sidewalls.
[0060] Referring to FIG. 5E, a second semiconductor channel layer
602 can be deposited directly on the semiconductor surface of the
epitaxial channel portion 11 or the semiconductor substrate layer
10 if portion 11 is omitted, and directly on the first
semiconductor channel layer 601. The second semiconductor channel
layer 602 includes a semiconductor material such as at least one
elemental semiconductor material, at least one III-V compound
semiconductor material, at least one II-VI compound semiconductor
material, at least one organic semiconductor material, or other
semiconductor materials known in the art. In one embodiment, the
second semiconductor channel layer 602 includes amorphous silicon
or polysilicon. The second semiconductor channel layer 602 can be
formed by a conformal deposition method such as low pressure
chemical vapor deposition (LPCVD). The thickness of the second
semiconductor channel layer 602 can be in a range from 2 nm to 10
nm, although lesser and greater thicknesses can also be employed.
The second semiconductor channel layer 602 may partially fill the
cavity 49' in each memory opening, or may fully fill the cavity in
each memory opening.
[0061] The materials of the first semiconductor channel layer 601
and the second semiconductor channel layer 602 are collectively
referred to as a semiconductor channel material. In other words,
the semiconductor channel material is a set of all semiconductor
material in the first semiconductor channel layer 601 and the
second semiconductor channel layer 602.
[0062] Referring to FIG. 5F, in case the cavity 49' in each memory
opening is not completely filled by the second semiconductor
channel layer 602, a dielectric core layer 62L can be deposited in
the cavity 49' to fill any remaining portion of the cavity 49'
within each memory opening. The dielectric core layer 62L includes
a dielectric material such as silicon oxide or organosilicate
glass. The dielectric core layer 62L can be deposited by a
conformal deposition method such as low pressure chemical vapor
deposition (LPCVD), or by a self-planarizing deposition process
such as spin coating.
[0063] Referring to FIG. 5G, the horizontal portion of the
dielectric core layer 62L can be removed, for example, by a recess
etch from above the top surface of the insulating cap layer 70.
Each remaining portion of the dielectric core layer 62L constitutes
a dielectric core 62. Further, the horizontal portion of the second
semiconductor channel layer 602 located above the top surface of
the insulating cap layer 70 can be removed by a planarization
process, which can employ a recess etch or chemical mechanical
planarization (CMP). Each remaining portion of the second
semiconductor channel layer 602 can be located entirety within a
memory opening 49 or entirely within a support opening 19.
[0064] Each adjoining pair of a first semiconductor channel layer
601 and a second semiconductor channel layer 602 can collectively
form a vertical semiconductor channel 60 through which electrical
current can flow when a vertical NAND device including the vertical
semiconductor channel 60 is turned on. A silicon-containing
tunneling dielectric layer 56 is surrounded by an aluminum oxide
tunneling dielectric layer 57, and laterally surrounds a portion of
the vertical semiconductor channel 60. Each adjoining set of a
continuous dielectric liner layer 53, an aluminum oxide tunneling
dielectric layer 57, and a silicon-containing tunneling dielectric
layer 56 collectively constitute a dielectric material layer stack
250, which can store electrical charges with a macroscopic
retention time. In some embodiments, a continuous dielectric liner
layer 53 may not be present in the dielectric material layer stack
250 at this step. As used herein, a macroscopic retention time
refers to a retention time suitable for operation of a memory
device as a permanent memory device such as a retention time in
excess of 24 hours.
[0065] Referring to FIG. 5H, the top surface of each dielectric
core 62 can be further recessed within each memory opening, for
example, by a recess etch to a depth that is located between the
top surface of the insulating cap layer 70 and the bottom surface
of the insulating cap layer 70. Drain regions 63 can be formed by
depositing a doped semiconductor material within each recessed
region above the dielectric cores 62. The drain regions 63 can have
a doping of a second conductivity type that is the opposite of the
first conductivity type. For example, if the first conductivity
type is p-type, the second conductivity type is n-type, and vice
versa. The dopant concentration in the drain regions 63 can be in a
range from 5.0.times.10.sup.19/cm.sup.3 to
2.0.times.10.sup.21/cm.sup.3, although lesser and greater dopant
concentrations can also be employed. The doped semiconductor
material can be, for example, doped polysilicon. Excess portions of
the deposited semiconductor material can be removed from above the
top surface of the insulating cap layer 70, for example, by
chemical mechanical planarization (CMP) or a recess etch to form
the drain regions 63.
[0066] Each combination of an epitaxial channel portion 11 (if
present), a dielectric material layer stack 250, a vertical
semiconductor channel 60, a dielectric core 62, and a drain region
63 within a memory opening 49 is herein referred to as a memory
opening fill structure (11, 250, 60, 62, 63). Each combination of
an epitaxial channel portion 11 (if present), a dielectric material
layer stack 250, a vertical semiconductor channel 60, a vertical
semiconductor channel 60, a dielectric core 62, and a drain region
63 within each support opening 19 fills the respective support
openings 19, and constitutes a support pillar structure 20 (shown
in FIG. 6). The drain region 63 in the support pillar structure is
a dummy drain region because it is not electrically connected to a
bit line. Thus, the vertical semiconductor channel 60 and the
dielectric material layer stack 250 in the support pillar structure
20 are structural support elements which are not electrically
active.
[0067] Referring to FIG. 6, the first exemplary structure is
illustrated after formation of memory opening fill structures (11,
250, 60, 62, 63) and support pillar structures 20 within the memory
openings 49 and the support openings 19, respectively. An instance
of a memory opening fill structure (11, 250, 60, 62, 63) can be
formed within each memory opening 49 of the structure of FIGS. 4A
and 4B. An instance of the support pillar structure 20 can be
formed within each support opening 19 of the structure of FIGS. 4A
and 4B.
[0068] Referring to FIGS. 7A and 7B, a contact level dielectric
layer 73 can be formed over the alternating stack (32, 42) of
insulating layer 32 and sacrificial material layers 42, and over
the memory opening fill structures (11, 250, 60, 62, 63) and the
support pillar structures 20. The contact level dielectric layer 73
includes a dielectric material that is different from the
dielectric material of the sacrificial material layers 42. For
example, the contact level dielectric layer 73 can include silicon
oxide. The contact level dielectric layer 73 can have a thickness
in a range from 50 nm to 500 nm, although lesser and greater
thicknesses can also be employed.
[0069] A photoresist layer (not shown) can be applied over the
contact level dielectric layer 73, and is lithographically
patterned to form openings in areas between clusters of memory
opening fill structures (11, 250, 60, 62, 63). The pattern in the
photoresist layer can be transferred through the contact level
dielectric layer 73, the alternating stack (32, 42) and/or the
retro-stepped dielectric material portion 65 employing an
anisotropic etch to form backside trenches 79, which vertically
extend from the top surface of the contact level dielectric layer
73 at least to the top surface of the substrate (9, 10), and
laterally extend through the memory array region 100 and the
contact region 300. In one embodiment, the backside trenches 79 can
include a source contact opening in which a source contact via
structure can be subsequently formed. The photoresist layer can be
removed, for example, by ashing.
[0070] Referring to FIG. 8A, an etchant that selectively etches the
second material of the sacrificial material layers 42 with respect
to the first material of the insulating layers 32 can be introduced
into the backside trenches 79, for example, employing an etch
process. Backside recesses 43 are formed in volumes from which the
sacrificial material layers 42 are removed. The removal of the
second material of the sacrificial material layers 42 can be
selective to the first material of the insulating layers 32, the
material of the retro-stepped dielectric material portion 65, the
semiconductor material of the semiconductor material layer 10, and
the material of the continuous dielectric liner layer 53. In one
embodiment, the sacrificial material layers 42 can include silicon
nitride, and the materials of the insulating layers 32, the support
pillar structure 20, the retro-stepped dielectric material portion
65, and the continuous dielectric liner layer 53 can be selected
from silicon oxide and dielectric metal oxides.
[0071] The etch process that removes the second material selective
to the first material and the continuous dielectric liner layer 53
can be a wet etch process employing a wet etch solution, or can be
a gas phase (dry) etch process in which the etchant is introduced
in a vapor phase into the backside trenches 79. For example, if the
sacrificial material layers 42 include silicon nitride, the etch
process can be a wet etch process in which the first exemplary
structure is immersed within a wet etch tank including phosphoric
acid, which etches silicon nitride selective to silicon oxide,
silicon, and various other materials employed in the art. The
support pillar structure 20, the retro-stepped dielectric material
portion 65, and the memory opening fill structures (11, 250, 60,
62, 63) provide structural support while the backside recesses 43
are present within volumes previously occupied by the sacrificial
material layers 42.
[0072] Each backside recess 43 can be a laterally extending cavity
having a lateral dimension that is greater than the vertical extent
of the cavity. In other words, the lateral dimension of each
backside recess 43 can be greater than the height of the backside
recess 43. A plurality of backside recesses 43 can be formed in the
volumes from which the second material of the sacrificial material
layers 42 is removed. The memory openings in which the memory
opening fill structures (11, 250, 60, 62, 63) are formed are herein
referred to as front side openings or front side cavities in
contrast with the backside recesses 43. In one embodiment, the
memory array region 100 comprises an array of monolithic
three-dimensional NAND strings having a plurality of device levels
disposed above the substrate (9, 10). In this case, each backside
recess 43 can define a space for receiving a respective word line
of the array of monolithic three-dimensional NAND strings.
[0073] Each of the plurality of backside recesses 43 can extend
substantially parallel to the top surface of the substrate (9, 10).
A backside recess 43 can be vertically bounded by a top surface of
an underlying insulating layer 32 and a bottom surface of an
overlying insulating layer 32. In one embodiment, each backside
recess 43 can have a uniform height throughout.
[0074] Referring to FIG. 8B, physically exposed portions of the
continuous dielectric liner layer 53 can be subsequently etched,
for example, employing an isotropic etch process that etches the
dielectric material of the continuous dielectric liner layer 53
selective to the material of the aluminum oxide tunneling
dielectric layer 57. If the continuous dielectric liner layer 53
includes silicon oxide, a wet etch employing hydrofluoric acid can
be employed to etch the material of the continuous dielectric liner
layer 53 selective to the aluminum oxide tunneling dielectric layer
57. The discrete remaining portions of the continuous dielectric
liner layer 53 after the etch process include dielectric liner
portions 53', which are located at each level of the insulating
layers 32 that are located at, or above the horizontal plane
including the bottom surface of the aluminum oxide tunneling
dielectric layer 57. Additional dielectric liner portions 53' are
formed at the level of the insulating cap layer 70.
[0075] Portions of the outer sidewalls of the aluminum oxide
tunneling dielectric layer 57 are physically exposed to the
backside recesses 43 around each dielectric material layer stack
250, which now includes a silicon-containing tunneling dielectric
layer 56, an aluminum oxide tunneling dielectric layer 57, and a
set of dielectric liner portions 53' located at each level of the
insulating layers 32 and at the level of the insulating cap layer
70.
[0076] Referring to FIG. 8C, physically exposed surface portions of
the optional epitaxial channel portions 11 and the semiconductor
material layer 10 can be optionally converted into dielectric
material portions by thermal conversion and/or plasma conversion of
the semiconductor materials into dielectric materials. For example,
thermal conversion and/or plasma conversion can be employed to
convert a surface portion of each epitaxial channel portion 11 into
a tubular dielectric spacer 116, and to convert each physically
exposed surface portion of the semiconductor material layer 10 into
a planar dielectric portion 616. In one embodiment, each tubular
dielectric spacer 116 can be topologically homeomorphic to a torus,
i.e., generally ring-shaped. As used herein, an element is
topologically homeomorphic to a torus if the shape of the element
can be continuously stretched without destroying a hole or forming
a new hole into the shape of a torus.
[0077] The tubular dielectric spacers 116 include a dielectric
material that includes the same semiconductor element as the
epitaxial channel portions 11 and additionally includes at least
one non-metallic element such as oxygen and/or nitrogen such that
the material of the tubular dielectric spacers 116 is a dielectric
material. In one embodiment, the tubular dielectric spacers 116 can
include a dielectric oxide, a dielectric nitride, or a dielectric
oxynitride of the semiconductor material of the epitaxial channel
portions 11. A planar dielectric portion 616 is formed at the
bottom of the backside trenches 79 on the exposed surface of the
substrate (9, 10), as shown in FIG. 9, at the same time as the
dielectric spacers 116. Each planar dielectric portion 616 includes
a dielectric material that includes the same semiconductor element
as the semiconductor material layer and additionally includes at
least one non-metallic element such as oxygen and/or nitrogen such
that the material of the planar dielectric portions 616 is a
dielectric material. In one embodiment, the planar dielectric
portions 616 can include a dielectric oxide, a dielectric nitride,
or a dielectric oxynitride of the semiconductor material of the
semiconductor material layer 10. In one embodiment, the tubular
dielectric spacers 116 and the planar dielectric portions 616 can
include silicon oxide. Formation of the tubular dielectric spacers
116 and the planar dielectric portion 616 is optional.
[0078] Referring to FIG. 8D, charge trapping material portions 54
can be formed on physically exposed surfaces of the aluminum oxide
tunneling dielectric layer 57 by performing a selective silicon
nitride deposition process through the backside trench 79 and the
backside recesses 43. In a selective silicon nitride deposition
process, silicon nitride grows from the physically exposed surfaces
of the aluminum oxide tunneling dielectric layer 57 while not
substantially growing from surfaces of the insulating layers 32,
the insulating cap layer 70, the contact level dielectric layer 73,
or the tubular dielectric spacers 116.
[0079] The selective silicon nitride deposition process can include
atomic layer deposition (ALD), including plasma enhanced ALD, in
which a silicon-containing reactant (such as silicon tetrachloride,
dichlorosilane or organosilicon compound) reacts with a
nitrogen-containing reactant (such as ammonia or nitrogen plasma)
to deposit silicon nitride.
[0080] The discrete charge trapping material portions 54 start to
grow on the aluminum oxide tunneling dielectric layer 57 exposed in
the backside recesses before they grow on the surfaces of the
insulating layers 32, the insulating cap layer 70, the contact
level dielectric layer 73, or the tubular dielectric spacers 116
(i.e., before they grow on the exposed silicon oxide material). The
discrete charge trapping material portions 54 on the aluminum oxide
tunneling dielectric layer 57 continue to thicken with each
subsequent ALD cycle. In contrast, silicon nitride does not begin
to grow on the exposed silicon oxide material until after an
incubation period. Thus, the selective growth of the discrete
charge trapping material portions 54 on the aluminum oxide
tunneling dielectric layer 57 can be terminated before the
expiration of the incubation period such that substantially no
silicon nitride (i.e., no silicon nitride or trace amounts of
silicon nitride) is deposited on the surfaces of the insulating
layers 32, the insulating cap layer 70, the contact level
dielectric layer 73, or the tubular dielectric spacers 116.
[0081] In other words, the selective silicon nitride deposition
process can be selective until silicon nitride nucleates on the
insulating layers 32. In this case, the silicon nitride deposition
process can be terminated before the silicon nitride deposition
process becomes non-selective (i.e., deposits silicon nitride
material on all surfaces), and the entire deposition process can be
a selective silicon nitride deposition process.
[0082] In one embodiment, the duration of the selective silicon
nitride deposition process can be less than the incubation delay
for nucleation of silicon nitride on silicon oxide. In this case,
the deposited silicon nitride material can form the discrete charge
trapping material portions 54, which are discrete silicon nitride
portions having a tubular configuration, i.e., having an annular
geometry in which the inner sidewall and the outer sidewall are
vertical and spaced from each other by a uniform thickness of the
charge trapping material portions 54. In this case, the thickness
of the charge trapping material portions 54 can be in a range from
1 nm to 5 nm, such as from 1.5 nm to 4 nm, although lesser and
greater thicknesses can also be employed.
[0083] Each of the charge trapping material portions 54 laterally
surrounds the aluminum oxide tunneling dielectric layer 57. The
charge trapping material portions 54 may be formed entirely within
the volumes of the memory openings 49 and the support openings 19
(as formed at the processing steps of FIGS. 4A and 4B), or may be
formed partially inside the volumes of the memory openings 49 and
the support openings 19 and partially outside the volumes of the
memory openings 49 and the support openings 19. Thus, at least an
inner portion of each of the charge trapping material portions 54
around an aluminum oxide tunneling dielectric layer 57 can be
formed within a volume of a memory opening 49 or inside a volume of
a support opening 19. A set of the discrete dielectric liner
portions 53' and the charge trapping material portions 54 contacts
an entirety of the outer sidewall of the aluminum oxide tunneling
dielectric layer 57 within each memory opening 49 or within each
support opening 19.
[0084] Each silicon nitride material portion on the aluminum oxide
tunneling dielectric layers 57 constitutes a charge storage
material portion 54. Each contiguous combination of a
silicon-containing tunneling dielectric layer 56, an aluminum oxide
tunneling dielectric layer 57, dielectric liner portions 53'
located directly on the aluminum oxide tunneling dielectric layer
57, and the charge storage material portions 54 located directly on
the aluminum oxide tunneling dielectric layer 57 constitutes a
memory film 50. Each combination of a memory film 50 and a vertical
semiconductor channel 60 in a memory opening 49 constitutes a
memory stack structure 55.
[0085] Referring to FIG. 8E, a backside blocking dielectric layer
44 can be optionally formed. The backside blocking dielectric layer
44 includes at least one dielectric material that functions as a
control gate dielectric for the control gates to be subsequently
formed in the backside recesses 43. The backside blocking
dielectric layer 44 can be formed in the backside recesses 43 and
on a sidewall of the backside trench 79.
[0086] In one embodiment, the backside blocking dielectric layer 44
can include a layer stack of a backside silicon oxide layer 442 and
a backside dielectric metal oxide layer 444. The backside silicon
oxide layer 442 includes silicon oxide, and can be formed directly
on horizontal surfaces of the insulating layers 32 and physically
exposed portions of the outer sidewalls of the charge storage
material portions 54. The backside silicon oxide layer 442 can be
formed by a conformal deposition process such as atomic layer
deposition (ALD) or chemical vapor deposition. The thickness of the
backside silicon oxide layer 442 can be in a range from 1 nm to 8
nm, such as 2 to 6 nm, although lesser and greater thicknesses can
also be employed. The backside silicon oxide layer 442 can be
omitted in some embodiments.
[0087] The dielectric material of the backside dielectric metal
oxide layer 444 can be a dielectric metal oxide such as aluminum
oxide, a dielectric oxide of at least one transition metal element,
a dielectric oxide of at least one Lanthanide element, a dielectric
oxide of a combination of aluminum, at least one transition metal
element, and/or at least one Lanthanide element. The backside
dielectric metal oxide layer 444 can be deposited by a conformal
deposition method such as atomic layer deposition. The thickness of
backside dielectric metal oxide layer 444 can be in a range from 1
nm to 10 nm, although lesser and greater thicknesses can also be
employed. In one embodiment, the backside dielectric metal oxide
layer 444 can consist essentially of aluminum oxide.
[0088] The backside blocking dielectric layer 44 is formed on the
sidewalls of the backside trenches 79, horizontal surfaces and
sidewalls of the insulating layers 32, outer sidewalls of the
charge trapping material portions 54, physically exposed surfaces
of the insulating cap layer 70 and the contact level dielectric
layer 73, and surfaces of the planar dielectric portions 616 (if
present) and tubular dielectric spacers 116 (if present). A
backside cavity 79' is present within the portion of each backside
trench 79 that is not filled with the backside blocking dielectric
layer 44.
[0089] Referring to FIGS. 8F and 9, a metallic barrier layer 46A
can be deposited on the backside blocking dielectric layer 44. The
metallic barrier layer 46A includes an electrically conductive
metallic material that can function as a diffusion barrier layer
and/or adhesion promotion layer for a metallic fill material to be
subsequently deposited. The metallic barrier layer 46A can include
a conductive metallic nitride material such as TiN, TaN, WN, or a
stack thereof, or can include a conductive metallic carbide
material such as TiC, TaC, WC, or a stack thereof. In one
embodiment, the metallic barrier layer 46A can be deposited by a
conformal deposition process such as chemical vapor deposition
(CVD) or atomic layer deposition (ALD). The thickness of the
metallic barrier layer 46A can be in a range from 2 nm to 8 nm,
such as from 3 nm to 6 nm, although lesser and greater thicknesses
can also be employed. In one embodiment, the metallic barrier layer
46A can consist essentially of a conductive metal nitride such as
TiN.
[0090] A metal fill material is deposited in the plurality of
backside recesses 43, on the sidewalls of the at least one the
backside trench 79, and over the top surface of the contact level
dielectric layer 73 to form a metallic fill material layer 46B. The
metallic fill material can be deposited by a conformal deposition
method, which can be, for example, chemical vapor deposition (CVD),
atomic layer deposition (ALD), electroless plating, electroplating,
or a combination thereof. In one embodiment, the metallic fill
material layer 46B can consist essentially of at least one
elemental metal. The at least one elemental metal of the metallic
fill material layer 46B can be selected, for example, from
tungsten, cobalt, ruthenium, titanium, and tantalum. In one
embodiment, the metallic fill material layer 46B can consist
essentially of a single elemental metal. In one embodiment, the
metallic fill material layer 46B can be deposited employing a
fluorine-containing precursor gas such as WF.sub.6. In one
embodiment, the metallic fill material layer 46B can be a tungsten
layer including a residual level of fluorine atoms as impurities.
The metallic fill material layer 46B is spaced from the insulating
layers 32 and the memory stack structures 55 by the metallic
barrier layer 46A, which is a metallic barrier layer that blocks
diffusion of fluorine atoms therethrough.
[0091] A plurality of electrically conductive layers 46 can be
formed in the plurality of backside recesses 43, and a continuous
metallic material layer 46L can be formed on the sidewalls of each
backside trench 79 and over the contact level dielectric layer 73.
Each electrically conductive layer 46 includes a portion of the
metallic barrier layer 46A and a portion of the metallic fill
material layer 46B that are located between a vertically
neighboring pair of dielectric material layers, which can be a pair
of insulating layers 32, a bottommost insulating layer and a gate
dielectric layer 12, or a topmost insulating layer and the
insulating cap layer 70. The continuous metallic material layer 46L
includes a continuous portion of the metallic barrier layer 46A and
a continuous portion of the metallic fill material layer 46B that
are located in the backside trenches 79 or above the contact level
dielectric layer 73.
[0092] Each sacrificial material layer 42 can be replaced with an
electrically conductive layer 46. A backside cavity 79' is present
in the portion of each backside trench 79 that is not filled with
the backside blocking dielectric layer 44 and the continuous
metallic material layer 46L. A tubular dielectric spacer 116
laterally surrounds an epitaxial channel portion 11. A bottommost
electrically conductive layer 46 laterally surrounds each tubular
dielectric spacer 116 upon formation of the electrically conductive
layers 46.
[0093] Referring to FIG. 10, the deposited metallic material of the
continuous electrically conductive material layer 46L is etched
back from the sidewalls of each backside trench 79 and from above
the contact level dielectric layer 73, for example, by an isotropic
wet etch, an anisotropic dry etch, or a combination thereof. Each
remaining portion of the deposited metallic material in the
backside recesses 43 constitutes an electrically conductive layer
46. Each electrically conductive layer 46 can be a conductive line
structure. Thus, the sacrificial material layers 42 are replaced
with the electrically conductive layers 46.
[0094] Each electrically conductive layer 46 can function as a
combination of a plurality of control gate electrodes located at a
same level and a word line electrically interconnecting, i.e.,
electrically shorting, the plurality of control gate electrodes
located at the same level. The plurality of control gate electrodes
within each electrically conductive layer 46 are the control gate
electrodes for the vertical memory devices including the memory
stack structures 55. In other words, each electrically conductive
layer 46 can be a word line that functions as a common control gate
electrode for the plurality of vertical memory devices.
[0095] In one embodiment, the removal of the continuous
electrically conductive material layer 46L can be selective to the
material of the backside blocking dielectric layer 44. In this
case, a horizontal portion of the backside blocking dielectric
layer 44 can be present at the bottom of each backside trench 79.
The gate dielectric layer 12 can be vertically spaced from the
backside trench 79 by the horizontal portion of the backside
blocking dielectric layer 44.
[0096] In another embodiment, the removal of the continuous
electrically conductive material layer 46L may not be selective to
the material of the backside blocking dielectric layer 44, or the
backside blocking dielectric layer 44 may not be employed. In this
case, a top surface and/or sidewall surface, of the gate dielectric
layer 12 can be physically exposed at the bottom of the backside
trench 79 depending on whether the gate dielectric layer 12 is not
removed or partially removed during removal of the continuous
electrically conductive material layer 46L. In one embodiment, a
top surface of the cap gate dielectric layer 126 can be physically
exposed at the bottom of the backside trench 79 after removal of
the continuous electrically conductive material layer 46L. A
backside cavity 79' is present within each backside trench 79.
[0097] Referring to FIG. 11, an insulating material layer can be
formed in the at least one backside trench 79 and over the contact
level dielectric layer 73 by a conformal deposition process.
Exemplary conformal deposition processes include, but are not
limited to, chemical vapor deposition and atomic layer deposition.
The insulating material layer includes an insulating material such
as silicon oxide, silicon nitride, a dielectric metal oxide, an
organosilicate glass, or a combination thereof. In one embodiment,
the insulating material layer can include silicon oxide. The
insulating material layer can be formed, for example, by low
pressure chemical vapor deposition (LPCVD) or atomic layer
deposition (ALD). The thickness of the insulating material layer
can be in a range from 1.5 nm to 60 nm, although lesser and greater
thicknesses can also be employed. The insulating material layer can
be formed directly on surfaces of the backside blocking dielectric
layer 44 and directly on the sidewalls of the electrically
conductive layers 46.
[0098] An anisotropic etch is performed to remove horizontal
portions of the insulating material layer from above the contact
level dielectric layer 73 and at the bottom of each backside trench
79. Each remaining portion of the insulating material layer
constitutes an insulating spacer 74. A backside cavity 79' is
present within a volume surrounded by each insulating spacer
74.
[0099] The anisotropic etch process can continue with, or without,
a change in the etch chemistry to remove portions of the optional
backside blocking dielectric layer 44 and the planar dielectric
portion 616 that underlies the opening through the insulating
spacer 74. An opening is formed though the planar dielectric
portion 616 underneath each backside cavity 79', thereby vertically
extending the backside cavity 79'. A top surface of the
semiconductor material layer 10 can be physically exposed at the
bottom of each backside trench 79. The remaining portion of each
planar dielectric portion 616 is herein referred to as an annular
dielectric portion 616', which can include a dielectric oxide of
the semiconductor material of the semiconductor material layer 10,
have a uniform thickness, and an opening therethrough.
[0100] A source region 61 can be formed at a surface portion of the
semiconductor material layer 10 under each backside cavity 79' by
implantation of electrical dopants into physically exposed surface
portions of the semiconductor material layer 10. Each source region
61 is formed in a surface portion of the substrate (9, 10) that
underlies a respective opening through the insulating spacer 74.
Due to the straggle of the implanted dopant atoms during the
implantation process and lateral diffusion of the implanted dopant
atoms during a subsequent activation anneal process, each source
region 61 can have a lateral extent greater than the lateral extent
of the opening through the insulating spacer 74.
[0101] An upper portion of the semiconductor material layer 10 that
extends between the source region 61 and the plurality of epitaxial
channel portions 11 constitutes a horizontal semiconductor channel
59 for a plurality of field effect transistors. The horizontal
semiconductor channel 59 is connected to multiple vertical
semiconductor channels 60 through respective epitaxial channel
portions 11. The horizontal semiconductor channel 59 contacts the
source region 61 and the plurality of epitaxial channel portions
11. A bottommost electrically conductive layer 46 provided upon
formation of the electrically conductive layers 46 within the
alternating stack (32, 46) can comprise a select gate electrode for
the field effect transistors. Each source region 61 is formed in an
upper portion of the semiconductor substrate (9, 10). Semiconductor
channels (59, 11, 60) extend between each source region 61 and a
respective set of drain regions 63. The semiconductor channels (59,
11, 60) include the vertical semiconductor channels 60 of the
memory stack structures 55.
[0102] A contact via structure 76 can be formed within each
backside cavity 79'. Each contact via structure 76 can fill a
respective cavity 79'. The contact via structures 76 can be formed
by depositing at least one conductive material in the remaining
unfilled volume (i.e., the backside cavity 79') of the backside
trench 79. For example, the at least one conductive material can
include a conductive liner 76A and a conductive fill material
portion 76B. The conductive liner 76A can include a conductive
metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy
thereof, or a stack thereof. The thickness of the conductive liner
76A can be in a range from 3 nm to 30 nm, although lesser and
greater thicknesses can also be employed. The conductive fill
material portion 76B can include a metal or a metallic alloy. For
example, the conductive fill material portion 76B can include W,
Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.
[0103] The at least one conductive material can be planarized
employing the contact level dielectric layer 73 overlying the
alternating stack (32, 46) as a stopping layer. If chemical
mechanical planarization (CMP) process is employed, the contact
level dielectric layer 73 can be employed as a CMP stopping layer.
Each remaining continuous portion of the at least one conductive
material in the backside trenches 79 constitutes a backside contact
via structure 76.
[0104] The backside contact via structure 76 extends through the
alternating stack (32, 46), and contacts a top surface of the
source region 61. If a backside blocking dielectric layer 44 is
employed, the backside contact via structure 76 can contact a
sidewall of the backside blocking dielectric layer 44.
[0105] Referring to FIGS. 12A and 12B, additional contact via
structures (88, 86, 8P) can be formed through the contact level
dielectric layer 73, and optionally through the retro-stepped
dielectric material portion 65. For example, drain contact via
structures 88 can be formed through the contact level dielectric
layer 73 on each drain region 63. Word line contact via structures
86 can be formed on the electrically conductive layers 46 through
the contact level dielectric layer 73, and through the
retro-stepped dielectric material portion 65. Peripheral device
contact via structures 8P can be formed through the retro-stepped
dielectric material portion 65 directly on respective nodes of the
peripheral devices.
[0106] FIGS. 13A-13D illustrate an alternative sequence of
processing steps that can be employed to form a second exemplary
structure, which is modified from the first exemplary structure or
an alternative embodiment thereof by performing the processing
steps of FIGS. 13B-13D in lieu of the processing steps of FIGS. 8E
and 8F.
[0107] Referring to FIG. 13A, the second exemplary structure
according to a second embodiment of the present disclosure can be
derived from the first exemplary structure illustrated in FIG. 8D.
The thickness of the charge storage material regions 54 as provided
at the processing step of FIG. 13A may be greater than the target
thickness for the charge storage material regions 54 in a final
three-dimensional memory device to be formed in order to compensate
for subsequent thinning of the charge storage material portions 54.
For example, the thickness of the charge storage material portions
54 may be in a range from 3 nm to 15 nm at the processing step of
FIG. 13A.
[0108] Referring to FIG. 13B, an oxidation process can be performed
to convert surface portions of the charge storage material portions
54 exposed in the backside recesses 43 into a silicon-containing
dielectric material portions that are employed as a component of
blocking dielectrics. A thermal or plasma oxidation method may be
used by providing the oxidizing gas through the backside trench 79
and backside recesses 43. The silicon-containing dielectric
material portions include silicon oxide or silicon oxynitride, and
are herein referred to as blocking dielectric spacers 443. Each of
the blocking dielectric spacers 443 can be in a tubular
configuration, i.e., can have a vertical inner sidewall and a
vertical outer sidewall that are laterally spaced from each other
by a uniform thickness. The thickness of each blocking dielectric
spacer 443 may be in a range from 1 nm to 12 nm (such as from 2 nm
to 8 nm), although lesser and greater thicknesses can also be
employed. The charge storage material portions 54 are thinned by
oxidation from the outer sidewalls, and can have a thickness in a
range from 1 nm to 10 nm after the oxidation process. Each charge
storage material portion 54 can have a vertical inner sidewall and
a vertical outer sidewall that are laterally spaced from each other
by a uniform thickness.
[0109] As in the first embodiment, each of the charge trapping
material portions 54 laterally surrounds a respective aluminum
oxide tunneling dielectric layer 57. At least an inner portion of
each of the charge trapping material portions 54 is formed within a
volume of a respective memory opening 49 or within a volume of a
respective support opening 19.
[0110] Referring to FIG. 13C, a backside dielectric metal oxide
layer 444 can be formed directly on horizontal surfaces of the
insulating layers 32 and outer sidewalls of the blocking dielectric
spacers 443. The dielectric material of the backside dielectric
metal oxide layer 444 can be a dielectric metal oxide such as
aluminum oxide, a dielectric oxide of at least one transition metal
element, a dielectric oxide of at least one Lanthanide element, a
dielectric oxide of a combination of aluminum, at least one
transition metal element, and/or at least one Lanthanide element.
The backside dielectric metal oxide layer 444 can be deposited by a
conformal deposition method such as atomic layer deposition. The
thickness of backside dielectric metal oxide layer 444 can be in a
range from 1 nm to 10 nm, although lesser and greater thicknesses
can also be employed. In one embodiment, the backside dielectric
metal oxide layer 444 can consist essentially of aluminum
oxide.
[0111] The entire set of blocking dielectric spacers 443 and the
backside dielectric metal oxide layer 444 collectively constitutes
a backside blocking dielectric layer 44. The backside blocking
dielectric layer 44 is formed on the sidewalls of the backside
trenches 79, horizontal surfaces and sidewalls of the insulating
layers 32, outer sidewalls of the charge trapping material portions
54, physically exposed surfaces of the insulating cap layer 70 and
the contact level dielectric layer 73, and surfaces of the planar
dielectric portions 616 (if present) and tubular dielectric spacers
116 (if present). A backside cavity 79' is present within the
portion of each backside trench 79 that is not filled with the
backside blocking dielectric layer 44.
[0112] Referring to FIG. 13D, the processing steps of FIGS. 8F and
9 can be performed to form electrically conductive layers 46 in the
remaining volumes of the backside recesses 43. Subsequently, the
processing steps of FIGS. 10, 11, and 12A-12B can be sequentially
performed to form the second exemplary structure.
[0113] Each of the first and second exemplary structures and
alternative embodiments can include a three-dimensional memory
device. The three-dimensional memory device can include: an
alternating stack of insulating layers 32 and electrically
conductive layers 46 located over a substrate (9, 10,); a vertical
semiconductor channel 60 vertically extending through a predominant
subset of layers within the alternating stack (32, 46) (i.e., more
than 50% of all layers such as all layers excluding the bottommost
electrically conductive layer 46); a tunneling dielectric layer
stack (56, 57) including a silicon-containing tunneling dielectric
layer 56 and an aluminum oxide tunneling dielectric layer 57 and
laterally surrounding the vertical semiconductor channel 60; and
charge trapping material portions 54 located at each level of the
electrically conductive layers 46 that are located at, or above a
horizontal plane including a bottom surface of the aluminum oxide
tunneling dielectric layer 57, comprising silicon nitride,
contacting portions of an outer sidewall of the aluminum oxide
tunneling dielectric layer 57, and vertically spaced from one
another.
[0114] In one embodiment, discrete dielectric liner portions 53'
can be located at each level of the insulating layers 32 that are
located at, or above the horizontal plane including the bottom
surface of the aluminum oxide tunneling dielectric layer 57. A set
of the discrete dielectric liner portions 53' and the charge
trapping material portions 54 contacts an entirety of the outer
sidewall of the aluminum oxide tunneling dielectric layer 57. A
dielectric liner portion 53' can be located between a pair of
nearest neighbor charge trapping material portions 54 to vertically
separate the pair of nearest neighbor charge trapping material
portions 54. In one embodiment, the insulating layers 32 comprise a
first silicon oxide material; and the discrete dielectric liner
portions 53' comprise a second silicon oxide material.
[0115] In one embodiment, a backside blocking dielectric layer 44
can be located between each vertically neighboring pair of an
insulating layer 32 and an electrically conductive layer 46 and
contact an outer sidewall of each of the charge trapping material
portions 54. In one embodiment, the backside blocking dielectric
layer 44 comprises a layer stack of a backside silicon oxide layer
442 and a backside dielectric metal oxide layer 444. The backside
silicon oxide layer 442 contacts horizontal surfaces of the
insulating layers 32, and the backside dielectric metal oxide layer
444 contacts horizontal surfaces of the electrically conductive
layers 46.
[0116] In one embodiment, the backside blocking dielectric layer 44
can include backside blocking dielectric spacers 443 laterally
surrounding, and contacting an outer sidewall of, a respective one
of the charge trapping material portions 54. The backside blocking
dielectric spacers 443 comprise a dielectric material comprising
silicon and oxygen. A backside dielectric metal oxide layer 444 can
contact, and laterally surround, each of the backside blocking
dielectric spacers 443. The three-dimensional memory device can
further comprise: an epitaxial channel portion 11 underlying, and
contacting, the vertical semiconductor channel 60, and a tubular
dielectric spacer 116 located at a level of a bottommost
electrically conductive layer 46 of the alternating stack (32, 46),
laterally surrounding the epitaxial channel portion 11, and
comprising a dielectric oxide of a semiconductor material of the
epitaxial channel portion 11.
[0117] In one embodiment, each of the charge trapping material
portions 54 has a tubular shape and has a uniform thickness
throughout. The three-dimensional memory device can further
comprise: a backside contact trench 79 vertically extending through
the alternating stack (32, 46); an insulating spacer 74 located at
a periphery of the backside contact trench 79; a backside contact
via structure 76 laterally surrounded by the insulating spacer 74;
and a source region 61 located in a portion of the substrate (9,
10,) underlying the backside contact trench 79 and contacting the
backside contact via structure 76.
[0118] In one embodiment, the alternating stack (32, 46) comprises
a terrace region in which each electrically conductive layer 46
other than a topmost electrically conductive layer 46 within the
alternating stack (32, 46) laterally extends farther than any
overlying electrically conductive layers 46 within the alternating
stack (32, 46), and the terrace region includes stepped surfaces of
the alternating stack (32, 46) that continuously extend from a
bottommost layer within the alternating stack (32, 46) to a topmost
layer within the alternating stack (32, 46).
[0119] Each of the first and second exemplary structures can
include a three-dimensional memory device. In one embodiment, the
three-dimensional memory device comprises a vertical NAND memory
device. The electrically conductive layers 46 can comprise, or can
be electrically connected to, a respective word line of the
monolithic three-dimensional NAND memory device. The substrate (9,
10,) can comprise a silicon substrate. The vertical NAND memory
device can comprise an array of monolithic three-dimensional NAND
strings over the silicon substrate. At least one memory cell (as
embodied as a portion of a charge storage layer 54 at a level of an
electrically conductive layer 46) in a first device level of the
array of monolithic three-dimensional NAND strings can be located
over another memory cell (as embodied as another portion of the
charge storage layer 54 at a level of another electrically
conductive layer 46) in a second device level of the array of
monolithic three-dimensional NAND strings. The silicon substrate
can contain an integrated circuit comprising a driver circuit for
the memory device located thereon. The electrically conductive
layers 46 can comprise a plurality of control gate electrodes
having a strip shape extending substantially parallel to the top
surface of the substrate (9, 10,), e.g., between a pair of backside
trenches 79. The plurality of control gate electrodes comprises at
least a first control gate electrode located in a first device
level and a second control gate electrode located in a second
device level. The array of monolithic three-dimensional NAND
strings can comprise: a plurality of semiconductor channels (59,
11, 60), wherein at least one end portion 60 of each of the
plurality of semiconductor channels (59, 11, 60) extends
substantially perpendicular to a top surface of the substrate (9,
10,); and a plurality of charge storage elements (as embodied as
charge trapping material portions). Each charge storage element can
be located adjacent to a respective one of the plurality of
semiconductor channels (59, 11, 60).
[0120] The discrete charge trapping material portions 54 reduce
lateral charge diffusion between adjacent memory cells and improve
data retention compared to a continuous charge trapping material
layer. The addition of the aluminum oxide tunnel dielectric layer
57 can increase the neutral threshold voltage of the device and
further improve data retention.
[0121] Although the foregoing refers to particular preferred
embodiments, it will be understood that the disclosure is not so
limited. It will occur to those of ordinary skill in the art that
various modifications may be made to the disclosed embodiments and
that such modifications are intended to be within the scope of the
disclosure. Where an embodiment employing a particular structure
and/or configuration is illustrated in the present disclosure, it
is understood that the present disclosure may be practiced with any
other compatible structures and/or configurations that are
functionally equivalent provided that such substitutions are not
explicitly forbidden or otherwise known to be impossible to one of
ordinary skill in the art. All of the publications, patent
applications and patents cited herein are incorporated herein by
reference in their entirety.
* * * * *