U.S. patent application number 15/867910 was filed with the patent office on 2018-05-17 for fabrication method of package on package structure.
The applicant listed for this patent is Siliconware Precision Industries Co., Ltd.. Invention is credited to Cheng-Chia Chiang, Shu-Huei Huang, Chang-Yi Lan, Shih-Hao Tung, Lung-Yuan Wang.
Application Number | 20180138158 15/867910 |
Document ID | / |
Family ID | 53482705 |
Filed Date | 2018-05-17 |
United States Patent
Application |
20180138158 |
Kind Code |
A1 |
Tung; Shih-Hao ; et
al. |
May 17, 2018 |
FABRICATION METHOD OF PACKAGE ON PACKAGE STRUCTURE
Abstract
A method for fabricating a package on package (PoP) structure is
provided, which includes: providing a first packaging substrate
having at least a first electronic element and a plurality of first
support portions, wherein the first electronic element is
electrically connected to the first packaging substrate; forming an
encapsulant on the first packaging substrate for encapsulating the
first electronic element and the first support portions; forming a
plurality of openings in the encapsulant for exposing portions of
surfaces of the first support portions; and providing a second
packaging substrate having a plurality of second support portions
and stacking the second packaging substrate on the first packaging
substrate with the second support portions positioned in the
openings of the encapsulant and bonded with the first support
portions. As such, the encapsulant effectively separates the first
support portions or the second support portions from one another to
prevent bridging from occurring therebetween.
Inventors: |
Tung; Shih-Hao; (Taichung,
TW) ; Lan; Chang-Yi; (Taichung, TW) ; Wang;
Lung-Yuan; (Taichung, TW) ; Chiang; Cheng-Chia;
(Taichung, TW) ; Huang; Shu-Huei; (Taichung,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Siliconware Precision Industries Co., Ltd. |
Taichung |
|
TW |
|
|
Family ID: |
53482705 |
Appl. No.: |
15/867910 |
Filed: |
January 11, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14211244 |
Mar 14, 2014 |
9905546 |
|
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15867910 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2924/15311
20130101; H01L 2924/12042 20130101; H01L 2224/48227 20130101; H01L
25/0657 20130101; H01L 2224/45015 20130101; H01L 2225/06568
20130101; H01L 2924/014 20130101; H01L 24/48 20130101; H01L
2924/181 20130101; H01L 2924/00014 20130101; H01L 2225/1058
20130101; H01L 2224/73265 20130101; H01L 2924/15331 20130101; H01L
2224/131 20130101; H01L 24/73 20130101; H01L 2224/32225 20130101;
H01L 24/32 20130101; H01L 23/49811 20130101; H01L 24/16 20130101;
H01L 2225/1023 20130101; H01L 2224/32145 20130101; H01L 24/13
20130101; H01L 2225/0651 20130101; H01L 23/3128 20130101; H01L
2224/16237 20130101; H01L 2224/73204 20130101; H01L 25/105
20130101; H01L 25/50 20130101; H01L 2224/48091 20130101; H01L
23/49816 20130101; H01L 2224/73265 20130101; H01L 2224/32225
20130101; H01L 2224/48227 20130101; H01L 2924/00012 20130101; H01L
2224/73265 20130101; H01L 2224/32145 20130101; H01L 2224/48227
20130101; H01L 2924/00012 20130101; H01L 2224/131 20130101; H01L
2924/014 20130101; H01L 2924/15311 20130101; H01L 2224/73265
20130101; H01L 2224/32225 20130101; H01L 2224/48227 20130101; H01L
2924/00 20130101; H01L 2924/12042 20130101; H01L 2924/00 20130101;
H01L 2924/181 20130101; H01L 2924/00012 20130101; H01L 2924/00014
20130101; H01L 2224/45099 20130101; H01L 2924/00014 20130101; H01L
2224/45015 20130101; H01L 2924/207 20130101; H01L 2224/73204
20130101; H01L 2224/16225 20130101; H01L 2224/32225 20130101; H01L
2924/00 20130101 |
International
Class: |
H01L 25/10 20060101
H01L025/10; H01L 25/00 20060101 H01L025/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 2, 2014 |
TW |
103100022 |
Claims
1-12 (canceled)
13 A method for fabricating a package on package (PoP) structure,
comprising the steps of: providing a first packaging substrate
having at least a first electronic element and a plurality of first
support portions thereon, wherein the first electronic element is
electrically connected to the first packaging substrate; forming an
encapsulant on the first packaging substrate for encapsulating the
first electronic element and the first support portions; forming a
plurality of openings in the encapsulant for exposing portions of
surfaces of the first support portions; and providing a second
packaging substrate having a plurality of second support portions
and stacking the second packaging substrate on the first packaging
substrate with the second support portions positioned in the
openings of the encapsulant and bonded with the first support
portions.
14 The method of claim 13, wherein the first support portions are
electrically connected to the first packaging substrate.
15 The method of claim 13, wherein the first support portions are
metal posts.
16 The method of claim 13, wherein the first support portions are
made of copper or a solder material.
17 The method of claim 13, wherein the first support portions are
copper bumps covered with a solder material.
18 The method of claim 17, wherein the copper bumps are of a ball
shape or a post shape.
19 The method of claim 13, wherein the second support portions are
electrically connected to the second packaging substrate.
20 The method of claim 13, wherein the second support portions are
metal posts.
21 The method of claim 13, wherein the second support portions are
made of copper or a solder material.
22 The method of claim 13, wherein the encapsulant abuts against
the second packaging substrate.
23 The method of claim 13, wherein a gap is formed between the
encapsulant and the second packaging substrate.
24 The method of claim 13, further comprising disposing at least a
second electronic element on the second packaging substrate.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The present invention relates to package on package (PoP)
structures and fabrication methods thereof, and more particularly,
to a PoP structure and a fabrication method thereof for improving
the product yield.
2. Description of Related Art
[0002] Along with the progress of semiconductor packaging
technologies, various package types have been developed for
semiconductor devices. To improve electrical performances and save
spaces, a plurality of packages can be vertically stacked on one
another to form a package on package (PoP) structure. Such a
packaging method allows merging of heterogeneous technologies in a
system-in-package (SiP) so as to systematically integrate a
plurality of electronic elements having different functions, such
as a memory, a CPU (Central Processing Unit), a GPU (Graphics
Processing Unit), an image application processor and so on, and
therefore is applicable to various thin type electronic
products.
[0003] FIG. 1 is a schematic cross-sectional view of a conventional
PoP structure 1. Referring to FIG. 1, the PoP structure 1 has a
first packaging substrate 11 and a second packaging substrate 12
stacked on the first packaging substrate 11. The first packaging
substrate 11 has a first surface 11a and a second surface 11b
opposite to the first surface 11a. A first semiconductor element 10
is disposed on the first surface 11a of the first packaging
substrate 11 and electrically connected to the first packaging
substrate 11, and a plurality of solder balls 17 are formed on
conductive pads 112 of the second surface 11b of the first
packaging substrate 11. The second packaging substrate 12 has a
third surface 12a with a plurality of conductive pads 120 and a
fourth surface 12b opposite to the third surface 12a. Further, a
solder mask layer 123 is formed on the third and fourth surfaces
12a, 12b and has a plurality of openings for exposing the
conductive pads 120.
[0004] To fabricate the PoP structure, the first semiconductor
element 10 is flip-chip electrically connected to the first
packaging substrate 11, an underfill 16 is formed between the first
semiconductor element 10 and the first packaging substrate 11, and
a plurality of solder posts 13 are formed on the first surface 11a
of the first packaging substrate 11. Then, the second packaging
substrate 12 is stacked on the solder posts 13 via the fourth
surface 12b thereof and electrically connected to the first
packaging substrate 11 through the solder posts 13. Thereafter, an
encapsulant 14 is formed between the first surface 11a of the first
packaging substrate 11 and the fourth surface 12b of the second
package substrate 12 for encapsulating the first semiconductor
element 10. Subsequently, a plurality of second semiconductor
elements 15 are disposed on the third surface 12a of the packaging
substrate 12 and electrically connected to the conductive pads 120,
and an underfill 16 is formed between the second semiconductor
element 15 and the second packaging substrate 12.
[0005] In the PoP structure 1, the solder posts 13 are used for
mechanical support and electrical connection between the first
packaging substrate 11 and the second packaging substrate 12.
However, as I/O counts of electronic products increase, if the
package size does not change, the pitch between the solder posts 13
must be reduced. As such, solder bridging easily occurs between the
solder posts 13, thus reducing the product yield and
reliability.
[0006] Therefore, how to overcome the above-described drawbacks has
become critical.
SUMMARY OF THE INVENTION
[0007] In view of the above-described drawbacks, the present
invention provides a package on package (PoP) structure, which
comprises: a first packaging substrate; at least a first electronic
element disposed on and electrically connected to the first
packaging substrate; a plurality of first support portions formed
on the first packaging substrate; an encapsulant formed on the
first packaging substrate for encapsulating the first electronic
element and the first support portions and having a plurality of
openings for exposing portions of surfaces of the first support
portions; and a second packaging substrate having a plurality of
second support portions and stacked on the first packaging
substrate with the second support portions positioned in the
openings of the encapsulant and bonded with the first support
portions.
[0008] The present invention further provides a method for
fabricating a package on package (PoP) structure, which comprises
the steps of: providing a first packaging substrate having at least
a first electronic element and a plurality of first support
portions thereon, wherein the first electronic element is
electrically connected to the first packaging substrate; forming an
encapsulant on the first packaging substrate for encapsulating the
first electronic element and the first support portions; forming a
plurality of openings in the encapsulant for exposing portions of
surfaces of the first support portions; and providing a second
packaging substrate having a plurality of second support portions
and stacking the second packaging substrate on the first packaging
substrate with the second support portions positioned in the
openings of the encapsulant and bonded with the first support
portions.
[0009] In the above-described structure and method, the first
support portions can be electrically connected to the first
packaging substrate. The first support portions can be metal posts.
The first support portions can be made of copper or a solder
material.
[0010] In the above-described structure and method, the first
support portions can be copper bumps covered with a solder
material. The copper bumps can be of a ball shape or a post
shape.
[0011] In the above-described structure and method, the second
support portions can be electrically connected to the second
packaging substrate. The second support portions can be metal
posts. The second support portions can be made of copper or a
solder material.
[0012] In the above-described structure and method, the encapsulant
can abut against the second packaging substrate. Alternatively, a
gap can be formed between the encapsulant and the second packaging
substrate.
[0013] In the above-described structure and method, at least a
second electronic element can further be disposed on the second
packaging substrate.
[0014] According to the present invention, an encapsulant is formed
first to encapsulate the first support portions and then a
plurality of openings are formed in the encapsulant for exposing
portions of the surfaces of the first support portions. As such,
when the second support portions are bonded with the first support
portions in a subsequent process, the encapsulant effectively
separates the first support portions or the second support portions
from one another so as to prevent bridging from occurring
therebetween, thereby improving the product yield and
reliability.
BRIEF DESCRIPTION OF DRAWINGS
[0015] FIG. 1 is a schematic cross-sectional view of a conventional
PoP structure;
[0016] FIGS. 2A to 2D are schematic cross-sectional views showing a
method for fabricating a PoP structure according to the present
invention, wherein FIG. 2B' shows another embodiment of FIG. 2B,
and FIGS. 2D' and 2D'' show other embodiments of FIG. 2D; and
[0017] FIGS. 3A and 3B are schematic cross-sectional views showing
a method for fabricating a PoP structure according to another
embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0018] The following illustrative embodiments are provided to
illustrate the disclosure of the present invention, these and other
advantages and effects can be apparent to those in the art after
reading this specification.
[0019] It should be noted that all the drawings are not intended to
limit the present invention. Various modifications and variations
can be made without departing from the spirit of the present
invention. Further, terms such as "top", "first", "second", "a"
etc. are merely for illustrative purposes and should not be
construed to limit the scope of the present invention.
[0020] FIGS. 2A to 2D are schematic cross-sectional views showing a
method for fabricating a PoP structure 2 according to the present
invention.
[0021] Referring to FIG. 2A, a first packaging substrate 21 having
a first surface 21a and a second surface 21b opposite to the first
surface 21a is provided.
[0022] The first surface 21a of the first packaging substrate 21
has a plurality of first conductive pads 210 and second conductive
pads 211, and the second surface 21b of the first packaging
substrate 21 has a plurality of third conductive pads 212. An
insulating layer 213, such as a solder mask layer, is formed on the
first surface 21a and the second surface 21b of the first packaging
substrate 21, and a plurality of openings 2130 are formed in the
insulating layer 213 for exposing the first conductive pads 210,
the second conductive pads 211 and the third conductive pads
212.
[0023] Further, a plurality of first support portions 231 are
formed on and electrically connected to the second conductive pads
211. The first support portions 231 can be metal posts and made of
such as copper or a solder material.
[0024] Furthermore, a first electronic element 20 is disposed on
the first conductive pads 210 through a plurality of solder bumps
200. That is, the first electronic element 20 is flip-chip
electrically connected to the first packaging substrate 21.
[0025] The first electronic element 20 can be an active element or
a passive element. In an embodiment, a plurality of first
electronic elements 20 are provided, which are active elements,
passive elements or a combination thereof. The active elements are,
for example, chips. The passive elements are, for example,
resistors, capacitors and inductors.
[0026] Referring to FIG. 2B, an encapsulant 24 is formed on the
first surface 21a of the first packaging substrate 21 for
encapsulating the first electronic element 20 and the first support
portions 231. Then, a plurality of openings 240 are formed in the
encapsulant 24 for exposing portions of top surfaces 231a of the
first support portions 231. In the present embodiment, the openings
240 of the encapsulant 24 are formed by laser.
[0027] In another embodiment, referring to FIG. 2B', both the top
surfaces 231a and side surfaces 231b of the first support portions
231 are exposed from the openings 240'.
[0028] Further, the encapsulant 24 is filled between the first
electronic element 20 and the first surface 21a of the first
packaging substrate 21. Alternatively, an underfil can be formed
between the first electronic element 20 and the first surface 21a
of the first packaging substrate 21.
[0029] Referring to FIG. 2C, continued from FIG. 2B, a second
packaging substrate 22 having a third surface 22a and a fourth
surface 22b opposite to the third surface 22a is provided.
[0030] The third surface 22a of the second packaging substrate 22
has a plurality of fourth conductive pads 220 and the fourth
surface 22b of the second packaging substrate 22 has a plurality of
fifth conductive pads 221. An insulating layer 223, such as a
solder mask layer, is formed on the third surface 22a and the
fourth surface 22b, and a plurality of openings 2230 are formed in
the insulating layer 223 for exposing the fourth conductive pads
220 and the fifth conductive pads 221.
[0031] Further, a plurality of second support portions 232 are
formed on and electrically connected to the fifth conductive pads
221. The second support portions 232 can be metal posts and made of
copper or a solder material.
[0032] Furthermore, a second electronic element 25 is disposed on
the third surface 22a of the second packaging substrate 22 and
flip-chip electrically connected to the fourth conductive pads 220
through, for example, a plurality of solder bumps 250. An underfill
26 is further formed between the second electronic element 25 and
the third surface 22a of the second packaging substrate 22.
[0033] The second electronic element 25 can be an active element or
a passive element. In an embodiment, a plurality of second
electronic elements 25 are provided, which are active elements,
passive elements or a combination thereof. The active elements are,
for example, chips. The passive elements are, for example,
resistors, capacitors and inductors.
[0034] Referring to FIG. 2D, the second packaging substrate 22 is
stacked on the first packaging substrate 21 via the fourth surface
22b thereof, with the second support portions 232 positioned in the
openings 240 of the encapsulant 24 and bonded with the top surfaces
231a of the first support portions 231.
[0035] In the present embodiment, the first support portions 231
and the second support portions 232 constitute support members 23
and the encapsulant 24 abuts against the insulating layer 223 on
the fourth surface 22b of the second packaging substrate 22.
[0036] Further, a plurality of solder balls 27 are formed on the
third conductive pads 212 of the second surface 21b of the first
packaging substrate 21.
[0037] In another embodiment, if the process is continued from FIG.
2B', a stack structure 2' as shown FIG. 2D' is formed. In a further
embodiment, referring to FIG. 2D'', a gap t is formed between the
encapsulant 24 and the second packaging substrate 22.
[0038] Further, referring to FIGS. 3A and 3B, a wire-bonding
package can be formed on the second packaging substrate 22. In
particular, a plurality of second electronic element 25' are
disposed on the second packaging substrate 22 and electrically
connected to the fourth conductive pads 220 through a plurality of
bonding wires 250', and an encapsulant 26' is formed on the second
packaging substrate 22 for encapsulating the second electronic
elements 25' and the bonding wires 250'.
[0039] In the present embodiment, the second electronic elements
25' are stacked on one another to form a stack structure. The first
support portions 231' are ball-shaped or post-shaped copper bumps
2310 covered with a solder material 2311. For example, the entire
surface of each of the copper bumps 2310 is covered by the solder
material 2311, and the side surface 231b of each of the first
support portions 231' is partially exposed from the corresponding
opening 240'.
[0040] According to the present invention, an encapsulant 24 is
formed first to encapsulate the first support portions 231, 231'
and then a plurality of openings 240, 240' are formed in the
encapsulant 24 for exposing at least portions of the top surfaces
231a of the first support portions 231, 231'. As such, when the
second support portions 232 are bonded with the first support
portions 231, 231' in a subsequent process, the encapsulant 24
effectively separates the support members 23 from one another so as
to prevent bridging from occurring therebetween, thereby improving
the product yield and reliability.
[0041] The present invention further provides a PoP stack structure
2, 2', 2'', 3, which has: a first packaging substrate 21 having a
first surface 21a and a second surface 21b opposite to the first
surface 21a; a first electronic element 20 disposed on the first
surface 21a of the first packaging substrate 21 and electrically
connected to the first packaging substrate 21; a plurality of first
support portions 231, 231' formed on the first surface 21a of the
first packaging substrate 21; an encapsulant 24 formed on the first
surface 21a of the first packaging substrate 21 for encapsulating
the first electronic element 20 and the first support portions 231,
231' and having a plurality of openings 240, 240' for exposing
portions of surfaces of the first support portions 231; and a
second packaging substrate 22 having a plurality of second support
portions 232 and stacked on the first packaging substrate 21 with
the second support portions 232 positioned in the openings 240 of
the encapsulant 24 and bonded with the first support portions 231,
231'.
[0042] In the present embodiment, the first support portions 231,
231' and the second support portions 232 are metal posts and made
of copper or a solder material.
[0043] In the present embodiment, the first support portions 231,
231' are electrically connected to the first packaging substrate
21, and the second support portions 232 are electrically connected
to the second packaging substrate 22.
[0044] The PoP structure 2, 2', 2'', 3 can further have at least a
second electronic element 25, 25' disposed on and electrically
connected to the second packaging substrate 22.
[0045] The encapsulant 24 can abut against the second packaging
substrate 22, or a gap t can be formed between the encapsulant 24
and the second packaging substrate 22.
[0046] According to the present invention, an encapsulant is formed
first to encapsulate the first support portions and then a
plurality of openings are formed in the encapsulant for exposing
the first support portions. As such, when the second support
portions are bonded with the first support portions in a subsequent
process, the encapsulant effectively separates the support members
from one another so as to prevent bridging from occurring
therebetween, thereby improving the product yield and
reliability.
[0047] The above-described descriptions of the detailed embodiments
are only to illustrate the preferred implementation according to
the present invention, and it is not to limit the scope of the
present invention. Accordingly, all modifications and variations
completed by those with ordinary skill in the art should fall
within the scope of present invention defined by the appended
claims.
* * * * *