U.S. patent application number 15/058864 was filed with the patent office on 2017-09-07 for interconnect structure and method.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Yao-Jen Chang, Chih-Chien Chi, Chia-Cheng Chou, Chen-Yuan Kao, Chung-Chi Ko, Kai-Shiang Kuo, Tze-Liang Lee, Jun-Yi Ruan, Po-Cheng Shih.
Application Number | 20170256445 15/058864 |
Document ID | / |
Family ID | 59650649 |
Filed Date | 2017-09-07 |
United States Patent
Application |
20170256445 |
Kind Code |
A1 |
Chou; Chia-Cheng ; et
al. |
September 7, 2017 |
INTERCONNECT STRUCTURE AND METHOD
Abstract
A device, structure, and method are provided whereby an insert
layer is utilized to provide additional support for surrounding
dielectric layers. The insert layer may be applied between two
dielectric layers. Once formed, trenches and vias are formed within
the composite layers, and the insert layer will help to provide
support that will limit or eliminate undesired bending or other
structural motions that could hamper subsequent process steps, such
as filling the trenches and vias with conductive material.
Inventors: |
Chou; Chia-Cheng; (Keelung
City, TW) ; Chi; Chih-Chien; (Hsin-Chu, TW) ;
Ko; Chung-Chi; (Nantou, TW) ; Chang; Yao-Jen;
(Taipei City, TW) ; Kao; Chen-Yuan; (Hsin-Chu,
TW) ; Kuo; Kai-Shiang; (Hsin-Chu, TW) ; Shih;
Po-Cheng; (Hsin-Chu, TW) ; Lee; Tze-Liang;
(Hsin-Chu, TW) ; Ruan; Jun-Yi; (Taoyuan City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsin-Chu |
|
TW |
|
|
Family ID: |
59650649 |
Appl. No.: |
15/058864 |
Filed: |
March 2, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/823431 20130101;
H01L 23/5226 20130101; H01L 23/53295 20130101; H01L 29/0847
20130101; H01L 21/76829 20130101; H01L 2221/1047 20130101; H01L
21/7684 20130101; H01L 21/76807 20130101; H01L 21/823475 20130101;
H01L 21/76801 20130101; H01L 21/76835 20130101; H01L 21/76843
20130101; H01L 21/845 20130101; H01L 21/76879 20130101; H01L
21/76816 20130101; H01L 21/76838 20130101; H01L 29/7851 20130101;
H01L 23/53238 20130101; H01L 21/76826 20130101; H01L 23/5283
20130101; H01L 29/66545 20130101 |
International
Class: |
H01L 21/768 20060101
H01L021/768; H01L 29/78 20060101 H01L029/78; H01L 23/532 20060101
H01L023/532; H01L 23/528 20060101 H01L023/528; H01L 23/522 20060101
H01L023/522 |
Claims
1. A method comprising: depositing a first dielectric layer over a
substrate; forming a second dielectric layer on the first
dielectric layer, the second dielectric layer having a hardness
that is greater than the first dielectric layer and a K-value that
is greater than the first dielectric layer; depositing a third
dielectric layer over the second dielectric layer, the third
dielectric layer having a hardness that is less than the second
dielectric layer and a K-value that is less than the second
dielectric layer; etching the third dielectric layer, the second
dielectric layer, and the first dielectric layer to form a first
opening exposing a first region over the substrate, the first
opening having a via opening of a first width and a trench opening
of a second width, the trench opening overlapping the via opening,
the second width being greater than the first width, wherein a
bottom surface of the trench opening is in the first dielectric
layer or in the third dielectric layer with a first portion of the
third dielectric layer disposed between the bottom surface of the
trench opening and a surface of the second dielectric layer; and
filling the first opening with a conductive material to form a
first conductive interconnect contacting the first region over the
substrate, the first conductive interconnect comprising a via
portion in the via opening and a trench portion in the trench
opening.
2. The method of claim 1, wherein the first region over the
substrate comprises a conductive element, the first conductive
interconnect contacting the conductive element.
3. The method of claim 1, wherein the second dielectric layer
contacts the via portion of the first conductive interconnect.
4. The method of claim 1, wherein the second dielectric layer
contacts the trench portion of the first conductive
interconnect.
5. The method of claim 1, wherein forming the second dielectric
layer on the first dielectric layer comprises: performing a plasma
treatment process on the first dielectric layer to form the second
dielectric layer on the first dielectric layer, wherein after the
plasma treatment process, the first dielectric layer has a
thickness less than a thickness of the first dielectric layer
before the plasma treatment process.
6. The method of claim 1, wherein forming the second dielectric
layer on the first dielectric layer comprises: depositing the
second dielectric layer on the first dielectric layer.
7. The method of claim 1, wherein filling the first opening with
the conductive material comprises: lining the first opening with a
barrier layer; filling the lined first opening with the conductive
material; and planarizing the conductive material, barrier layer,
and third dielectric layer to remove excess conductive material and
barrier layer over a top surface of the third dielectric layer to
form the first conductive interconnect contacting the first region
over the substrate.
8. The method of claim 1 further comprising: depositing an etch
stop layer over the substrate, the first dielectric layer being
formed over and contacting the etch stop layer, the first opening
extending through the etch stop layer.
9. The method of claim 1, wherein the first dielectric layer has a
K-value of 2.6 or less and the second dielectric layer has a
K-value of 2.8 or greater.
10. A method comprising: depositing a first dielectric layer having
a first thickness over a conductive element over a substrate;
performing a plasma treatment process to convert a top portion of
the first dielectric layer into an insert layer, the insert layer
having a K-value that is greater than the first dielectric layer,
wherein after the plasma treatment process, a remaining lower
portion of the first dielectric layer has a second thickness less
than the first thickness; depositing a second dielectric layer over
the insert layer, the second dielectric layer having a K-value that
is less than the insert layer; etching the second dielectric layer,
the insert layer, and the first dielectric layer to form a via
opening exposing the conductive element over the substrate; and
etching the second dielectric layer to form a trench opening
overlapping the via opening, the trench opening having a greater
width than the via opening, a first portion of the second
dielectric layer being interposed between a bottom surface of the
trench opening and a top surface of the insert layer.
11. The method of claim 10, wherein the first dielectric layer has
a K-value of 2.6 or less and the insert layer has a K-value of 2.8
or greater.
12. The method of claim 10 further comprising: filling the via
opening and the trench opening with a conductive material to form a
first conductive interconnect contacting the conductive element on
the substrate, the first conductive interconnect comprising a via
portion in the via opening and a trench portion in the trench
opening.
13. The method of claim 12, wherein the insert layer contacts the
via portion of the first conductive interconnect.
14. The method of claim 10 further comprising: depositing an etch
stop layer over the substrate and the conductive element within the
substrate, the first dielectric layer being formed over and
contacting the etch stop layer, the via opening extending through
the etch stop layer.
15. The method of claim 10, wherein the conductive element is a
conductive contact, the conductive contact electrically contacting
a source/drain region of a fin field-effect transistor
(FinFET).
16-20. (canceled)
21. A method comprising: forming a fin extending from a substrate;
forming an isolation regions surrounding the fin; forming a gate
structure on a top surface and sidewalls of the fin; forming a
source region and a drain region on the fin, the gate structure
being interposed between the source region and the drain region;
forming an interlayer dielectric over the fin, the source region,
the drain region, the isolation region, and the gate structure;
forming a conductive contact extending through the interlayer
dielectric to contact the source region or the drain region;
depositing a first dielectric layer over interlayer dielectric and
the conductive contact; forming an insert layer over and in contact
with the first dielectric layer, the insert layer having a hardness
that is greater than the first dielectric layer and a K-value that
is greater than the first dielectric layer; depositing a second
dielectric layer over and in contact with the insert layer, the
second dielectric layer having a hardness that is less than the
insert layer and a K-value that is less than the insert layer; and
forming a first conductive interconnect extending through the
second dielectric layer, the insert layer, and the first dielectric
layer to contact the conductive contact, the first conductive
interconnect comprising a via of a first width and a trench of a
second width, the trench overlapping the via, the second width
being greater than the first width, wherein a bottom surface of the
trench is in the first dielectric layer, or is separated from a
surface of the insert layer by a first portion of the second
dielectric layer.
22. The method of claim 21, wherein the insert layer contacts the
via of the first conductive interconnect.
23. The method of claim 21, wherein the insert layer contacts the
trench of the first conductive interconnect.
24. The method of claim 21, wherein forming the insert layer on the
first dielectric layer comprises: performing a plasma treatment
process on the first dielectric layer to form the insert layer on
the first dielectric layer, wherein after the plasma treatment
process, the first dielectric layer has a thickness less than a
thickness of the first dielectric layer before the plasma treatment
process.
25. The method of claim 21, wherein forming the insert layer on the
first dielectric layer comprises: depositing the insert layer on
the first dielectric layer.
Description
BACKGROUND
[0001] In the current process of miniaturizing semiconductor
devices, low-k dielectric materials are desired as the inter-metal
and/or inter-layer dielectric between conductive interconnects in
order to reduce the resistive-capacitive (RC) delay in signal
propagation due to capacitive effects. As such, the lower the
dielectric layer constant of the dielectric, the lower the
parasitic capacitance of adjacent conductive lines and the lower
the RC delay of the integrated circuit (IC).
[0002] However, the materials that are currently being considered
or used as low-k dielectric materials are not ideal. In particular,
in choosing a material based upon its k-value, and particularly
based upon its low-k value, other characteristics, such as the
hardness of the material or its strength, may not be ideal for use
in a semiconductor manufacturing process. As such, improvements in
processes that utilize low-k dielectric materials are desired.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIGS. 1 through 6 are cross-sectional views of intermediate
stages in the manufacturing of an interconnect structure in
accordance with some embodiments.
[0005] FIG. 7 is a cross-sectional views of an interconnect
structure in accordance with some embodiments.
[0006] FIGS. 8 through 11 are cross-sectional views of intermediate
stages in the manufacturing of an interconnect structure in
accordance with some embodiments.
[0007] FIG. 12 is a cross-sectional views of an interconnect
structure in accordance with some embodiments
[0008] FIG. 13 is an example of a Fin Field-Effect Transistor
(FinFET) in a three-dimensional view.
[0009] FIGS. 14 through 18, 19A-19C, 20A-20C, 21A-21C, 22A-22C,
23A-23C, 24A-24C, 25A-25C, 26A-26C, and 27A-27C are cross-sectional
views of intermediate stages in the manufacturing of FinFETs with
interconnect structures in accordance with some embodiments.
DETAILED DESCRIPTION
[0010] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the invention. Specific examples of components and arrangements are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
[0011] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0012] Interconnect structures and methods of forming the same are
provided in accordance with various embodiments. Intermediate
stages of forming interconnect structures are illustrated. Some
embodiments discussed herein are discussed in the context of
interconnects formed using a dual damascene process. In other
embodiments, a single damascene process may be used. Some
variations of the embodiments are discussed. One of ordinary skill
in the art will readily understand other modifications that may be
made that are contemplated within the scope of other embodiments.
Although method embodiments are discussed in a particular order,
various other method embodiments may be performed in any logical
order and may include fewer or more steps described herein.
[0013] With reference now to FIG. 1, FIG. 1 illustrates a substrate
10 with active devices (not shown), metallization layers (not
shown) in the substrate 10, a conductive element 12 coupled to the
metallization layers, an optional etch stop layer 14, and a first
dielectric layer 16. The substrate 10 may be a semiconductor
substrate, such as a bulk semiconductor, a
semiconductor-on-insulator (SOI) substrate, or the like, which may
be doped (e.g., with a p-type or an n-type dopant) or undoped. The
substrate 10 may be a wafer, such as a silicon wafer. Generally, an
SOI substrate comprises a layer of a semiconductor material formed
on an insulator layer. The insulator layer may be, for example, a
buried oxide (BOX) layer, a silicon oxide layer, or the like. The
insulator layer is provided on a substrate, typically a silicon or
glass substrate. Other substrates, such as a multi-layered or
gradient substrate may also be used. In some embodiments, the
semiconductor material of the substrate 10 may include silicon;
germanium; a compound semiconductor including silicon carbide,
gallium arsenic, gallium phosphide, indium phosphide, indium
arsenide, and/or indium antimonide; an alloy semiconductor
including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or
GaInAsP; or combinations thereof.
[0014] The active devices may comprise a wide variety of active
devices such as transistors and the like and passive devices such
as capacitors, resistors, inductors and the like that may be used
to generate the desired structural and functional parts of the
design. The active devices and passive devices may be formed using
any suitable methods either within or else on the substrate 10.
[0015] The metallization layers are formed over active devices and
are designed to connect the various active devices to form
functional circuitry for the design. In an embodiment the
metallization layers are formed of alternating layers of dielectric
and conductive material and may be formed through any suitable
process (such as deposition, damascene, dual damascene, etc.). In
an embodiment there may be one to four layers of metallization
separated from each other by at least one interlayer dielectric
layer (ILD), but the precise number of metallization layers is
dependent upon the design.
[0016] The conductive element 12 may be formed in or over the
metallization layers, and is a region to which an interconnect 24
(not illustrated in FIG. 1 but illustrated and described below in
FIG. 6) will make physical and electrical connection. In an
embodiment the conductive element 12 may be a material such as
copper formed using, e.g., a damascene or dual damascene process,
whereby an opening is formed within the metallization layers, the
opening is filled and/or overfilled with a conductive material such
as copper, and a planarization process is performed to embed the
conductive material within the metallization layers. However, any
suitable material and any suitable process may be used to form the
conductive element 12.
[0017] The etch stop layer 14 may be formed over the substrate 10,
any metallization layers, and the conductive elements 12. In some
embodiments, the etch stop layer 14 may be silicon nitride, silicon
carbide, silicon oxide, low-k dielectrics such as carbon doped
oxides, extremely low-k dielectrics such as porous carbon doped
silicon dioxide, the like, or a combination thereof, and deposited
by CVD, PVD, ALD, a spin-on-dielectric process, the like, or a
combination thereof.
[0018] The first dielectric layer 16 may be formed in order to help
isolate the interconnect 24 from other adjacent electrical routing
lines. In an embodiment the first dielectric layer 16 may be, e.g.,
a low-k dielectric film intended to help isolate the interconnect
24 from other structures. By isolating the interconnect 24, the
resistance-capacitance (RC) delay of the interconnect 24 may be
reduced, thereby improving the overall efficiency and speed of
electricity through the interconnect 24.
[0019] In an embodiment the first dielectric layer 16 may be a
porous material such as SiOCN, SiCN, SiOC, SiOCH, or the like and
may be formed by initially forming a precursor layer over the etch
stop layer 14, if present. The precursor layer may comprise both a
matrix material and a porogen interspersed within the matrix
material, or may alternatively comprise the matrix material without
the porogen. In an embodiment the precursor layer may be formed,
e.g., by co-depositing the matrix and the porogen using a process
such as plasma enhanced chemical vapor deposition (PECVD) where the
matrix material is deposited at the same time as the porogen,
thereby forming the precursor layer with the matrix material and
the porogen mixed together. However, as one of ordinary skill in
the art will recognize, co-deposition using a simultaneous PECVD
process is not the only process that may be used to form the
precursor layer. Any suitable process, such as premixing the matrix
material and the porogen material as a liquid and then spin-coating
the mixture onto the etch stop layer 14, may also be utilized.
[0020] The precursor layer may be formed to a thickness sufficient
to provide the isolation and routing characteristics that are
desired of the first dielectric layer 16. In an embodiment, the
precursor layer may be formed to a first thickness T1 of in a range
from about 10 .ANG. and about 1000 .ANG., such as about 300 .ANG..
However, these thicknesses are meant to be illustrative only, and
are not intended to limit the scope of the embodiments, as the
precise thickness of the precursor layer may be any suitable
desired thickness.
[0021] The matrix material, or base dielectric material, may be
formed using a process such as PECVD, although any suitable
process, such as a chemical vapor deposition (CVD), physical vapor
deposition (PVD), or even spin-on coating, may alternatively be
utilized. The PECVD process may utilize precursors such as
methyldiethoxy silane (DEMS), although other precursors such as
other silanes, alkylsilanes (e.g., trimethylsilane and
tetramethylsilane), alkoxysilanes (e.g., methyltriethoxysilane
(MTEOS), methyltrimethoxysilane (MTMOS), methyldimethoxysilane
(MDMOS), trimethylmethoxysilane (TMMOS) and dimethyldimethoxysilane
(DMDMOS)), linear siloxanes and cyclic siloxanes (e.g.,
octamethylcyclotetrasiloxane (OMCTS) and
tetramethylcyclotetrasiloxane (TMCTS)), combinations of these, and
the like may alternatively be utilized. However, as one of ordinary
skill in the art will recognize, the materials and processes listed
herein are merely illustrative and are not meant to be limiting to
the embodiments, as any other suitable matrix precursors may
alternatively be utilized.
[0022] The porogen may be a molecule that can be removed from the
matrix material after the matrix material has set in order to form
pores within the matrix and thereby reduce the overall value of the
dielectric constant of the first dielectric layer 16. The porogen
may be a material that is big enough to form the pores while also
remaining small enough such that the size of the individual pores
does not overly displace the matrix material. As such, the porogen
may comprise an organic molecule such as alpha-terpinene (ATRP)
(1-Isopropyl-4-Methyl-1,3-Cyclohexadiene) or Cyclooctane (boat
shape) or 1,2-bis(triethoxysilyl) ethane Silicon.
[0023] After the precursor layer has been formed with the porogen
dispersed within the matrix material, the porogen is removed from
the matrix material to form the pores within the matrix material.
In an embodiment the removal of the porogen is performed by an
annealing process which can break down and vaporize the porogen
material, thereby allowing the porogen material to diffuse and
leave the matrix material, thereby leaving behind a structurally
intact porous dielectric material as the first dielectric layer 16.
For example, an anneal of in a range from about 200.degree. C. and
about 500.degree. C., such as about 400.degree. C., for in a range
from about 10 seconds to about 600 seconds, such as about 200
seconds, may be utilized.
[0024] However, as one of ordinary skill in the art will recognize,
the thermal process described above is not the only method that may
be utilized to remove the porogen from the matrix material to form
the first dielectric layer 16. Other suitable processes, such as
irradiating the porogen with UV radiation to decompose the porogen
or utilizing microwaves to decompose the porogen, may alternatively
be utilized. These and any other suitable process to remove all or
a portion of the porogen are all fully intended to be included
within the scope of the embodiments.
[0025] However, the first dielectric layer 16 as described above
does not have the desired resistance to withstand unbalanced stress
that can occur during a patterning process. For example, trench
openings that are located adjacent to a via opening may deform a
different amount than a trench opening that is located further away
from the via opening, such as by being the third trench opening
removed from the via opening. In a particular example, each of the
trench openings may be patterned with a process that attempts to
form the trench openings to have a similar width, but because of
the unbalanced forces within each opening, a trench opening
adjacent to the via opening may have that desired width reduced by
4 nm to 5 nm or 6 nm as compared to the width achieved by a trench
opening located away from the via opening. Such reductions and
differences between the various trench openings could cause
gap-filling problems in subsequent metallization processes
(discussed further below).
[0026] FIG. 2 illustrates forming an insert layer 18 over the first
dielectric layer 16 in order to provide a frame for additional
structural support to increase the robustness of the first
dielectric layer 16 and other subsequently deposited layers. In
addition, the inclusion of the insert layer 18 impacts the
capacitance less than simply changing the bulk film from being a
low-k dielectric film. In an embodiment the insert layer 18 is a
material with a larger hardness and a higher K-value than the first
dielectric layer 16. For example, in an embodiment in which the
first dielectric layer 16 has a hardness of in a range from about
1.5 GPa to about 3.0 GPa, such as about 2 GPa, the insert layer 18
may have a hardness of greater than about 8 GPa, such as in a range
from about 10 GPa to about 13 GPa, such as about 12 GPa. In other
words, the insert layer 18 may have a hardness that is greater than
the first dielectric layer 16 by at least 5 GPa. Similarly, in an
embodiment in which the first dielectric layer 16 has a K-value in
a range from about 2.3 to about 2.9, the insert layer 18 may have a
K-value of greater than about 3.0.
[0027] In some embodiments, the insert layer 18 may comprise a
material such as Si.sub.xO.sub.y (e.g., SiO.sub.2), Si.sub.xC.sub.y
(e.g., SiC), Si.sub.xO.sub.yC.sub.z (e.g., SiOC), and
Si.sub.XC.sub.yN.sub.Z (e.g., SiCN), combinations of these, or the
like. However, any suitable material may be used to provide the
additional structural support for the first dielectric layer
16.
[0028] In an embodiment the insert layer 18 may be formed using a
deposition process such as chemical vapor deposition (CVD), atomic
layer deposition (ALD), physical vapor deposition (PVD), plasma
enhanced CVD (PECVD), spin-on coating, or the like. In other
embodiments, such as an embodiment in which SiO.sub.2 if formed, an
initial layer of a first material such as silicon may be deposited
or formed, and then the layer may be treated with, e.g., oxygen in
order to form the final material for the insert layer 18. Any
suitable process may be used to form the insert layer 18. The
insert layer 18 may be formed to a second thickness T2 of in a
range from about 10 .ANG. to about 100 .ANG., such as about 50
.ANG..
[0029] FIG. 3 illustrates forming a second dielectric layer 20 over
the insert layer 18. In an embodiment the second dielectric layer
20 may be formed from a similar material and in a similar fashion
as the first dielectric layer 16. For example, the second
dielectric layer 20 may comprise a porous material such as ATRP
(1-Isopropyl-4-Methyl-1, 3-Cyclohexadiene) or Cyclooctane (boat
shape) or 1, 2-bis(triethoxysilyl) ethane Silicon formed by
initially placing a matrix material and a porogen and then removing
the porogen. However, in other embodiments the second dielectric
layer 20 may be a different material than the first dielectric
layer 16. Any suitable combination of materials may be formed. In
an embodiment the second dielectric layer 20 may be formed to a
third thickness T3 of in a range from about 10 .ANG. to about 1000
.ANG., such as about 600 .ANG..
[0030] FIG. 4 illustrates patterning the second dielectric layer
20, the insert layer 18, the first dielectric layer 16, and the
etch stop layer 14, if present, to form openings 22 to expose
portions of the conductive elements 12. The openings 22 allows a
portion of the interconnects 24 to make physical and electrical
contact with the conductive elements 12. In some embodiments, the
openings 22 are dual damascene openings including upper trench
sections 22A and lower via-hole sections 22B. Although the
embodiments illustrate dual damascene openings in the layers 16,
18, and 20, the method disclosed in the present application is
applicable for an embodiment having single damascene openings in
the layers. In dual damascene techniques including a "via-first"
patterning method or a "trench-first" patterning method, the upper
trench section 22A and the lower via-hole section 22B may be formed
using photolithography with masking technologies and anisotropic
etch operations (e.g. plasma etching or reactive ion etching).
[0031] For example, in a via-first embodiment, a first photoresist
(not shown) is formed over the second dielectric layer 20 and
patterned to expose a portion of the second dielectric layer 20.
The first photoresist can be formed by using a spin-on technique
and can be patterned using acceptable photolithography techniques.
Once the first photoresist is patterned, a first anisotropic
etching process is performed to form the via openings to the
conductive elements 12, and the first photoresist may act as a mask
for the etching process. After the first anisotropic etching
process, the first photoresist is removed, such as by an acceptable
ashing process. After the first photoresist is removed, a second
photoresist is formed over the second dielectric layer 20 and
patterned to expose a portion of the second dielectric layer 20.
The second photoresist can be formed by using a spin-on technique
and can be patterned using acceptable photolithography techniques.
Once the second photoresist is patterned, a second anisotropic
etching process is performed to form the trench section of the
openings, and the second photoresist may act as a mask for the
etching process. After the second anisotropic etching process, the
second photoresist is removed, such as by an acceptable ashing
process.
[0032] Whereas previous processes (which do not utilize the insert
layer 18) resulted in unbalanced stresses from nearby via etching
processes that resulted in a bending of the top opening of trenches
adjacent to the via and caused critical dimension mismatch issues
in a range from trench openings at different locations around the
device, the presence of the insert layer 18 will help to prevent
the first dielectric layer 16 and the second dielectric layer 20
from bending or collapsing. As such, the top of the openings 22
will better retain the desired shape, and openings 22 across the
device may have less variation. For example, whereas previous
processes without the insert layer 18 may result in bending that
could cause variations in widths in a range from different openings
22 of in a range from about 5 nm to about 6 nm, such as about 5.5
nm (or greater than 10% of the desired pattern), the inclusion of
the insert layer 18 may reduce the amount of bending at the top of
the openings 22.
[0033] FIG. 5 illustrates a filling of the openings 22 with a
conductive material 24. In an embodiment the openings 22 may be
filled with a barrier layer 23 and a conductive material 24. The
barrier layer 23 may comprise a conductive material such as
titanium nitride, although other materials, such as tantalum
nitride, titanium, a dielectric, or the like may alternatively be
utilized. The barrier layer 23 may be formed using a CVD process,
such as PECVD. In some embodiments, the barrier layer 23 is formed
to have a thickness in a range from about 10 .ANG. to about 1000
.ANG.. However, other processes, such as sputtering or metal
organic chemical vapor deposition (MOCVD), may be used. The barrier
layer 23 is formed so as to contour to the underlying shape of the
openings 22.
[0034] The conductive material 24 may comprise copper, although
other suitable materials such as aluminum, alloys, doped
polysilicon, combinations thereof, and the like, may alternatively
be utilized. The conductive material may be formed by first
depositing a seed layer (not separately illustrated in FIG. 5) and
then electroplating copper onto the seed layer, filling and
overfilling the openings 22.
[0035] Once the openings 22 have been filled, FIG. 6 illustrates
removing excess barrier layer 23 and excess conductive material 24
outside of the openings 22 to form interconnects 24. In some
embodiments, the removal of excess barrier layer 23 and excess
conductive material 24 is by a grinding process such as chemical
mechanical polishing (CMP), although any suitable removal process
may be used. In some embodiments, the interconnects 24 are dual
damascene interconnects including an trench section 24A and a via
section 24B. In some embodiments, the via sections 24B of the
interconnects 24 have heights D1 measured from a surface of the
substrate 10 with the heights D1 being in a range from about 400
.ANG. to about 450 .ANG.. In some embodiments, the trench sections
24A of the interconnects 24 have heights D2 measured from top
surfaces of trench sections 24A to bottom surfaces of the trench
sections 24A with the heights D2 being in a range from about 410
.ANG. to about 460 .ANG.. In some embodiments, bottom surfaces of
the trench sections 24A of the interconnects 24 are separated from
a top surface of the insert layer 18 by a distance D3 with the
distance D3 being in a range from about 20 .ANG. to about 130
.ANG..
[0036] By forming the insert layer 18 to provide additional support
for the first dielectric layer 16 as well as the second dielectric
layer 20, the disfiguration and bending that would normally occur
during the patterning process may be mitigated or prevented. As
such, the deleterious effects of these undesired disfigurations,
such as variable reduced widths along a top of the openings 22, may
be prevented. Such preventions allow for fewer defects during the
subsequent filling process.
[0037] FIG. 7 illustrates a cross-section view of an interconnect
structure in accordance with another embodiment. The embodiment in
FIG. 7 is similar to the embodiments illustrated in FIGS. 1 through
6 except that in this embodiment the insert layer 18 is formed in
the trench section of the interconnects 24 as opposed to the via
section in the previous embodiment. The materials and formation
processes of the first dielectric layer 16, the insert layer 18,
and the second dielectric layer 20 may be similar to the previously
described embodiment except that that the relative thicknesses of
the layers may be altered, and thus, the description of these
layers is not repeated herein. Details regarding this embodiment
that are similar to those for the previously described embodiment
will not be repeated herein.
[0038] In this embodiment the first dielectric layer 16 may have a
fourth thickness T4 of in a range from about 10 .ANG. to about 1000
.ANG., such as about 600 .ANG., the insert layer 18 may second
thickness T2, and the second dielectric layer 20 may have a fifth
thickness T5 of in a range from about 10 .ANG. to about 1000 .ANG.,
such as about 300 .ANG.. In this embodiment, bottom surfaces of the
trench sections 24A of the interconnects 24 are separated from a
bottom surface of the insert layer 18 by a distance D4 with the
distance D4 being in a range from about 30 .ANG. to about 150
.ANG..
[0039] FIGS. 8 through 11 are cross-sectional views of intermediate
stages in the manufacturing of an interconnect structure in
accordance with another embodiment. This embodiment is similar to
the embodiments illustrated in FIGS. 1 through 6 except that in
this embodiment the insert layer is formed by a plasma treatment
process as opposed to the deposition process in the previous
embodiment. Details regarding this embodiment that are similar to
those for the previously described embodiment will not be repeated
herein.
[0040] FIG. 8 is at a similar point of processing as FIG. 1
described above and the descriptions of the processes and steps
performed up until this point are not repeated herein. FIG. 8
includes the substrate 10, the conductive elements 12, the optional
etch stop layer 14, and the first dielectric layer 16.
[0041] FIG. 9 illustrates the formation of insert layer 26 over the
first dielectric layer 16 in order to provide a frame for
additional structural support to increase the robustness of the
first dielectric layer 16 and other subsequently deposited layers.
In addition, the inclusion of the insert layer 26 impacts the
capacitance less than simply changing the bulk film from being a
low-k dielectric film. In an embodiment the insert layer 26 is a
material with a larger hardness and a higher K-value than the first
dielectric layer 16. For example, in some embodiments, the first
dielectric layer 16 has a K-value of about 2.6 or less and the
insert layer 26 has a K-value of greater than 2.8, such as about
3.0.
[0042] In some embodiments, the insert layer 26 is formed by
performing a plasma treatment process on the first dielectric layer
16. The plasma treatment process may include plasma reaction gases
such as He, Ar, NH.sub.3, CO.sub.2, N.sub.2, O.sub.2, the like, or
a combination thereof. In some embodiments, the plasma treatment
process may be performed at a temperature in a range from about
200.degree. C. to about 400.degree. C., at a pressure in a range
from about 0.5 torr to about 10 torr, and at a treatment power
(sometimes referred to as discharge power and/or bombardment
intensity) in a range from about 100 Watts (W) to about 500 W. In
some embodiments, the plasma system is a direct plasma system, and
in other embodiments, the plasma system is a remote plasma system.
The plasma treatment process may convert at least an upper portion
of the first dielectric layer 16 into the insert layer 26 such that
the thickness of the first dielectric layer 16 is reduced. In some
embodiments, the insert layer 26 is at least partially formed from
the plasma treated first dielectric layer 16, while, in other
embodiments, the insert layer 26 consists primarily of plasma
treated first dielectric layer 16.
[0043] FIG. 10 illustrates forming the second dielectric layer 20
over the insert layer 26. In an embodiment the second dielectric
layer 20 may be formed from a similar material and in a similar
fashion as the first dielectric layer 16. However, in other
embodiments the second dielectric layer 20 may be a different
material than the first dielectric layer 16. Any suitable
combination of materials may be formed. In an embodiment the second
dielectric layer 20 may be formed to a thickness T8 of in a range
from about 10 .ANG. to about 1000 .ANG., such as about 600 .ANG..
The insert layer 26 may be formed to a thickness T7 of in a range
from about 10 .ANG. to about 100 .ANG., such as about 50 .ANG.. The
first dielectric layer 16 may be formed to a thickness T6 of in a
range from about 10 .ANG. to about 1000 .ANG., such as about 300
.ANG..
[0044] After the second dielectric layer 20 is formed, processing
similar to those described above in FIGS. 4, 5, and 6 are performed
to form the structure of FIG. 11, which is at a similar point of
processing as FIG. 6. The processes and steps of FIGS. 4, 5, and 6
have been described above and are not repeated herein.
[0045] FIG. 12 is a cross-sectional views of an interconnect
structure in accordance with another embodiment. The embodiment in
FIG. 12 is similar to the embodiment illustrated in FIGS. 8 through
11 except that in this embodiment the insert layer 26 is formed in
the trench section of the interconnects 24 as opposed to the via
section in the previous embodiment. The materials and formation
processes of the first dielectric layer 16, the insert layer 26,
and the second dielectric layer 20 may be similar to the previously
described embodiment except that that the relative thicknesses of
the layers may be altered, and thus, the description of these
layers is not repeated herein. Details regarding this embodiment
that are similar to those for the previously described embodiment
will not be repeated herein.
[0046] In this embodiment the first dielectric layer 16 may have a
thickness T9 in a range from about 10 .ANG. to about 1000 .ANG.,
such as about 600 .ANG., the insert layer 26 may thickness T7, and
the second dielectric layer 20 may have a thickness T10 in a range
from about 10 .ANG. to about 1000 .ANG., such as about 300 .ANG..
In this embodiment, bottom surfaces of the trench sections 24A of
the interconnects 24 are separated from a bottom surface of the
insert layer 26 by the distance D4.
[0047] By providing the insert layer as a frame for additional
structural support, the normally weaker porous material of the
first dielectric layer 16 and second dielectric layer 20 may be
supported. Such additional support helps to reduce variances
between different openings that may be caused by their proximity
(or lack of proximity) to neighboring openings. This prevents
complications that could arise during subsequent gap-filling
processes.
[0048] FIGS. 14 through 18, 19A-19C, 20A-20C, 21A-21C, 22A-22C,
23A-23C, 24A-24C, 25A-25C, 26A-26C, and 27A-27C are cross-sectional
views of intermediate stages in the manufacturing of FinFETs with
interconnect structures in accordance with some embodiments.
[0049] FIG. 13 illustrates an example of a fin field-effect
transistor (FinFET) 30 in a three-dimensional view. The FinFET 30
comprises a fin 36 on a substrate 32. The substrate 32 includes
isolation regions 34, and the fin 36 protrudes above and from
between neighboring isolation regions 34. A gate dielectric 38 is
along sidewalls and over a top surface of the fin 36, and a gate
electrode 40 is over the gate dielectric 38. Source/drain regions
42 and 44 are disposed in opposite sides of the fin 36 with respect
to the gate dielectric 38 and gate electrode 40. FIG. 13 further
illustrates reference cross-sections that are used in later
figures. Cross-section A-A is across a channel, gate dielectric 38,
and gate electrode 40 of the FinFET 30. Cross-section B/C-B/C is
perpendicular to cross-section A-A and is along a longitudinal axis
of the fin 36 and in a direction of, for example, a current flow
between the source/drain regions 42 and 44. Subsequent figures
refer to these reference cross-sections for clarity.
[0050] Some embodiments discussed herein are discussed in the
context of FinFETs formed using a gate-last process. In other
embodiments, a gate-first process may be used. Also, some
embodiments contemplate aspects used in planar devices, such as
planar FETs.
[0051] FIGS. 14 through 27C are cross-sectional views of
intermediate stages in the manufacturing of FinFETs in accordance
with an exemplary embodiment. FIGS. 14 through 18 illustrate
reference cross-section A-A illustrated in FIG. 13, except for
multiple FinFETs. In FIGS. 19A through 27C, figures ending with an
"A" designation are illustrated along a similar cross-section A-A;
figures ending with a "B" designation are illustrated along a
similar cross-section B/C-B/C and in a first region on a substrate;
and figures ending with a "C" designation are illustrated along a
similar cross-section B/C-B/C and in a second region on a
substrate.
[0052] FIG. 14 illustrates a substrate 50. Substrate 50 may be a
semiconductor substrate, such as a bulk semiconductor, a
semiconductor-on-insulator (SOI) substrate, or the like, which may
be doped (e.g., with a p-type or an n-type dopant) or undoped. The
substrate 50 may be a wafer, such as a silicon wafer. Generally, an
SOI substrate comprises a layer of a semiconductor material formed
on an insulator layer. The insulator layer may be, for example, a
buried oxide (BOX) layer, a silicon oxide layer, or the like. The
insulator layer is provided on a substrate, typically a silicon or
glass substrate. Other substrates, such as a multi-layered or
gradient substrate may also be used. In some embodiments, the
semiconductor material of the substrate 50 may include silicon;
germanium; a compound semiconductor including silicon carbide,
gallium arsenic, gallium phosphide, indium phosphide, indium
arsenide, and/or indium antimonide; an alloy semiconductor
including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or
GaInAsP; or combinations thereof.
[0053] The substrate 50 has a first region 50B and a second region
50C. The first region 50B (which corresponds to subsequent figures
ending in "B") can be for forming n-type devices, such as NMOS
transistors, such as n-type FinFETs. The second region 50C (which
corresponds to subsequent figures ending in "C") can be for forming
p-type devices, such as PMOS transistors, such as p-type
FinFETs.
[0054] FIGS. 15 and 16 illustrate the formation of fins 52 and
isolation regions 54 between neighboring fins 52. In FIG. 15 fins
52 are formed in the substrate 50. In some embodiments, the fins 52
may be formed in the substrate 50 by etching trenches in the
substrate 50. The etching may be any acceptable etch process, such
as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or
a combination thereof. The etch may be anisotropic.
[0055] In FIG. 16 an insulation material 54 is formed between
neighboring fins 52 to form the isolation regions 54. The
insulation material 54 may be an oxide, such as silicon oxide, a
nitride, the like, or a combination thereof, and may be formed by a
high density plasma chemical vapor deposition (HDP-CVD), a flowable
CVD (FCVD) (e.g., a CVD-based material deposition in a remote
plasma system and post curing to make it convert to another
material, such as an oxide), the like, or a combination thereof.
Other insulation materials formed by any acceptable process may be
used. An anneal process may be performed once the insulation
material is formed. In the illustrated embodiment, the insulation
material 54 is silicon oxide formed by a FCVD process. The
insulating material 54 may be referred to as isolation regions 54.
Further in FIG. 5 and in step 204, a planarization process, such as
a chemical mechanical polish (CMP), may remove any excess
insulation material 54 and form top surfaces of the isolation
regions 54 and top surfaces of the fins 52 that are coplanar.
[0056] FIG. 17 illustrates the recessing of the isolation regions
54 to form Shallow Trench Isolation (STI) regions 54. The isolation
regions 54 are recessed such that fins 56 in the first region 50B
and in the second region 50C protrude from between neighboring
isolation regions 54. Further, the top surfaces of the isolation
regions 54 may have a flat surface as illustrated, a convex
surface, a concave surface (such as dishing), or a combination
thereof. The top surfaces of the isolation regions 54 may be formed
flat, convex, and/or concave by an appropriate etch. The isolation
regions 54 may be recessed using an acceptable etching process,
such as one that is selective to the material of the isolation
regions 54. For example, a chemical oxide removal using a
CERTAS.RTM. etch or an Applied Materials SICONI tool or dilute
hydrofluoric (dHF) acid may be used.
[0057] A person having ordinary skill in the art will readily
understand that the process described with respect to FIGS. 15
through 17 is just one example of how fins 56 may be formed. In
other embodiments, a dielectric layer can be formed over a top
surface of the substrate 50; trenches can be etched through the
dielectric layer; homoepitaxial structures can be epitaxially grown
in the trenches; and the dielectric layer can be recessed such that
the homoepitaxial structures protrude from the dielectric layer to
form fins. In still other embodiments, heteroepitaxial structures
can be used for the fins. For example, the semiconductor strips 52
in FIG. 16 can be recessed, and a material different from the
semiconductor strips 52 may be epitaxially grown in their place. In
an even further embodiment, a dielectric layer can be formed over a
top surface of the substrate 50; trenches can be etched through the
dielectric layer; heteroepitaxial structures can be epitaxially
grown in the trenches using a material different from the substrate
50; and the dielectric layer can be recessed such that the
heteroepitaxial structures protrude from the dielectric layer to
form fins 56. In some embodiments where homoepitaxial or
heteroepitaxial structures are epitaxially grown, the grown
materials may be in situ doped during growth, which may obviate
prior and subsequent implantations although in situ and
implantation doping may be used together. Still further, it may be
advantageous to epitaxially grow a material in an NMOS region
different from the material in a PMOS region. In various
embodiments, the fins 56 may comprise silicon germanium
(Si.sub.xGe.sub.1-x, where x can be between approximately 0 and
100), silicon carbide, pure or substantially pure germanium, a
III-V compound semiconductor, a II-VI compound semiconductor, or
the like. For example, the available materials for forming III-V
compound semiconductor include, but are not limited to, InAs, AlAs,
GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the
like.
[0058] In FIG. 17, appropriate wells may be formed in the fins 56,
fins 52, and/or substrate 50. For example, a P well may be formed
in the first region 50B, and an N well may be formed in the second
region 50C.
[0059] The different implant steps for the different regions 50B
and 50C may be achieved using a photoresist or other masks (not
shown). For example, a photoresist is formed over the fins 56 and
the isolation regions 54 in the first region 50B. The photoresist
is patterned to expose the second region 50C of the substrate 50,
such as a PMOS region. The photoresist can be formed by using a
spin-on technique and can be patterned using acceptable
photolithography techniques. Once the photoresist is patterned, an
n-type impurity implant is performed in the second region 50C, and
the photoresist may act as a mask to substantially prevent n-type
impurities from being implanted into the first region 50B, such as
an NMOS region. The n-type impurities may be phosphorus, arsenic,
or the like implanted in the first region to a concentration of
equal to or less than 10.sup.18 cm.sup.-3, such as in a range from
about 10.sup.17 cm.sup.-3 to about 10.sup.18 cm.sup.-3. After the
implant, the photoresist is removed, such as by an acceptable
ashing process.
[0060] Following the implanting of the second region 50C, a
photoresist is formed over the fins 56 and the isolation regions 54
in the second region 50C. The photoresist is patterned to expose
the first region 50B of the substrate 50, such as the NMOS region.
The photoresist can be formed by using a spin-on technique and can
be patterned using acceptable photolithography techniques. Once the
photoresist is patterned, a p-type impurity implant may be
performed in the first region 50B, and the photoresist may act as a
mask to substantially prevent p-type impurities from being
implanted into the second region, such as the PMOS region. The
p-type impurities may be boron, BF.sub.2, or the like implanted in
the first region to a concentration of equal to or less than
10.sup.18 cm.sup.-3, such as in a range from about 10.sup.17
cm.sup.-3 to about 10.sup.18 cm.sup.-3. After the implant, the
photoresist may be removed, such as by an acceptable ashing
process.
[0061] After the implants of the first region 50B and the second
region 50C, an anneal may be performed to activate the p-type and
n-type impurities that were implanted. The implantations may form a
p-well in the first region 50B, e.g., the NMOS region, and an
n-well in the second region 50C, e.g., the PMOS region. In some
embodiments, the grown materials of epitaxial fins may be in situ
doped during growth, which may obviate the implantations, although
in situ and implantation doping may be used together.
[0062] In FIG. 18, a dummy dielectric layer 58 is formed on the
fins 56. The dummy dielectric layer 58 may be, for example, silicon
oxide, silicon nitride, a combination thereof, or the like, and may
be deposited or thermally grown according to acceptable techniques.
A dummy gate layer 60 is formed over the dummy dielectric layer 58,
and a mask layer 62 is formed over the dummy gate layer 60. The
dummy gate layer 60 may be deposited over the dummy dielectric
layer 58 and then planarized, such as by a CMP. The mask layer 62
may be deposited over the dummy gate layer 60. The dummy gate layer
60 may be made of, for example, polysilicon, although other
materials that have a high etching selectivity from the etching of
isolation regions 54 may also be used. The mask layer 62 may
include, for example, silicon nitride or the like. In this example,
a single dummy gate layer 60 and a single mask layer 62 are formed
across the first region 50B and the second region 50C. In other
embodiments, separate dummy gate layers may be formed in the first
region 50B and the second region 50C, and separate mask layers may
be formed in the first region 50B and the second region 50C.
[0063] In FIGS. 19A, 19B, and 29C, the mask layer 62 may be
patterned using acceptable photolithography and etching techniques
to form masks 72 in the first region 50B (as illustrated in FIG.
19B) and masks 78 in the second region 50C (as illustrated in FIG.
19C). The pattern of the masks 72 and 78 then may be transferred to
the dummy gate layer 60 and dummy dielectric layer 58 by an
acceptable etching technique to form dummy gates 70 in the first
region 50B and dummy gates 76 in the second region 50C. The dummy
gates 70 and 76 cover respective channel regions of the fins 56.
The dummy gates 70 and 76 may also have a lengthwise direction
substantially perpendicular to the lengthwise direction of
respective epitaxial fins.
[0064] In FIGS. 20A, 20B, and 20C, gate seal spacers 80 can be
formed on exposed surfaces of respective dummy gates 70 and 76
and/or fins 56. A thermal oxidation or a deposition followed by an
anisotropic etch may form the gate seal spacers 80.
[0065] After the formation of the gate seal spacers 80, implants
for lightly doped source/drain (LDD) regions may be performed.
Similar to the implants discussed above in FIG. 17, a mask, such as
a photoresist, may be formed over the first region 50B, e.g., NMOS
region, while exposing the second region 50C, e.g., PMOS region,
and p-type impurities may be implanted into the exposed fins 56 in
the second region 50C. The mask may then be removed. Subsequently,
a mask, such as a photoresist, may be formed over the second region
50C while exposing the first region 50B, and n-type impurities may
be implanted into the exposed fins 56 in the first region 50B. The
mask may then be removed. The n-type impurities may be the any of
the n-type impurities previously discussed, and the p-type
impurities may be the any of the p-type impurities previously
discussed. The lightly doped source/drain regions may have a
concentration of impurities of from about 10.sup.15 cm.sup.-3 to
about 10.sup.16 cm.sup.-3. An anneal may be used to activate the
implanted impurities.
[0066] Further in FIGS. 20A, 20B, and 20C, epitaxial source/drain
regions 82 and 84 are formed in the fins 56. In the first region
50B, epitaxial source/drain regions 82 are formed in the fins 56
such that each dummy gate 70 is disposed between respective
neighboring pairs of the epitaxial source/drain regions 82. In some
embodiments that epitaxial source/drain regions 82 may extend into
the fins 52. In the second region 50C, epitaxial source/drain
regions 84 are formed in the fins 56 such that each dummy gate 76
is disposed between respective neighboring pairs of the epitaxial
source/drain regions 84. In some embodiments that epitaxial
source/drain regions 84 may extend into the fins 52.
[0067] Epitaxial source/drain regions 82 in the first region 50B,
e.g., the NMOS region, may be formed by masking the second region
50C, e.g., the PMOS region, and conformally depositing a dummy
spacer layer in the first region 50B followed by an anisotropic
etch to form dummy gate spacers (not shown) along sidewalls of the
dummy gates 70 and/or gate seal spacers 80 in the first region 50B.
Then, source/drain regions of the epitaxial fins in the first
region 50B are etched to form recesses. The epitaxial source/drain
regions 82 in the first region 50B are epitaxially grown in the
recesses. The epitaxial source/drain regions 82 may include any
acceptable material, such as appropriate for n-type FinFETs. For
example, if the fin 56 is silicon, the epitaxial source/drain
regions 82 may include silicon, SiC, SiCP, SiP, or the like. The
epitaxial source/drain regions 82 may have surfaces raised from
respective surfaces of the fins 56 and may have facets.
Subsequently, the dummy gate spacers in the first region 50B are
removed, for example, by an etch, as is the mask on the second
region 50C.
[0068] Epitaxial source/drain regions 84 in the second region 50C,
e.g., the PMOS region, may be formed by masking the first region
50B, e.g., the NMOS region, and conformally depositing a dummy
spacer layer in the second region 50C followed by an anisotropic
etch to form dummy gate spacers (not shown) along sidewalls of the
dummy gates 76 and/or gate seal spacers 80 in the second region
50C. Then, source/drain regions of the epitaxial fins in the second
region 50C are etched to form recesses. The epitaxial source/drain
regions 84 in the second region 50C are epitaxially grown in the
recesses. The epitaxial source/drain regions 84 may include any
acceptable material, such as appropriate for p-type FinFETs. For
example, if the fin 56 is silicon, the epitaxial source/drain
regions 84 may comprise SiGe, SiGeB, Ge, GeSn, or the like. The
epitaxial source/drain regions 84 may have surfaces raised from
respective surfaces of the fins 56 and may have facets.
Subsequently, the dummy gate spacers in the second region 50C are
removed, for example, by an etch, as is the mask on the first
region 50B.
[0069] In FIGS. 21A, 21B, and 21C, gate spacers 86 are formed on
the gate seal spacers 80 along sidewalls of the dummy gates 70 and
76. The gate spacers 86 may be formed by conformally depositing a
material and subsequently anisotropically etching the material. The
material of the gate spacers 86 may be silicon nitride, SiCN, a
combination thereof, or the like.
[0070] The epitaxial source/drain regions 82 and 84 and/or
epitaxial fins may be implanted with dopants to form source/drain
regions, similar to the process previously discussed for forming
lightly doped source/drain regions, followed by an anneal. The
source/drain regions may have an impurity concentration of in a
range from about 10.sup.19 cm.sup.-3 to about 10.sup.21 cm.sup.-3.
The n-type impurities for source/drain regions in the first region
50B, e.g., the NMOS region, may be any of the n-type impurities
previously discussed, and the p-type impurities for source/drain
regions in the second region 50C, e.g., the PMOS region, may be any
of the p-type impurities previously discussed. In other
embodiments, the epitaxial source/drain regions 82 and 84 may be in
situ doped during growth.
[0071] In FIGS. 22A, 22B, and 22C, an ILD 88 is deposited over the
structure illustrated in FIGS. 21A, 21B, and 21C. In an embodiment,
the ILD 88 is a flowable film formed by a flowable CVD. In some
embodiments, the ILD 88 is formed of a dielectric material such as
Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG),
Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass
(USG), or the like, and may be deposited by any suitable method,
such as CVD, or PECVD.
[0072] In FIGS. 23A, 23B, and 23C, a planarization process, such as
a CMP, may be performed to level the top surface of ILD 88 with the
top surfaces of the dummy gates 70 and 76. The CMP may also remove
the masks 72 and 78 on the dummy gates 70 and 76. Accordingly, top
surfaces of the dummy gates 70 and 76 are exposed through the ILD
88.
[0073] In FIGS. 24A, 24B, and 24C, the dummy gates 70 and 76, gate
seal spacers 80, and portions of the dummy dielectric layer 58
directly underlying the dummy gates 70 and 76 are removed in an
etching step(s), so that recesses 90 are formed. Each recess 90
exposes a channel region of a respective fin 56. Each channel
region is disposed between neighboring pairs of epitaxial
source/drain regions 82 and 84. During the removal, the dummy
dielectric layer 58 may be used as an etch stop layer when the
dummy gates 70 and 76 are etched. The dummy dielectric layer 58 and
gate seal spacers 80 may then be removed after the removal of the
dummy gates 70 and 76.
[0074] In FIGS. 25A, 25B, and 25C, gate dielectric layers 92 and 96
and gate electrodes 94 and 98 are formed for replacement gates.
Gate dielectric layers 92 and 96 are deposited conformally in
recesses 90, such as on the top surfaces and the sidewalls of the
fins 56 and on sidewalls of the gate spacers 86, and on a top
surface of the ILD 88. In accordance with some embodiments, gate
dielectric layers 92 and 96 comprise silicon oxide, silicon
nitride, or multilayers thereof. In other embodiments, gate
dielectric layers 92 and 96 include a high-k dielectric material,
and in these embodiments, gate dielectric layers 92 and 96 may have
a k value greater than about 7.0, and may include a metal oxide or
a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations
thereof. The formation methods of gate dielectric layers 92 and 96
may include Molecular-Beam Deposition (MBD), Atomic Layer
Deposition (ALD), PECVD, and the like.
[0075] Next, gate electrodes 94 and 98 are deposited over gate
dielectric layers 92 and 96, respectively, and fill the remaining
portions of the recesses 90. Gate electrodes 94 and 98 may be made
of a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al,
combinations thereof, or multi-layers thereof. After the filling of
gate electrodes 94 and 98, in step 228, a planarization process,
such as a CMP, may be performed to remove the excess portions of
gate dielectric layers 92 and 96 and the material of gate
electrodes 94 and 98, which excess portions are over the top
surface of ILD 88. The resulting remaining portions of material of
gate electrodes 94 and 98 and gate dielectric layers 92 and 96 thus
form replacement gates of the resulting FinFETs.
[0076] The formation of the gate dielectric layers 92 and 96 may
occur simultaneously such that the gate dielectric layers 92 and 96
are made of the same materials, and the formation of the gate
electrodes 94 and 98 may occur simultaneously such that the gate
electrodes 94 and 98 are made of the same materials. However, in
other embodiments, the gate dielectric layers 92 and 96 may be
formed by distinct processes, such that the gate dielectric layers
92 and 96 may be made of different materials, and the gate
electrodes 94 and 98 may be formed by distinct processes, such that
the gate electrodes 94 and 98 may be made of different materials.
Various masking steps may be used to mask and expose appropriate
regions when using distinct processes.
[0077] In FIGS. 26A, 26B, and 26C, an ILD 100 is deposited over ILD
88. Further illustrated in FIGS. 26A, 26B, and 26C, contacts 102
and 104 are formed through ILD 100 and ILD 88 and contacts 106 and
108 are formed through ILD 100. In an embodiment, the ILD 100 is a
flowable film formed by a flowable CVD method. In some embodiments,
the ILD 100 is formed of a dielectric material such as PSG, BSG,
BPSG, USG, or the like, and may be deposited by any suitable
method, such as CVD and PECVD. Openings for contacts 102 and 104
are formed through the ILDs 88 and 100. Openings for contacts 106
and 108 are formed through the ILD 100. These openings may all be
formed simultaneously in a same process, or in separate processes.
The openings may be formed using acceptable photolithography and
etching techniques. A liner, such as a diffusion barrier layer, an
adhesion layer, or the like, and a conductive material are formed
in the openings. The liner may include titanium, titanium nitride,
tantalum, tantalum nitride, or the like. The conductive material
may be copper, a copper alloy, silver, gold, tungsten, aluminum,
nickel, or the like. A planarization process, such as a CMP, may be
performed to remove excess material from a surface of the ILD 100.
The remaining liner and conductive material form contacts 102 and
104 in the openings. An anneal process may be performed to form a
silicide at the interface between the epitaxial source/drain
regions 82 and 84 and the contacts 102 and 104, respectively.
Contacts 102 are physically and electrically coupled to the
epitaxial source/drain regions 82, contacts 104 are physically and
electrically coupled to the epitaxial source/drain regions 84,
contact 106 is physically and electrically coupled to the gate
electrode 94, and contact 108 is physically and electrically
coupled to the gate electrode 98.
[0078] In FIGS. 27A, 27B, and 27C, an Inter-Metal Dielectrics (IMD)
110 is deposited over ILD 100. Further illustrated in FIGS. 27A,
27B, and 27C, interconnects 124, 126, 128, and 130 formed through
IMD 110 to contact respective conductive features within the
underlying ILD 100 (e.g., contacts 102, 104, 106, and/or 108). In
an embodiment, the IMD 110 is a multi-layer film stack formed by
the method described above in FIGS. 1-7 and/or FIGS. 8-12 and
corresponding paragraphs. Layer 114 corresponds to etch stop layer
14 described above, layer 116 corresponds to first dielectric layer
16 described above, layer 118 corresponds to insert layers 18 or 26
described above, and layer 120 corresponds to second dielectric
layer 20 described above. These layers are similar to the
corresponding layers described above in previous embodiments and
the descriptions are not repeated herein. Openings for the
interconnects 124, 126, 128, and 130 are formed through IMD 110 in
similar method as described above in FIGS. 4 and corresponding
paragraphs. These openings may all be formed simultaneously in a
same process, or in separate processes. The interconnects 124, 126,
128, and 130 are formed in similar method as described above in
FIGS. 5-6 and/or FIGS. 11-12 and corresponding paragraphs.
Interconnect 124 is physically and electrically coupled to contact
106, interconnect 126 is physically and electrically coupled to the
contact 108, interconnects 128 are physically and electrically
coupled to the contacts 102, and interconnects 130 are physically
and electrically coupled to the contacts 104.
[0079] Although not explicitly shown, a person having ordinary
skill in the art will readily understand that further processing
steps may be performed on the structure in FIGS. 27A, 27B, and 27C.
For example, various IMDs and their corresponding metallizations
may be formed over IMD 110.
[0080] By providing the insert layer (e.g. layers 18, 26, and/or
118), as a frame for additional structural support, the normally
weaker porous material of the surrounding dielectric layers (e.g.
layers 16, 20, 116, and/or 120), may be supported. Such additional
support helps to reduce variances between different openings that
may be caused by their proximity (or lack of proximity) to
neighboring openings. This prevents complications that could arise
during subsequent gap-filling processes.
[0081] An embodiment is a method including depositing a first
dielectric layer over a substrate, forming a second dielectric
layer on the first dielectric layer, the second dielectric layer
having a hardness that is greater than the first dielectric layer
and a K-value that is greater than the first dielectric layer, and
depositing a third dielectric layer over the second dielectric
layer, the third dielectric layer having a hardness that is less
than the second dielectric layer and a K-value that is less than
the second dielectric layer. The method further includes etching
the third dielectric layer, the second dielectric layer, and the
first dielectric layer to form a first opening exposing a first
region over the substrate, the first opening having a via opening
of a first width and a trench opening of a second width, the trench
opening overlapping the via opening, the second width being greater
than the first width, a bottom surface of the trench opening being
separated from a surface of the second dielectric layer by a first
portion of the first dielectric layer or a first portion of the
third dielectric layer, and filling the first opening with a
conductive material to form a first conductive interconnect
contacting the first region of the substrate, the first conductive
interconnect comprising a via portion in the via opening and a
trench portion in the trench opening.
[0082] Another embodiment is a method including depositing a first
dielectric layer having a first thickness over a conductive element
over a substrate, performing a plasma treatment process to form an
insert layer on the first dielectric layer, the insert layer having
a K-value that is greater than the first dielectric layer, wherein
after the plasma treatment process, the first dielectric layer has
a second thickness less than the first thickness, and depositing a
second dielectric layer over the insert layer, the second
dielectric layer having a K-value that is less than the insert
layer. The method further includes etching the second dielectric
layer, the insert layer, and the first dielectric layer to form a
via opening exposing the conductive element over the substrate, and
etching the second dielectric layer to form a trench opening
overlapping the via opening, the trench opening having a greater
width than the via opening, a first portion of the second
dielectric layer being interposed between a bottom surface of the
trench opening and a top surface of the insert layer.
[0083] A further embodiment is a structure including a first
dielectric layer over a substrate, an insert layer over and in
contact with the first dielectric layer, the insert layer having a
hardness that is greater than the first dielectric layer and a
K-value that is greater than the first dielectric layer, a second
dielectric layer over and in contact with the insert layer, the
second dielectric layer having a hardness that is less than the
insert layer and a K-value that is less than the insert layer, and
a first conductive interconnect extending through the second
dielectric layer, the insert layer, and the first dielectric layer
to contact a first region over the substrate, the first conductive
interconnect comprising via portion of a first width and a trench
portion of a second width, the trench portion overlapping the via
portion, the second width being greater than the first width, a
bottom surface of the trench portion being separated from a surface
of the insert layer by a first portion of the first dielectric
layer or a first portion of the second dielectric layer.
[0084] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *