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name:-0.041339159011841
name:-0.035936117172241
name:-0.019761085510254
Shih; Po-Cheng Patent Filings

Shih; Po-Cheng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shih; Po-Cheng.The latest application filed is for "hybrid film scheme for self-aligned contact".

Company Profile
16.36.39
  • Shih; Po-Cheng - Hsinchu TW
  • SHIH; Po-Cheng - Hsin Chiu City TW
  • Shih; Po-Cheng - Hsin Chiu TW
  • SHIH; Po-Cheng - Hsinchu City TW
  • Shih; Po-Cheng - Hsin-Chu TW
  • SHIH; Po-Cheng - Hsin Chu City TW
  • Shih; Po-Cheng - Hsnchu TW
  • Shih; Po-Cheng - Taipei TW
  • Shih; Po-Cheng - Taipei City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor device having an extra low-k dielectric layer and method of forming the same
Grant 11,417,602 - Shih , et al. August 16, 2
2022-08-16
Hybrid Film Scheme For Self-aligned Contact
App 20220246473 - Lu; Jian-Hong ;   et al.
2022-08-04
Method For Forming Semiconductor Device With Multi-layer Etch Stop Structure
App 20220208603 - SHIH; Po-Cheng ;   et al.
2022-06-30
Multi-layer film device and method
Grant 11,374,127 - Chang , et al. June 28, 2
2022-06-28
Interconnect structure and method
Grant 11,328,952 - Chou , et al. May 10, 2
2022-05-10
Semiconductor device with multi-layer etch stop structure and method for forming the same
Grant 11,282,742 - Shih , et al. March 22, 2
2022-03-22
Patterning Interconnects and Other Structures by Photo-Sensitizing Method
App 20210265204 - Lo; Wei-Jen ;   et al.
2021-08-26
Low-k dielectric and processes for forming same
Grant 11,062,901 - Chou , et al. July 13, 2
2021-07-13
Low-k Dielectric and Processes for Forming Same
App 20210183646 - Chou; Chia Cheng ;   et al.
2021-06-17
Semiconductor Device With Multi-layer Etch Stop Structure And Method For Forming The Same
App 20210118728 - SHIH; Po-Cheng ;   et al.
2021-04-22
Interconnect Structure and Method
App 20210074581 - Chou; Chia-Cheng ;   et al.
2021-03-11
Methods for Reducing Dual Damascene Distortion
App 20210057340 - Wang; Chao-Chun ;   et al.
2021-02-25
Low-k dielectric and processes for forming same
Grant 10,910,216 - Chou , et al. February 2, 2
2021-02-02
Interconnect structure and method
Grant 10,840,134 - Chou , et al. November 17, 2
2020-11-17
Multi-Layer Film Device and Method
App 20200357922 - Chang; Yao-Jen ;   et al.
2020-11-12
Methods for reducing dual damascene distortion
Grant 10,818,598 - Wang , et al. October 27, 2
2020-10-27
Semiconductor Device Having An Extra Low-k Dielectric Layer And Method Of Forming The Same
App 20200335449 - SHIH; Po-Cheng ;   et al.
2020-10-22
Multi-layer film device and method
Grant 10,727,350 - Chang , et al.
2020-07-28
Semiconductor device having an extra low-k dielectric layer and method of forming the same
Grant 10,707,165 - Shih , et al.
2020-07-07
Low-k Dielectric and Processes for Forming Same
App 20200006059 - Chou; Chia Cheng ;   et al.
2020-01-02
Interconnect Structure and Method
App 20190252246 - Chou; Chia-Cheng ;   et al.
2019-08-15
Methods for Reducing Dual Damascene Distortion
App 20190244898 - Wang; Chao-Chun ;   et al.
2019-08-08
Methods for reducing dual damascene distortion
Grant 10,332,836 - Wang , et al.
2019-06-25
Low-k Dielectric and Processes for Forming Same
App 20190164748 - CHOU; Chia Cheng ;   et al.
2019-05-30
Interconnect structure and method
Grant 10,269,627 - Chou , et al.
2019-04-23
Multi-layer film device and method
Grant 10,199,500 - Chang , et al. Fe
2019-02-05
Low-K dielectric interconnect systems
Grant 10,163,691 - Shih , et al. Dec
2018-12-25
Multi-Layer Film Device and Method
App 20180350993 - Chang; Yao-Jen ;   et al.
2018-12-06
Semiconductor Device Having An Extra Low-k Dielectric Layer And Method Of Forming The Same
App 20180308801 - SHIH; Po-Cheng ;   et al.
2018-10-25
Methods for Reducing Dual Damascene Distortion
App 20180102319 - Wang; Chao-Chun ;   et al.
2018-04-12
Multi-Layer Film Device and Method
App 20180040732 - Chang; Yao-Jen ;   et al.
2018-02-08
Low-k Dielectric Interconnect Systems
App 20180005882 - SHIH; Po-Cheng ;   et al.
2018-01-04
Interconnect Structure and Method
App 20170372948 - Chou; Chia-Cheng ;   et al.
2017-12-28
Methods for reducing dual damascene distortion
Grant 9,842,804 - Wang , et al. December 12, 2
2017-12-12
Low-k dielectric interconnect systems
Grant 9,768,061 - Shih , et al. September 19, 2
2017-09-19
Interconnect Structure And Method
App 20170256445 - Chou; Chia-Cheng ;   et al.
2017-09-07
Interconnect structure and method
Grant 9,754,822 - Chou , et al. September 5, 2
2017-09-05
Method of making interconnect structure
Grant 9,748,134 - Shih , et al. August 29, 2
2017-08-29
Methods for Reducing Dual Damascene Distortion
App 20170194253 - Wang; Chao-Chun ;   et al.
2017-07-06
Interconnect structure and method for forming the same
Grant 9,373,581 - Shih , et al. June 21, 2
2016-06-21
Method Of Making Interconnect Structure
App 20160155663 - Shih; Po-Cheng ;   et al.
2016-06-02
Method of forming semiconductor device using remote plasma treatment
Grant 9,269,614 - Shih , et al. February 23, 2
2016-02-23
Method of making interconnect structure
Grant 9,257,331 - Shih , et al. February 9, 2
2016-02-09
Method for forming semiconductor device structure
Grant 9,236,294 - Chou , et al. January 12, 2
2016-01-12
Methods for forming interconnect structures of integrated circuits
Grant 9,130,017 - Shih , et al. September 8, 2
2015-09-08
High UV curing efficiency for low-k dielectrics
Grant 9,093,265 - Shih , et al. July 28, 2
2015-07-28
Method For Forming Semiconductor Device Structure
App 20150200133 - CHOU; Chia-Cheng ;   et al.
2015-07-16
Method Of Forming Semiconductor Device
App 20150170960 - SHIH; Po-Cheng ;   et al.
2015-06-18
Interconnect Structure and Method for Forming the Same
App 20150155234 - Shih; Po-Cheng ;   et al.
2015-06-04
High Uv Curing Efficiency For Low-k Dielectrics
App 20150104953 - Shih; Po-Cheng ;   et al.
2015-04-16
Interconnect structure and method for forming the same
Grant 8,993,442 - Shih , et al. March 31, 2
2015-03-31
Interconnect structure and method for forming the same
Grant 8,994,178 - Shih , et al. March 31, 2
2015-03-31
Low-k Cu barriers in damascene interconnect structures
Grant 8,993,435 - Wang , et al. March 31, 2
2015-03-31
Interconnect Structure And Method For Forming The Same
App 20150056802 - Shih; Po-Cheng ;   et al.
2015-02-26
Method Of Making Interconnect Structure
App 20150011084 - SHIH; Po-Cheng ;   et al.
2015-01-08
Surface treatment in the formation of interconnect structure
Grant 8,877,083 - Chou , et al. November 4, 2
2014-11-04
Interconnect structure and method for forming the same
Grant 8,853,831 - Shih , et al. October 7, 2
2014-10-07
Surface Treatment in the Formation of Interconnect Structure
App 20140141611 - Chou; Chia-Cheng ;   et al.
2014-05-22
Interconnect Structure And Method For Forming The Same
App 20130256903 - SHIH; Po-Cheng ;   et al.
2013-10-03
Interconnect Structure And Method For Forming The Same
App 20130256888 - SHIH; Po-Cheng ;   et al.
2013-10-03
Double patterning strategy for contact hole and trench in photolithography
Grant 8,470,708 - Shih , et al. June 25, 2
2013-06-25
Methods for Forming Interconnect Structures of Integrated Circuits
App 20130052818 - Shih; Po-Cheng ;   et al.
2013-02-28
Low-k Cu Barriers in Damascene Interconnect Structures
App 20110223759 - Wang; Kuan-Chen ;   et al.
2011-09-15
Double Patterning Strategy For Contact Hole And Trench In Photolithography
App 20110207329 - SHIH; Po-Cheng ;   et al.
2011-08-25
Common voltage adjustment circuit and liquid crystal display panel utilizing the same
Grant 7,400,312 - Hung , et al. July 15, 2
2008-07-15
Liquid Crystal Module
App 20060001820 - Cheng; Yin-Tsung ;   et al.
2006-01-05
Common voltage adjustment circuit and liquid crystal display panel utilizing the same
App 20050219185 - Hung, Chi-Mao ;   et al.
2005-10-06

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