U.S. patent application number 15/483544 was filed with the patent office on 2017-07-27 for method for fabricating a shallow and narrow trench fet.
The applicant listed for this patent is Infineon Technologies Americas Corp.. Invention is credited to Igor Bol, Hugo Burke, Timothy D. Henson, David P. Jones, Kapil Kelkar, Ling Ma, Niraj Ranjan.
Application Number | 20170213909 15/483544 |
Document ID | / |
Family ID | 44262920 |
Filed Date | 2017-07-27 |
United States Patent
Application |
20170213909 |
Kind Code |
A1 |
Henson; Timothy D. ; et
al. |
July 27, 2017 |
Method for Fabricating a Shallow and Narrow Trench FET
Abstract
According to an embodiment of a method for fabricating a trench
field-effect transistor (trench FET), the method includes: forming
a trench in a semiconductor substrate of a first conductivity type,
the trench including sidewalls which taper from a wider, top
portion of the trench to a narrower, bottom portion of the trench;
forming a gate dielectric in the trench, the gate dielectric having
substantially the same thickness in the wider, top portion of the
trench as in the narrower, bottom portion of the trench; forming a
gate electrode in the trench and separated from the semiconductor
substrate by the gate dielectric; and forming a channel region of a
second conductivity type in the semiconductor substrate after
forming the trench and the gate dielectric, the channel region
being disposed adjacent the trench. Trench FETs formed by the
method are also disclosed.
Inventors: |
Henson; Timothy D.;
(Torrance, CA) ; Ma; Ling; (Redondo Beach, CA)
; Burke; Hugo; (Llantrisant, GB) ; Jones; David
P.; (Penarth, GB) ; Kelkar; Kapil; (Torrance,
CA) ; Ranjan; Niraj; (El Segundo, CA) ; Bol;
Igor; (Topanga, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Infineon Technologies Americas Corp. |
El Segundo |
CA |
US |
|
|
Family ID: |
44262920 |
Appl. No.: |
15/483544 |
Filed: |
April 10, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12800662 |
May 20, 2010 |
9653597 |
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15483544 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/30625 20130101;
H01L 29/42376 20130101; H01L 29/4236 20130101; H01L 29/36 20130101;
H01L 29/7813 20130101; H01L 29/66734 20130101; H01L 29/0878
20130101; H01L 21/265 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/36 20060101 H01L029/36; H01L 21/306 20060101
H01L021/306; H01L 29/66 20060101 H01L029/66; H01L 21/265 20060101
H01L021/265; H01L 29/423 20060101 H01L029/423; H01L 29/08 20060101
H01L029/08 |
Claims
1-20. (canceled)
21. A method for fabricating a trench field-effect transistor
(trench FET), the method comprising: forming a trench in a
semiconductor substrate of a first conductivity type, the trench
including sidewalls which taper from a wider, top portion of the
trench to a narrower, bottom portion of the trench; forming a gate
dielectric in the trench, the gate dielectric having substantially
the same thickness in the wider, top portion of the trench as in
the narrower, bottom portion of the trench; forming a gate
electrode in the trench and separated from the semiconductor
substrate by the gate dielectric; and forming a channel region of a
second conductivity type in the semiconductor substrate after
forming the trench and the gate dielectric, the channel region
being disposed adjacent the trench.
22. The method of claim 21, wherein the channel region is formed by
dopant implantation.
23. The method of claim 21, further comprising: forming a bottom
implanted region of the first conductivity type surrounding the
narrower, bottom portion of the trench before forming the gate
dielectric in the trench, the bottom implanted region having a
dopant concentration greater than the dopant concentration of the
semiconductor substrate, the narrower, bottom portion of the trench
being disposed in the bottom implanted region.
24. The method of claim 21, wherein the gate electrode is coplanar
with a top surface of the semiconductor substrate.
25. The method of claim 24, wherein the gate electrode is made
coplanar with a top surface of the semiconductor substrate by
chemical mechanical polishing of the top surface.
26. The method of claim 21, further comprising: forming a source
region of the first conductivity type in the semiconductor
substrate adjacent the trench, after forming the trench and the
gate dielectric.
27. The method of claim 26, further comprising: forming a drift
region of the first conductivity type in the semiconductor
substrate, the drift region being separated from the source region
by the channel region.
28. The method of claim 27, wherein the narrower, bottom portion of
the trench is disposed in the drift region.
29. The method of claim 26, further comprising: forming a drift
region of the first conductivity type in the semiconductor
substrate below the channel region so that the source region is
separated from the drift region by the channel region; and forming
a bottom implanted region of the first conductivity type
surrounding the narrower, bottom portion of the trench before
forming the gate dielectric in the trench, the bottom implanted
region being disposed in the drift region and having a dopant
concentration greater than the dopant concentration of the
semiconductor substrate, wherein the narrower, bottom portion of
the trench is disposed in the bottom implanted region.
30. The method of claim 26, wherein the gate electrode is coplanar
with a top surface of the source region.
31. The method of claim 26, further comprising: forming a recessed
region in the semiconductor substrate which extends through the
source region and into the channel region, wherein a top surface of
the gate electrode is disposed above a bottom surface of the
recessed region.
32. The method of claim 26, wherein a depth of the source region is
0.15 microns or less, wherein a length of the channel region is
between 0.3 to 0.45 microns, and wherein a depth of the trench is
between 0.6 to 0.8 microns.
33. The method of claim 26, further comprising: forming a first
dielectric portion over the source region; forming a second
dielectric portion over the trench; and forming a third dielectric
portion over the first and the second dielectric portions.
34. The method of claim 33, further comprising: forming a source
contact material over the semiconductor substrate, wherein the
second and the third dielectric portions insulate the gate
electrode from the source contact material, wherein the first and
the third dielectric portions separate the source contact material
from a top surface of the source region, wherein the source contact
material contacts a side face of the source region uncovered by the
first and the third dielectric portions.
35. The method of claim 21, wherein the semiconductor substrate is
doped to form the channel region after forming the gate
electrode.
36. A trench field-effect transistor (trench FET), comprising: a
trench formed in a semiconductor substrate of a first conductivity
type, the trench including sidewalls which taper from a wider, top
portion of the trench to a narrower, bottom portion of the trench;
a gate dielectric formed in the trench, the gate dielectric having
substantially the same thickness in the wider, top portion of the
trench as in the narrower, bottom portion of the trench; a gate
electrode formed in the trench and separated from the semiconductor
substrate by the gate dielectric; and a channel region of a second
conductivity type formed in the semiconductor substrate, the
channel region being disposed adjacent the trench.
37. The trench FET of claim 36, further comprising a bottom
implanted region of the first conductivity type surrounding the
narrower, bottom portion of the trench, wherein the bottom
implanted region has a dopant concentration greater than the dopant
concentration of the semiconductor substrate, and wherein the
narrower, bottom portion of the trench is disposed in the bottom
implanted region.
38. The trench FET of claim 36, wherein the gate electrode is
coplanar with a top surface of the semiconductor substrate.
39. The trench FET of claim 36, further comprising a source region
of the first conductivity type formed in the semiconductor
substrate adjacent the trench.
40. The trench FET of claim 39, further comprising a drift region
of the first conductivity type formed in the semiconductor
substrate, wherein the drift region is separated from the source
region by the channel region.
41. The trench of claim 40, wherein the narrower, bottom portion of
the trench is disposed in the drift region.
42. The trench FET of claim 39, further comprising: a drift region
of the first conductivity type formed in the semiconductor
substrate below the channel region; and a bottom implanted region
of the first conductivity type surrounding the narrower, bottom
portion of the trench, wherein the source region is separated from
the drift region by the channel region, wherein the bottom
implanted region is disposed in the drift region and has a dopant
concentration greater than the dopant concentration of the
semiconductor substrate, wherein the narrower, bottom portion of
the trench is disposed in the bottom implanted region.
43. The trench FET of claim 42, wherein the gate electrode is
coplanar with a top surface of the source region.
44. The trench FET of claim 42, further comprising a recessed
region in the semiconductor substrate which extends through the
source region and into the channel region, wherein a top surface of
the gate electrode is disposed above a bottom surface of the
recessed region.
45. The trench of claim 42, wherein a depth of the source region is
0.15 microns or less, wherein a length of the channel region is
between 0.3 to 0.45 microns, and wherein a depth of the trench is
between 0.6 to 0.8 microns.
46. The trench FET of claim 36, further comprising: a first
dielectric portion formed over the source region; a second
dielectric portion formed over the trench; and a third dielectric
portion formed over the first and the second dielectric
portions.
47. The trench FET of claim 46, further comprising: a source
contact material formed over the semiconductor substrate, wherein
the second and the third dielectric portions insulate the gate
electrode from the source contact material, wherein the first and
the third dielectric portions separate the source contact material
from a top surface of the source region, wherein the source contact
material contacts a side face of the source region uncovered by the
first and the third dielectric portions.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention is generally in the field of
semiconductors. More specifically, the present invention is in the
field of fabrication of transistors.
[0003] 2. Background Art
[0004] Power semiconductor devices, such as field-effect
transistors (FETs) are widely used in a variety of electronic
devices and systems. Examples of such electronic devices and
systems are power converters, such as DC to DC converters, in which
vertically conducting trench type silicon FETs, for instance, may
be implemented as power switches. In power converters, power losses
within the power switches, as well as factors affecting switching
speed, are becoming increasingly important. For example, for
optimal performance it is desirable to reduce overall gate charge
Qg, gate resistance Rg, and ON-resistance R.sub.dson of the power
switches.
[0005] Optimizing R.sub.dson in a vertical trench FET, for example,
may require carefully controlling the length of the channel. That
is to say, implementation of a vertical trench FET having a short
channel may improve the R.sub.dson characteristic of the device.
However, conventional methods of forming vertical trench FETs can
undesirably affect channel length rendering a short channel
unachievable and the channel length uncontrollable. For example,
conventional methods can expose dopants, used to form the channel,
to high temperature processes, thereby uncontrollably increasing
channel length. Moreover, the conventional vertical trench FET
requires deep trenches to, for example, counter the lack of control
over the channel length.
[0006] Thus, there is a need for a method that can provide trench
FETs while overcoming the drawbacks and deficiencies in the
art.
SUMMARY OF THE INVENTION
[0007] A method for fabricating a shallow and narrow trench
field-effect transistor (trench FET) and related structures,
substantially as shown in and/or described in connection with at
least one of the figures, as set forth more completely in the
claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a cross-sectional view showing trench field-effect
transistors fabricated using a conventional method of
fabrication.
[0009] FIG. 2 is a flowchart presenting a method for fabricating
shallow and narrow trench field-effect transistors, according to
one embodiment of the present invention.
[0010] FIG. 3 is a cross-sectional view showing shallow and narrow
trench field-effect transistors fabricated according to one
embodiment of the present invention.
[0011] FIG. 4 is a cross-sectional view showing shallow and narrow
trench field-effect transistors fabricated according to one
embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0012] The present invention is directed to a method for
fabricating a shallow and narrow trench field-effect transistor
(trench FET) and related structures. Although the invention is
described with respect to specific embodiments, the principles of
the invention, as defined by the claims appended herein, can
obviously be applied beyond the specifically described embodiments
of the invention described herein. Moreover, in the description of
the present invention, certain details have been left out in order
to not obscure the inventive aspects of the invention. The details
left out are within the knowledge of a person of ordinary skill in
the art.
[0013] The drawings in the present application and their
accompanying detailed description are directed to merely example
embodiments of the invention. To maintain brevity, other
embodiments of the invention, which use the principles of the
present invention, are not specifically described in the present
application and are not specifically illustrated by the present
drawings. It should be borne in mind that, unless noted otherwise,
like or corresponding elements among the figures may be indicated
by like or corresponding reference numerals. Moreover, the drawings
and illustrations in the present application are generally not to
scale, and are not intended to correspond to actual relative
dimensions.
[0014] FIG. 1 shows a cross-sectional view of a semiconductor
device including conventional trench field-effect transistors
(FETs). As shown in FIG. 1, semiconductor device 100 includes
transistors 102a and 102b, which are implemented, for example, in
silicon and which are vertical trench type transistors. In the
present example, in semiconductor device 100, transistors 102a and
102b correspond to one another and include similar elements and
dimensions, and are generally identical, and may comprise multiple
fingers or segments of the same transistor.
[0015] As shown in FIG. 1, transistor 102a includes drift region
104, channel regions 106, and source regions 108. As shown in FIG.
1, channel regions 106 are formed over drift region 104 and source
regions 108 are formed over channel regions 106. In the present
example, drift region 104 comprises N type semiconductor material,
channel regions 106 comprise P type semiconductor material, arid
source regions 108 comprise N type semiconductor material. Thus, in
the present example, transistor 102a is an N type trench FET.
[0016] Also shown in FIG. 1, transistor 102a has trench 110
including sidewalls 112 and bottom portion 114. Trench 110 is
situated between source regions 108 and channel regions 106.
Furthermore, in the present example, trench 110 extends from a top
surface of source regions 108 and into drift region 104, such that
bottom portion 114 of trench 110 is in drift region 104.
[0017] As shown in FIG. 1, trench 110 also includes gate dielectric
116 and gate electrode 118 formed therein. Gate dielectric 116
includes portions lining respective sidewalls 112 of trench 110 and
thick bottom oxide 140 formed over bottom portion 114 of trench
110. Gate electrode 118 is formed over thick bottom oxide 140 of
gate dielectric 116. Thick bottom oxide 140 of gate dielectric 116
can reduce gate to drain charge Q.sub.gd in semiconductor device
100. As shown in FIG. 1, in the present example, gate electrode 118
is recessed from the top surface of trench 110 and the top surfaces
of source regions 108, thereby forming recess 117. Dielectric
material 128 is formed over source regions 108 and fills recess
117.
[0018] As stated above, in the present example, transistors 102a
and 102b have similar dimensions. Thus, as shown in FIG. 1,
transistor 102a has trench width 122, source depth 119, and channel
length 120. In transistor 102a, trench sidewalls 112 are
substantially parallel, thus, trench 110 has a uniform trench width
122, which by way of a specific example, can be approximately 0.5
to 0.6 microns. Also, as one example, in transistor 102a, source
depth 119 can be approximately 0.3 to 0.35 microns and channel
length 120 can be approximately 0.7 microns. Thus, transistor 102a
has a relatively long channel length, which is accommodated by a
relatively deep trench 110. For example, trench 110 can be
approximately 1.2 microns long.
[0019] The formation of semiconductor device 100 is subject to
significant constraints, which can degrade device performance and
characteristics. For example, in forming transistor 102a, source
depth 119 and channel length 120 are subject to significant
constraints, which prevent formation of a short channel device.
Thus, reduction of R.sub.dson is significantly limited in
semiconductor device 100.
[0020] In forming transistor 102a, a semiconductor substrate is
doped with, for example, P type dopants, to form channel regions
106. N type source regions 108 can be formed before or after
formation of the transistor gate. When trench 110, gate dielectric
116, and gate electrode 118 are formed in the semiconductor
substrate, the semiconductor substrate is exposed to significant
temperatures, which can undesirably drive the dopants and can
render channel length 120 uncontrollable in semiconductor device
100. For example, channel length 120 (and source depth 119, if
source regions 108 are formed prior to gate formation) can be
driven to an undesirable depth, preventing a relatively short
channel length 120 and requiring a deep trench 110.
[0021] Forming a gate dielectric can comprise a high temperature
process. Furthermore, including a thick bottom oxide, for example
thick bottom oxide 140, requires additional processing steps, which
can increase exposure of dopants to high temperatures. Thus,
because gate dielectric 116 includes thick bottom oxide 140, the
semiconductor substrate can be exposed to additional high
temperatures, further increasing channel length 120 in
semiconductor device 100, thereby hindering formation of a short
channel length 120 and a shallow trench 110. Forming thick bottom
oxide 140 can further complicate formation of semiconductor device
100, for example, by requiring additional processing steps and
increasing manufacturing costs.
[0022] Forming transistor 102a with recess 117 can also introduce
significant constraints in forming semiconductor device 100. In
transistor 102a, recess 117 prevents shorting between gate
electrode 118 and source regions 108 and can have a depth of
approximately 0.15 microns. The depth of recess 117 can be
difficult to control in formation of semiconductor device 100.
Thus, reducing source depth 119, introduces considerable risk of
gate electrode 118 falling below source regions 108, which would
significantly degrade device performance. As such, source depth 119
cannot be significantly reduced in order to prevent gate electrode
118 from falling below source regions 108, thereby hindering
formation of a short channel length 120 and a shallow trench
110.
[0023] The present invention provides a trench field-effect
transistor (trench FET) and a method for fabricating the same. The
method can be used to form a shallow and narrow trench FET having
improved device performance characteristics, such as R.sub.dson,
not achievable in conventional semiconductor devices, by reducing
or eliminating significant constraints imposed by conventional
methods.
[0024] FIG. 2 presents flowchart 200 describing exemplary
embodiments of a method for fabricating shallow and narrow trench
FETs, for example, trench FETs 302a and 302b in FIG. 3 and trench
FETs 402a and 402b in FIG. 4. It will be appreciated that the
method illustrated by flowchart 200 in FIG. 2 in not limited to the
semiconductor devices shown in FIGS. 3 and 4. Also, certain details
and features have been left out of flowchart 200 that are apparent
to a person of ordinary skill in the art. For example, a step may
comprise one or more substeps or may involve specialized equipment
or materials, as known in the art. It is noted that the processing
steps shown in flowchart 200 are performed on a portion of wafer,
which, prior to step 210, includes, a semiconductor substrate, for
example, an N type semiconductor substrate.
[0025] While steps 210 through 250 indicated in flowchart 200 are
sufficient to describe embodiments of the present invention, other
embodiments of the invention may utilize steps different from those
shown in flowchart 200, or may comprise more, or fewer, steps. For
example, while the method of flowchart 200 is for an N channel
device, it will be appreciated that the present invention can also
provide for a P channel device. Furthermore, the sequence of steps
210 through 250 is not limited by flowchart 200. For example, while
flowchart 200 shows step 250 occurring after step 240, in other
embodiments step 250 can occur before step 240.
[0026] Exemplary shallow and narrow trench FETs, which can be
fabricated according the present invention, will be described with
respect to FIGS. 3 and 4. Thus, FIGS. 3 shows a cross-sectional
view of exemplary shallow and narrow trench field-effect
transistors (trench FETs), which can be fabricated according to one
embodiment of the present invention. For example, FIG. 3 shows
exemplary trench FETs 302a and 302b, which correspond to one
another, include similar elements and dimensions, are generally
identical, and may comprise multiple fingers or segments of the
same transistor. Similarly, FIGS. 4 shows a cross-sectional view of
exemplary shallow and narrow trench field-effect transistors
(trench FETs), which can be fabricated according to one embodiment
of the present invention.
[0027] FIGS. 3 includes semiconductor device 300, which can
correspond to semiconductor device 400 in FIG. 4. Thus,
semiconductor device 300 comprises similar elements as
semiconductor device 400. For example, semiconductor device 300
includes trench FETs 302a and 302b, drift region 304, channel
regions 306, source regions 308, trench 310, trench bottom 314, and
channel length 320, which can correspond to trench FETs 402a and
402b, drift region 404, channel regions 406, source regions 408,
trench 410, trench bottom 414, and channel length 420 respectively
in FIG. 4. It is noted that other elements in FIG. 4, not marked
for reference, can likewise correspond to similar elements in FIG.
3. Semiconductor device 400 in FIG. 4 notably includes bottom
implanted region 430, which is not included in semiconductor device
300 in FIG. 3. Although steps 410, 430, 440, and 450 will be
described with respect to semiconductor device 300, it will be
appreciated that the steps can similarly be performed with respect
to semiconductor device 400. For example, elements in semiconductor
device 400 can be formed similar to corresponding elements in
semiconductor device 300.
[0028] Referring now to step 210 of FIG. 2 and FIG. 3, step 210 of
flowchart 200 comprises forming a trench within an N type
semiconductor substrate, the trench including sidewalls and a
bottom portion. For example, in step 210, trench 310 can be formed
in a semiconductor substrate (not shown in FIG. 3). The
semiconductor substrate can be, for example, an N type
semiconductor substrate having the same dopant concentration as
drift region 304, which is formed in the semiconductor substrate
after step 210. In some embodiments the semiconductor substrate can
he a support substrate. In other embodiments, the semiconductor
substrate can be formed over a support substrate.
[0029] Trench 310, which can correspond to the trench formed in
step 210, includes sidewalls 312 and bottom portion 314. As shown
in FIG. 3, in contrast to sidewalls 112 in FIG. 1, sidewalls 312
taper into a narrow bottom portion 314. Thus, the uppermost width
between sidewalls 312 can be, for example, approximately 0.3
microns and bottom trench width 322 can be, for example,
approximately 0.19 microns. Upon completion of step 210, trench 310
does not include gate dielectric 316 and gate electrode 318. It is
also noted that after step 210, source regions 308, and channel
regions 306 are formed, for example, by doping the semiconductor
substrate. The doped semiconductor substrate can be eventually
etched to form etched regions 332, 334, and 336.
[0030] Now referring to step 220 of FIG. 2 and FIG. 4, step 220 of
flowchart 200 comprises forming an N type bottom implanted region
surrounding the bottom portion of the trench and having a dopant
concentration greater than that of the semiconductor substrate. It
is noted that step 220 is not required. As such, in other
embodiments, flowchart 200 can transition from step 210 to step 230
without performing step 220. For example, FIG. 3 shows exemplarily
trench FETs 302a and 302b formed without performing step 220.
Conversely, FIG. 4 shows trench FETs 402a and 402b formed after
performing step 220.
[0031] As shown in FIG. 4, semiconductor device 400 includes bottom
implanted region 430, which can correspond to the N type bottom
implanted region formed in step 220. As such, bottom implanted
region 430 can surround the bottom portion of trench 410 and has a
dopant concentration greater than that of the semiconductor
substrate (not shown in FIG. 4). Thus, the dopant concentration of
bottom implanted region 430 can also be greater than that of drift
region 404 in FIG. 4. In the present example, bottom portion 414 of
trench 410 is formed in bottom implanted region 430, which itself
is formed in drift region 404. However, in the example shown in
FIG. 3, bottom portion 314 of trench 310 is formed in drift region
304.
[0032] In semiconductor device 400, bottom implanted region 430 can
account for process variations, which can form a shallower trench
410 than desired. For example, without bottom implanted region 430,
bottom portion 414 may be formed too shallow to sufficiently
contact drift region 404. Thus, bottom implanted region 430 can
enable a shallower trench 410 by maintaining contact between bottom
portion 414 and drift region 404 with process variations.
[0033] Furthermore, because trench FET 402a includes gate
dielectric 416, formed without a thick bottom oxide, bottom
implanted region 430 is not exposed to additional process
temperatures used to form the thick bottom oxide. These additional
process temperatures can prevent formation of an effective and
controllable bottom implanted region, for example, in semiconductor
device 100, by significantly driving deeper the dopants used to
form the bottom implanted region. Controlling dopants is
increasingly important as device dimensions are reduced, for
example, in forming shallow and narrow trench FETs 402a and
402b.
[0034] Referring to step 230 of FIG. 2 and FIG. 3, step 230 of
flowchart 200 comprises forming a substantially uniform gate
dielectric in the trench. As noted above, in one embodiment step
230 can be performed after step 210 while skipping step 220, for
example, resulting in semiconductor device 300 of FIG. 3. In
another embodiment step 230 can be performed after step 220, for
example, resulting in semiconductor device 400 of FIG. 4. Thus, the
substantially uniform gate dielectric formed in step 230 can
correspond to gate dielectric 316 in FIG. 3 and gate dielectric 416
in FIG. 4. Gate dielectric 316 can comprise, for example, thermally
grown silicon oxide (SiO2), and in the present example is formed in
trench 310 lining sidewalls 312 and bottom portion 314 of trench
310. In contrast to transistor 102a in FIG. 1, the thickness of the
portion of gate dielectric 316 lining bottom portion 314 of trench
310 can be substantially equal to the portions of gate dielectric
316 lining respective sidewalls 212 of trench 310.
[0035] Gate dielectric 316 can be formed without a thick bottom
oxide in trench 310. As discussed above, including gate dielectric
116 having thick bottom oxide 140 can reduce gate to drain charge
Q.sub.gd. However, also discussed above, forming thick bottom oxide
140 can introduce significant constraints in device fabrication,
particularly in fabricating shallow and narrow trench FETs. Thus,
in semiconductor device 300, sidewalls 312 of trench 310 taper into
a narrower bottom portion 314. Alternatively, the entire trench 310
can be formed narrowly (with substantially the same small width)
from top to bottom or with a slightly tapered bottom portion.
However, including a narrower bottom portion 314 in forming trench
FET 302a, according to the present invention, can substantially
reduce gate to drain charge Q.sub.gd and overall gate charge
Q.sub.g, thereby significantly enhancing device performance. Thus,
trench FETs 302a and 402a, for example, can be formed without a
thick bottom oxide in respective trenches 310 and 410, while
achieving low gate to drain charge Q.sub.gd.
[0036] Referring now to step 240 of FIG. 2 and FIG. 3, step 240 of
flowchart 200 comprises forming a gate electrode within the trench
and over the gate dielectric. The gate electrode can correspond to
gate electrode 318 of trench FET 302a in FIG. 3 and can comprise,
for example, conductive polysilicon. The gate electrode can be made
coplanar with a top surface of the semiconductor substrate. Thus,
in the present example, gate electrode 318 is shown in FIG. 3
including planar surface 317, which is coplanar with a top surface
of source regions 308. Gate electrode 318 can be made coplanar, for
example, by depositing polysilicon over the semiconductor substrate
and performing a chemical mechanical polishing.
[0037] Forming gate electrode 318 coplanar with a top surface of
the semiconductor substrate can prevent short circuit between gate
electrode 318 and source regions 308 in trench FET 302a. Thus, as
shown in FIG. 3, gate electrode 318 can be formed without a recess,
such as recess 117 in FIG. 1. In the present example, by forming
gate electrode 318 without a recess, source depth 319 can be
reduced without the risk of gate electrode 318 falling below source
regions 308. Thus, channel length 320 and the depth of trench 310
can be further reduced.
[0038] Referring to step 250 of FIG. 2 and FIG. 3, step 250 of
flowchart 200 comprises doping the semiconductor substrate to form
a P type channel region. The P type channel region can correspond,
for example, to any of channel regions 306 in semiconductor device
300. The channel region is thus formed over drift region 304.
Furthermore, in the embodiment shown, the semiconductor substrate
can be doped, for example, using dopant implantation, to form an N
type source region, which can correspond, for example, to any of
source regions 308 in FIG. 3. As shown in the present example,
respective source regions 308 and respective channel regions 306
are adjacent trench 310. Also shown in FIG. 3, in semiconductor
device 300, channel regions 306 are formed over drift region 304,
and source regions 308 are formed over channel regions 306.
[0039] In contrast to conventional methods, in forming, for
example, source regions 308 and channel regions 306, the doped
semiconductor regions are exposed to significantly lower
temperatures and are saved from higher temperature processes that
were associated with trench formation and the related dielectric
growth and deposition in the conventional process flow. Thus, the
present invention prevents an increase in the depth of source
regions 308 and channel regions 306 that would otherwise result
from higher temperature processes in the conventional approach.
Thus, the present invention provides for reduced source depth 319
and channel length 320, enabling a shorter channel length 320 and a
shallower trench 310 in semiconductor device 300.
[0040] For example, in one embodiment, the semiconductor substrate
is doped to form channel regions 306 after forming gate dielectric
316. Thus, the doped semiconductor substrate may not be exposed to,
for example, high thermal oxidation temperatures. As stated
previously, in one embodiment step 250 can be performed after step
230, but before step 240, of flowchart 200. However, in the
embodiment shown in FIG. 2, the semiconductor substrate is doped to
form channel regions 306 after forming gate dielectric 316 and gate
electrode 318, i.e. step 250 is performed after both steps 230 and
240. In this way, the doped semiconductor substrate may not be
exposed to, additional significant process temperatures for forming
gate electrode 318.
[0041] Thus, in one specific example, in trench FET 302a, source
depth 319 can be, for example, 0.15 microns and channel length 320
can be, for example, approximately 0.3 to 0.45 microns. By way of
example, the depth of trench 310 can be approximately 0.6 to 0.8
microns. As such, ON-resistance R.sub.dson can be significantly
reduced compared to, for example, transistor 102a in FIG. 1.
[0042] After completion of step 250, additional steps can be
performed in order to form semiconductor device 300 in FIG. 3 or
semiconductor device 400 in FIG. 4. For example, additional layers
can be formed over the semiconductor substrate. Furthermore, in
some embodiments, dielectric portions 324, 326, and 328 can be
formed over source regions 308 and trench 310 by performing an
etching step to form etched regions 332, 334, and 336. Dielectric
materials 324, 326, and 328 can comprise, for example, SiO.sub.2,
and can insulate gate electrode 318 from source contact material
327.
[0043] Thus, as discussed above, in the embodiments of FIGS. 2, 3,
and 4, the invention provides a method for fabricating
semiconductor devices including a shallow and narrow trench FET and
related structures. From the above description of the invention it
is manifest that various techniques can be used for implementing
the concepts of the present invention without departing from its
scope. Moreover, while the invention has been described with
specific reference to certain embodiments, a person of ordinary
skill in the art would recognize that changes can be made in form
and detail without departing from is the spirit and the scope of
the invention. The described embodiments are to be considered in
all respects as illustrative and not restrictive. It should also be
understood that the invention is not limited to the particular
embodiments described herein, but is capable of many
rearrangements, modifications, and substitutions without departing
from the scope of the invention.
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