U.S. patent application number 15/218717 was filed with the patent office on 2017-03-23 for semiconductor device and method of forming an alignment structure in backside of a semiconductor die.
This patent application is currently assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC. The applicant listed for this patent is SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC. Invention is credited to Francis J. CARNEY, Chee Hiong CHEW, Michael J. SEDDON, Soon Wei WANG.
Application Number | 20170084545 15/218717 |
Document ID | / |
Family ID | 58283128 |
Filed Date | 2017-03-23 |
United States Patent
Application |
20170084545 |
Kind Code |
A1 |
SEDDON; Michael J. ; et
al. |
March 23, 2017 |
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN ALIGNMENT STRUCTURE
IN BACKSIDE OF A SEMICONDUCTOR DIE
Abstract
A semiconductor device has a semiconductor die containing a base
material having an active surface and a back surface opposite the
active surface. A portion of the base material is removed by plasma
etching to form an alignment recess in the base material.
Alternatively, an alignment protrusion is formed over the base
material. The alignment recess or alignment protrusion make a
non-uniform surface. The semiconductor die is disposed over a
substrate with a portion of the substrate, such as a die pad,
positioned within the alignment recess. The die pad may be disposed
partially or completely within the alignment recess of the base
material. The base material may extend beyond the die pad, or the
alignment recess or alignment protrusion may extend a length of the
base material. A metal layer can be formed in the alignment recess
of the base material.
Inventors: |
SEDDON; Michael J.;
(Gilbert, AZ) ; CARNEY; Francis J.; (Mesa, AZ)
; CHEW; Chee Hiong; (Seremban, MY) ; WANG; Soon
Wei; (Seremban, MY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC |
Phoenix |
AZ |
US |
|
|
Assignee: |
SEMICONDUCTOR COMPONENTS
INDUSTRIES, LLC
Phoenix
AZ
|
Family ID: |
58283128 |
Appl. No.: |
15/218717 |
Filed: |
July 25, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62219666 |
Sep 17, 2015 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/05172
20130101; H01L 24/00 20130101; H01L 23/481 20130101; H01L 23/49811
20130101; H01L 27/14625 20130101; H01L 27/14685 20130101; H01L
22/26 20130101; H01L 2224/05083 20130101; H01L 23/49866 20130101;
H01L 2224/02166 20130101; H01L 23/49575 20130101; H01L 2224/05139
20130101; H01L 2224/11334 20130101; H01L 21/76877 20130101; H01L
2223/5446 20130101; H01L 2224/05164 20130101; H01L 23/3107
20130101; H01L 23/3114 20130101; H01L 2224/0401 20130101; H01L
2924/13055 20130101; H01L 2924/13091 20130101; H01L 21/76898
20130101; H01L 2224/05144 20130101; H01L 2224/05647 20130101; H01L
2224/05655 20130101; H02M 3/158 20130101; H01L 21/4825 20130101;
H01L 27/14 20130101; H01L 2224/05166 20130101; H01L 21/486
20130101; H01L 21/78 20130101; H01L 23/4951 20130101; H01L 27/0207
20130101; H01L 2225/06596 20130101; H01L 2224/05084 20130101; H01L
21/3065 20130101; H01L 23/49562 20130101; H01L 2223/54426 20130101;
H01L 2224/05147 20130101; H01L 25/50 20130101; H01L 23/49816
20130101; H01L 2224/04042 20130101; H01L 2224/13025 20130101; H01L
21/304 20130101; H01L 21/4853 20130101; H01L 21/565 20130101; H01L
24/05 20130101; H01L 25/0657 20130101; H01L 2224/13111 20130101;
H01L 2224/05171 20130101; H01L 24/13 20130101; H01L 2221/68327
20130101; H01L 2224/05124 20130101; H01L 21/308 20130101; H01L
21/6835 20130101; H01L 27/14683 20130101; H01L 2224/05639 20130101;
H01L 21/02035 20130101; H01L 22/12 20130101; H01L 23/49503
20130101; H01L 23/49827 20130101; H01L 2225/06555 20130101; H01L
21/288 20130101; H01L 23/562 20130101; H01L 2224/05664 20130101;
H01L 23/544 20130101; H01L 24/11 20130101; H01L 27/088 20130101;
H01L 2224/05184 20130101; H01L 2924/3511 20130101; H01L 23/49541
20130101; H01L 2224/05644 20130101; H01L 21/67069 20130101; H01L
23/147 20130101; H01L 23/49838 20130101; H01L 29/0847 20130101;
H01L 21/3083 20130101; H01L 2224/05155 20130101; H01L 2224/05572
20130101; H01L 2224/13022 20130101; H01L 2224/13021 20130101; H01L
2224/13116 20130101; H01L 2225/06593 20130101; H01L 2924/10155
20130101; H01L 23/3677 20130101; H01L 23/15 20130101; H01L 25/0655
20130101; H01L 2224/05672 20130101; H01L 23/4822 20130101; H01L
2924/3511 20130101; H01L 2924/00 20130101; H01L 2924/3511 20130101;
H01L 2924/00012 20130101; H01L 2224/05664 20130101; H01L 2924/00014
20130101; H01L 2224/13116 20130101; H01L 2924/014 20130101; H01L
2924/0105 20130101; H01L 2924/00014 20130101; H01L 2224/05166
20130101; H01L 2924/013 20130101; H01L 2924/01084 20130101; H01L
2924/00014 20130101; H01L 2224/13111 20130101; H01L 2924/014
20130101; H01L 2924/01082 20130101; H01L 2924/00014 20130101; H01L
2224/05166 20130101; H01L 2924/00014 20130101; H01L 2224/05184
20130101; H01L 2924/013 20130101; H01L 2924/01022 20130101; H01L
2924/00014 20130101; H01L 2224/05672 20130101; H01L 2924/013
20130101; H01L 2924/01028 20130101; H01L 2924/00014 20130101; H01L
2224/05171 20130101; H01L 2924/00014 20130101; H01L 2224/05147
20130101; H01L 2924/00014 20130101; H01L 2224/05647 20130101; H01L
2924/013 20130101; H01L 2924/00014 20130101; H01L 2224/05155
20130101; H01L 2924/00014 20130101; H01L 2224/05655 20130101; H01L
2924/013 20130101; H01L 2924/01023 20130101; H01L 2924/00014
20130101; H01L 2224/05639 20130101; H01L 2924/00014 20130101; H01L
2224/05644 20130101; H01L 2924/00014 20130101; H01L 2224/05124
20130101; H01L 2924/00014 20130101 |
International
Class: |
H01L 23/544 20060101
H01L023/544; H01L 23/00 20060101 H01L023/00; H01L 23/31 20060101
H01L023/31; H01L 21/3065 20060101 H01L021/3065; H01L 21/78 20060101
H01L021/78 |
Claims
1. A method of making a semiconductor device, comprising: providing
a semiconductor die including a base material; and removing a
portion of the base material to form an alignment recess or
alignment protrusion in a surface of the base material.
2. The method of claim 1, further including: providing a substrate;
and disposing the semiconductor die over the substrate with a
portion of the substrate within the alignment recess.
3. The method of claim 2, wherein the substrate includes a
leadframe, interposer, or semiconductor die.
4. The method of claim 2, wherein the portion of the substrate is
disposed partially within the alignment recess of the base
material.
5. The method of claim 1, further including utilizing plasma
etching to remove the portion of the base material.
6. The method of claim 1, wherein the alignment recess extends a
length of the base material.
7. A semiconductor device, comprising: a semiconductor die
including a base material; and an alignment recess or alignment
protrusion formed in a surface of the base material.
8. The semiconductor device of claim 7, further including a
substrate, wherein the semiconductor die is disposed over the
substrate with a portion of the substrate within the alignment
recess.
9. The semiconductor device of claim 8, wherein the portion of the
substrate includes a die pad.
10. The semiconductor device of claim 8, wherein the portion of the
substrate is disposed partially within the alignment recess of the
base material.
11. The semiconductor device of claim 7, further including a
substrate, wherein the semiconductor die is disposed over a
substrate with a portion of the alignment protrusion within a
recess of the substrate.
12. The semiconductor device of claim 7, wherein the alignment
recess or alignment protrusion extends a length of the base
material.
13. The semiconductor device of claim 7, further including a metal
layer formed in the alignment recess of the base material.
14. A semiconductor device, comprising a semiconductor die
including a base material comprising a first surface and a
non-uniform second surface for alignment.
15. The semiconductor device of claim 14, wherein the non-uniform
second surface includes an alignment recess or alignment
protrusion.
16. The semiconductor device of claim 15, further including a
substrate, wherein the semiconductor die is disposed over the
substrate with a portion of the substrate within the alignment
recess.
17. The semiconductor device of claim 16, wherein the portion of
the substrate includes a die pad.
18. The semiconductor device of claim 16, wherein the portion of
the substrate is disposed partially within the alignment recess of
the base material.
19. The semiconductor device of claim 15, further including a metal
layer formed in the alignment recess of the base material.
20. The semiconductor device of claim 15, further including a
substrate, wherein the semiconductor die is disposed over a
substrate with a portion of the alignment protrusion within a
recess of the substrate.
Description
CLAIM TO DOMESTIC PRIORITY
[0001] The present application claims the benefit of U.S.
Provisional Application No. 62/219,666, filed Sep. 17, 2015,
entitled "SEMICONDUCTOR PACKAGES AND METHODS" invented by Francis
J. CARNEY and Michael J. SEDDON, and which is incorporated herein
by reference and priority thereto for common subject matter is
hereby claimed.
FIELD OF THE INVENTION
[0002] The present invention relates in general to semiconductor
devices and, more particularly, to a semiconductor device and
method of forming an alignment notch or alignment protrusion in
backside of a semiconductor die.
BACKGROUND
[0003] Semiconductor devices are commonly found in modern
electronic products. Semiconductor devices vary in the number and
density of electrical components. Semiconductor devices perform a
wide range of functions such as analog and digital signal
processing, sensors, transmitting and receiving electromagnetic
signals, controlling electronic devices, power management, and
audio/video signal processing. Discrete semiconductor devices
generally contain one type of electrical component, e.g., light
emitting diode (LED), small signal transistor, resistor, capacitor,
inductor, diodes, rectifiers, thyristors, and power
metal-oxide-semiconductor field-effect transistor (MOSFET).
Integrated semiconductor devices typically contain hundreds to
millions of electrical components. Examples of integrated
semiconductor devices include microcontrollers, application
specific integrated circuits (ASIC), standard logic, amplifiers,
clock management, memory, interface circuits, and other signal
processing circuits.
[0004] A need exists in the semiconductor industry for smaller
package size so that the end products, such as cell phones,
computers, and watches, can be reduced in size and weight. Advanced
micro packaging and multichip packaging require precise die
alignment tolerances. The die placement accuracy is dependent on
variation in die size due to wafer saw, placement accuracy during
pick and place operations, movement during reflow, and shifting or
sliding off of a die pedestal within micro packaging. The alignment
tolerance adds to the overall package dimensions and spacing
limitations.
[0005] Common micro packaging relies on semiconductor die which are
only partially placed on a planar surface of a die pad in order to
meet the customer footprint requirements, i.e., the semiconductor
die overhangs the die pad. FIG. 1a shows semiconductor die 50
partially placed on a planar surface of die pad 52 with a portion
of the planar back surface 53 of the semiconductor die overhanging
the die pad. Semiconductor die 50 is bonded to die pad 52 with an
adhesive and active surface 54 is coupled to wire bond pad 56 with
bond wire 58. Die pad 52 and wire bond pad 56 are integral
components of a leadframe. An encapsulant 60 covers semiconductor
die 50, wire bond pad 56, and bond wire 58.
[0006] Given the overhang of the planar back surface 53 of
semiconductor die 50 with respect to the planar surface of die pad
52, semiconductor die 50 is susceptible to tilting, rotation,
slipping off, or other undesired movement on die pad 52 during the
manufacturing process. The planar back surface 53 of semiconductor
die 50 may detach or otherwise shift in position with respect to
die pad 52 by improper alignment, or by adhesive failure and
tension of bond wire 58, as shown in FIG. 1b. Holding semiconductor
die 50 to exact alignment tolerances is difficult and can lead to
bond wire sweep, bond wire disconnect, or shorting of the bond
wires. Since die pad 52 must be kept small in order to meet the
customer footprint requirements, the die size is limited because of
the relatively small die overhang that can be used before
semiconductor die 50 becomes susceptible to slipping, tilting,
rotation, or detachment from the die pad. The movement of large
semiconductor die 50 with respect to small die pad 52 may
constitute a manufacturing defect and reduce production yield.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIGS. 1a-1b illustrate a common mounting arrangement between
a larger semiconductor die and smaller die pad;
[0008] FIGS. 2a-2c illustrate a semiconductor wafer with a
plurality of semiconductor die separated by a saw street;
[0009] FIGS. 3a-3e illustrate a process of forming an alignment
notch in a back surface of the semiconductor die;
[0010] FIG. 4 illustrates a semiconductor package with the
semiconductor die mounted to a die pad within the backside
alignment notch;
[0011] FIG. 5 illustrates another semiconductor package with the
semiconductor die mounted to a die pad partially within the
backside alignment notch;
[0012] FIG. 6 illustrates another semiconductor package with the
semiconductor die mounted to a die pad partially within the
backside alignment notch;
[0013] FIGS. 7a-7g illustrate another process of forming an
alignment notch with backside metal;
[0014] FIG. 8 illustrates another semiconductor package with the
semiconductor die mounted to a die pad within the backside metal
alignment notch;
[0015] FIG. 9 illustrates another semiconductor package with the
semiconductor die mounted to a die pad partially within the
backside metal alignment notch;
[0016] FIGS. 10a-10c illustrate semiconductor die with elongated
alignment notches mated to protrusions formed over a substrate;
[0017] FIGS. 11a-11c illustrate semiconductor die with cross-shaped
alignment notches mated to cross-shaped protrusions formed over a
substrate;
[0018] FIGS. 12a-12c illustrate semiconductor die with elongated
alignment protrusions mated to recesses formed in a substrate;
[0019] FIGS. 13a-13c illustrate semiconductor die with cross-shaped
alignment protrusions mated to cross-shaped recesses formed in a
substrate;
[0020] FIGS. 14a-14b illustrate semiconductor die with alignment
recesses or protrusions mated to corresponding structures formed in
a PCB; and
[0021] FIGS. 15a-15c illustrate a semiconductor die with alignment
protrusions inserted into mating openings formed through a
substrate.
DETAILED DESCRIPTION OF THE DRAWINGS
[0022] The following describes one or more embodiments with
reference to the figures, in which like numerals represent the same
or similar elements. While the figures are described in terms of
the best mode for achieving certain objectives, the description is
intended to cover alternatives, modifications, and equivalents as
may be included within the spirit and scope of the disclosure. The
term "semiconductor die" as used herein refers to both the singular
and plural form of the words, and accordingly, can refer to both a
single semiconductor device and multiple semiconductor devices.
[0023] Semiconductor devices are generally manufactured using two
complex manufacturing processes: front-end manufacturing and
back-end manufacturing. Front-end manufacturing involves the
formation of a plurality of die on the surface of a semiconductor
wafer. Each die on the wafer may contain active and passive
electrical components and optical devices, which are electrically
connected to form functional electrical circuits. Active electrical
components, such as transistors and diodes, have the ability to
control the flow of electrical current. Passive electrical
components, such as capacitors, inductors, and resistors, create a
relationship between voltage and current necessary to perform
electrical circuit functions. The optical device detects and
records an image by converting the variable attenuation of light
waves or electromagnetic radiation into electric signals.
[0024] Back-end manufacturing refers to cutting or singulating the
finished wafer into the individual semiconductor die and packaging
the semiconductor die for structural support, electrical
interconnect, and environmental isolation. The wafer is singulated
using plasma etching, laser cutting tool, or saw blade along
non-functional regions of the wafer called saw streets or scribes.
After singulation, the individual semiconductor die are mounted to
a package substrate that includes pins or contact pads for
interconnection with other system components. Contact pads formed
over the semiconductor die are then connected to contact pads
within the package. The electrical connections can be made with
conductive layers, bumps, stud bumps, conductive paste, or
wirebonds. An encapsulant or other molding material is deposited
over the package to provide physical support and electrical
isolation. The finished package is then inserted into an electrical
system and the functionality of the semiconductor device is made
available to the other system components.
[0025] FIG. 2a shows semiconductor wafer 100 with a base substrate
material 102, such as silicon, germanium, aluminum phosphide,
aluminum arsenide, gallium arsenide, gallium nitride, indium
phosphide, silicon carbide, or other bulk semiconductor material
for structural support. A plurality of semiconductor die 104 is
formed on wafer 100 separated by a non-active, inter-die wafer area
or saw street 106, as described above. Saw street 106 provides
cutting areas to singulate semiconductor wafer 100 into individual
semiconductor die 104. In one embodiment, semiconductor wafer 100
has a width or diameter of 100-450 millimeters (mm) and thickness
of 50-100 micrometers (.mu.m) or 15-250 .mu.m.
[0026] FIG. 2b shows a cross-sectional view of a portion of
semiconductor wafer 100. Each semiconductor die 104 has a back or
non-active surface 108 and an active surface or region 110
containing analog or digital circuits implemented as active
devices, passive devices, conductive layers, and dielectric layers
formed within the die and electrically interconnected according to
the electrical design and function of the die. For example, the
circuit may include one or more transistors, diodes, and other
circuit elements formed within active surface or region 110 to
implement analog circuits or digital circuits, such as digital
signal processor (DSP), microcontrollers, ASIC, standard logic,
amplifiers, clock management, memory, interface circuits, and other
signal processing circuit. Semiconductor die 104 may also contain
integrated passive devices (IPDs), such as inductors, capacitors,
and resistors, for RF signal processing. Active surface 110 may
contain an image sensor area implemented as semiconductor
charge-coupled devices (CCD) and active pixel sensors in
complementary metal-oxide-semiconductor (CMOS) or N-type
metal-oxide-semiconductor (NMOS) technologies. Alternatively,
semiconductor die 104 can be an optical lens, detector, vertical
cavity surface emitting laser (VCSEL), waveguide, stacked die,
electromagnetic (EM) filter, or multi-chip module.
[0027] An electrically conductive layer 112 is formed over active
surface 110 using PVD, CVD, electrolytic plating, electroless
plating process, or other suitable metal deposition process.
Conductive layer 112 includes one or more layers of aluminum (Al),
copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag),
titanium (Ti), titanium tungsten (TiW), or other suitable
electrically conductive material. Conductive layer 112 operates as
contact pads electrically connected to the circuits on active
surface 110. Conductive layer 112 can be formed as contact pads
disposed side-by-side along an edge of semiconductor die 104, as
shown in FIG. 2b. Alternatively, conductive layer 112 can be formed
as contact pads that are offset in multiple rows such that a first
row of contact pads is disposed a first distance from the edge of
the die, and a second row of contact pads alternating with the
first row is disposed a second distance from the edge of the
die.
[0028] Semiconductor wafer 100 undergoes electrical testing and
inspection as part of a quality control process. Manual visual
inspection and automated optical systems are used to perform
inspections on semiconductor wafer 100. Software can be used in the
automated optical analysis of semiconductor wafer 100. Visual
inspection methods may employ equipment such as a scanning electron
microscope, high-intensity or ultra-violet light, or metallurgical
microscope. Semiconductor wafer 100 is inspected for structural
characteristics including warpage, thickness variation, surface
particulates, irregularities, cracks, delamination, and
discoloration.
[0029] The active and passive components within semiconductor die
104 undergo testing at the wafer level for electrical performance
and circuit function. Each semiconductor die 104 is tested for
functionality and electrical parameters, as shown in FIG. 2c, using
a test probe head 116 including a plurality of probes or test leads
118, or other testing device. Probes 118 are used to make
electrical contact with nodes or conductive layer 112 on each
semiconductor die 104 and provide electrical stimuli to contact
pads 112. Semiconductor die 104 responds to the electrical stimuli,
which is measured by computer test system 119 and compared to an
expected response to test functionality of the semiconductor die.
The electrical tests may include circuit functionality, lead
integrity, resistivity, continuity, reliability, junction depth,
ESD, RF performance, drive current, threshold current, leakage
current, and operational parameters specific to the component type.
The inspection and electrical testing of semiconductor wafer 100
enables semiconductor die 104 that pass to be designated as known
good die (KGD) for use in a semiconductor package.
[0030] FIGS. 3a-3e illustrate a process of forming an alignment
notch in back surface 108 of semiconductor die 104. In FIG. 3a, a
portion of back surface 108 is removed by grinder 120 in a
backgrinding operation. The backgrinding operation reduces a
thickness of base substrate material 102 to surface 122 of the base
substrate material. In one embodiment, semiconductor wafer 100 has
a post-grinding thickness of 100 .mu.m.
[0031] In FIG. 3b, semiconductor wafer 100 is inverted and a
masking layer 126 is disposed over surface 122 of base substrate
material 102. Masking layer 126 can be implemented as a photoresist
layer or oxide layer with openings 128 extending to surface
122.
[0032] In FIG. 3c, surface 122 is plasma etched through openings
128 in masking layer 126 to form alignment notches or keyed
recesses 130 in base substrate material 102 while in wafer form of
FIG. 2a. Alternatively, alignment notches or keyed recesses 130 in
base substrate material 102 can be formed by laser direct ablation
(LDA) or other wet or dry chemical etching process.
[0033] In FIG. 3d, masking layer 126 is removed. Semiconductor die
104 are shown with alignment notches or keyed recesses 130 having
side surfaces 132 and back surface 134 in base substrate material
102. Alignment notches 130 make a non-uniform thickness or surface
of base substrate material 102.
[0034] In FIG. 3e, semiconductor wafer 100 is disposed over film
frame or backing tape 136 with surface 122 and alignment notches
130 oriented toward the film frame. Semiconductor wafer 100 is
singulated through saw street 106 into individual semiconductor die
104 using plasma etching. Plasma etching has advantages of removing
base substrate 102 to form precision surfaces, while retaining the
structure and integrity of the base substrate material.
Alternatively, semiconductor wafer 100 is singulated through saw
street 106 using a saw blade or laser cutting tool 137 into
individual semiconductor die 104. The individual semiconductor die
104 can be inspected and electrically tested for identification of
KGD post singulation.
[0035] FIG. 4 illustrates a semiconductor package 138 containing
semiconductor die 104 with alignment notch or keyed recess 130
formed in base substrate material 102 disposed over die pad 140. In
particular, surfaces 132 and 134 of notch 130 provide alignment for
mounting semiconductor die 104 to die pad 140. In one embodiment,
die pad 140 has thickness of 30-40 .mu.m and semiconductor die 104
has thickness of 50-100 .mu.m. Semiconductor die 104 is larger than
die pad 140 resulting in a significant extension of base substrate
material 102 beyond the die pad. Die pad 140 is completely
contained with alignment notch 130 to securely hold semiconductor
die 104 to the die pad. The smaller die pad 140 allows for smaller
semiconductor package dimensions and package footprint to meet
industry demands. Even with the smaller die pad 140, semiconductor
die 104 is robust against laterally slippage, tilting, shifting, or
detachment with respect to the die pad because the surfaces of the
die pad are disposed within notch 130. Semiconductor die 104 can be
significantly larger than die pad 140 with the use of alignment
notch 130, while avoiding the manufacturing slippage, tilt,
rotation, or detachment defect noted in FIGS. 1a-1b.
[0036] Bond wire 144 is connected between conductive layer or
contact pad 112 on active surface 110 and wire bond pad 146. Die
pad 140 and wire bond pad 146 represent a portion of a leadframe,
substrate, interposer, or semiconductor die. An optional insulating
layer 148 is formed over surface 122 of semiconductor die 104 using
PVD, CVD, printing, spin coating, spray coating, sintering or
thermal oxidation. The insulating layer 148 contains one or more
layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having
similar insulating and structural properties. Insulating layer 148
is exposed from semiconductor package 138. An encapsulant or
molding compound 150 is deposited over semiconductor die 104, bond
wire 144, and wire bond pad 146 using a compressive molding,
transfer molding, liquid encapsulant molding, vacuum lamination, or
other suitable applicator. Encapsulant 150 can be polymer composite
material, such as epoxy resin with filler, epoxy acrylate with
filler, or polymer with proper filler. Encapsulant 150 is
non-conductive, provides physical support, and environmentally
protects the semiconductor device from external elements and
contaminants.
[0037] FIG. 5 illustrates a semiconductor package 160, similar to
FIG. 4, containing semiconductor die 104 with a shallow alignment
notch or keyed recess 130 formed in base substrate material 102
disposed over die pad 162. In particular, surfaces 132 and 134 of
notch 130 provide alignment for mounting semiconductor die 104 to
die pad 162. Semiconductor die 104 is larger than die pad 162
resulting in a significant extension or overhang of base substrate
material 102 beyond the die pad. Die pad 162 is partially contained
with alignment notch 130 to securely hold semiconductor die 104 to
the die pad. A portion of die pad 162 extends vertically outside
alignment notch 130. The smaller die pad 162 allows for smaller
semiconductor package dimensions and package footprint to meet
industry demands. Even with the smaller die pad 162, semiconductor
die 104 is robust against laterally slippage, tilting, shifting, or
detachment with respect to the die pad because the surfaces of the
die pad are disposed at least partially within notch 130.
Semiconductor die 104 can be significantly larger than die pad 162
with the use of alignment notch 130, while avoiding the
manufacturing slippage, tilt, rotation, or detachment defect noted
in FIGS. 1a-1b.
[0038] Bond wire 164 is connected between conductive layer or
contact pad 112 on active surface 110 and wire bond pad 166. Die
pad 162 and wire bond pad 166 represent a portion of a leadframe,
substrate, interposer, or semiconductor die. An encapsulant or
molding compound 170 is deposited over semiconductor die 104, bond
wire 164, and wire bond pad 166 using a compressive molding,
transfer molding, liquid encapsulant molding, vacuum lamination, or
other suitable applicator. Encapsulant 170 can be polymer composite
material, such as epoxy resin with filler, epoxy acrylate with
filler, or polymer with proper filler. Encapsulant 170 is
non-conductive, provides physical support, and environmentally
protects the semiconductor device from external elements and
contaminants.
[0039] FIG. 6 illustrates a semiconductor package 180, similar to
FIG. 5, containing semiconductor die 104 with a shallow alignment
notch or keyed recess 130 formed in base substrate material 102
disposed over die pad 182. In particular, surfaces 132 and 134 of
notch 130 provide alignment for mounting semiconductor die 104 to
die pad 182. Semiconductor die 104 is larger than die pad 182
resulting in a significant extension or overhang of base substrate
material 102 beyond the die pad. Die pad 182 is partially contained
with alignment notch 130 to securely hold semiconductor die 104 to
the die pad. A portion of die pad 182 extends vertically outside
alignment notch 130. The smaller die pad 182 allows for smaller
semiconductor package dimensions and package footprint to meet
industry demands. The alignment of semiconductor die 104 with
alignment notch 130 to die pad 182 can be offset for reliable and
repeatable wirebonding.
[0040] Bond wire 184 is connected between conductive layer or
contact pad 112 on active surface 110 and wire bond pad 186. Die
pad 182 and wire bond pad 186 represent a portion of a leadframe,
substrate, interposer, or semiconductor die. An encapsulant or
molding compound 190 is deposited over semiconductor die 104, bond
wire 184, and wire bond pad 186 using a compressive molding,
transfer molding, liquid encapsulant molding, vacuum lamination, or
other suitable applicator. Encapsulant 190 can be polymer composite
material, such as epoxy resin with filler, epoxy acrylate with
filler, or polymer with proper filler. Encapsulant 190 is
non-conductive, provides physical support, and environmentally
protects the semiconductor device from external elements and
contaminants.
[0041] In general, alignment notch 130 can be a one-sided,
two-sided, three-sided, or four-sided sidewall structure to
partially or completely contain the die pad. Notch 130 provides
alignment in mounting semiconductor die 104 to the die pad, as well
as stiffness and stability for the semiconductor die. Semiconductor
die 104 is robust against laterally slippage, tilting, shifting, or
detachment with respect to the die pad because the surfaces of the
die pad are disposed at least partially within notch 130. Alignment
notch 130 allows for thinner semiconductor die 104 to accommodate
the height requirements of the bond wires in a thinner
semiconductor package, while avoiding the manufacturing slippage,
tilt, rotation, or detachment defect.
[0042] FIGS. 7a-7g illustrate another process of forming an
alignment notch in back surface 108 of semiconductor die 104 with
backside metal within the notch. Continuing from FIG. 2c, a portion
of back surface 108 is removed by grinder 200 in a backgrinding
operation. The backgrinding operation reduces a thickness of base
substrate material 102 and exposes surface 202 of the base
substrate material. FIG. 7b shows semiconductor wafer 100 after the
backgrinding operation.
[0043] In FIG. 7c, semiconductor wafer 100 is inverted and a
masking layer 206 is disposed over surface 202 of base substrate
material 102. Masking layer 206 can be implemented as a photoresist
layer or oxide layer with openings 208 extending to surface
202.
[0044] In FIG. 7d, surface 202 is plasma etched through openings
208 in masking layer 206 to form alignment notches or keyed
recesses 210 in base substrate material 102 while in wafer form of
FIG. 2a. Alternatively, alignment notches or keyed recesses 210 in
base substrate material 102 can be formed by LDA or other wet or
dry chemical etching process. Alignment notches 210 have side
surfaces 212 and back surface 214. Alignment notches 210 make a
non-uniform thickness or surface of base substrate material
102.
[0045] In FIG. 7e, an electrically conductive layer 216 is formed
over masking layer 206 and into alignment notches or keyed recesses
210 using PVD, CVD, electrolytic plating, electroless plating
process, or other suitable metal deposition process. Conductive
layer 216 includes one or more layers of Al, Cu, Sn, Ni, Au, Ag,
Ti, TiW, or other suitable electrically conductive material or
combination thereof. Conductive layer 216 operates a backside metal
in alignment notches 210 of base substrate material 102 for
electrical interconnect or heat dissipation.
[0046] In FIG. 7f, masking layer 206 is removed taking along with
it the portion of conductive layer 216 formed over the masking
layer. Semiconductor die 104 are shown with alignment notches or
keyed recesses 210 having side surfaces 212 and back surface 214 in
base substrate material 102. Conductive layer 216 remains within
alignment notches 210.
[0047] In FIG. 7g, semiconductor wafer 100 is disposed over film
frame or backing tape 218 with surface 202 and alignment notches
210 oriented toward the film frame. Semiconductor wafer 100 is
singulated through saw street 106 into individual semiconductor die
104 using plasma etching. Plasma etching has advantages of removing
base substrate material 102 to form precision surfaces, while
retaining the structure and integrity of the base substrate
material. Alternatively, semiconductor wafer 100 is singulated
through saw street 106 using a saw blade or laser cutting tool 220
into individual semiconductor die 104. The individual semiconductor
die 104 can be inspected and electrically tested for identification
of known good die post singulation. Alternatively, active surface
110 of semiconductor wafer 100 can be oriented toward film frame
218 while the wafer is singulated using any of the aforementioned
methods.
[0048] FIG. 8 illustrates a semiconductor package 230 containing
semiconductor die 104 with alignment notch or keyed recess 210
formed in base substrate material 102 containing back metal
conductive layer 216 disposed over die pad 232. In particular,
surfaces 212 and 214 of notch 210 provide alignment for mounting
semiconductor die 104 to die pad 232. Semiconductor die 104 is
larger than die pad 232 resulting in a significant extension of
base substrate material 102 beyond the die pad. Die pad 232 is
completely contained with alignment notch 210 to securely hold
semiconductor die 104 to the die pad. The smaller die pad 232
allows for smaller semiconductor package dimensions and package
footprint to meet industry demands. Backside metal conductive layer
216 provides electrical interconnect or heat dissipation. Even with
the smaller die pad 232, semiconductor die 104 is robust against
laterally slippage, tilting, shifting, or detachment with respect
to the die pad because the surfaces of the die pad are disposed
within notch 210. Semiconductor die 104 can be significantly larger
than die pad 232 with the use of alignment notch 210 containing
back metal conductive layer 216, while avoiding the manufacturing
slippage, tilt, rotation, or detachment defect noted in FIGS.
1a-1b.
[0049] Bond wire 234 is connected between conductive layer 112 on
active surface 110 and wire bond pad 236. Die pad 232 and wire bond
pad 236 represent a portion of a leadframe, substrate, interposer,
or semiconductor die. An encapsulant or molding compound 240 is
deposited over semiconductor die 104, bond wire 234, and wire bond
pad 236 using a compressive molding, transfer molding, liquid
encapsulant molding, vacuum lamination, or other suitable
applicator. Encapsulant 240 can be polymer composite material, such
as epoxy resin with filler, epoxy acrylate with filler, or polymer
with proper filler. Encapsulant 240 is non-conductive, provides
physical support, and environmentally protects the semiconductor
device from external elements and contaminants.
[0050] FIG. 9 illustrates a semiconductor package 250, similar to
FIG. 8, containing semiconductor die 104 with a shallow alignment
notch or keyed recess 210 formed in base substrate material 102 and
containing back metal conductive layer 216 disposed over die pad
252. In particular, surfaces 212 and 214 of notch 210 provide
alignment for mounting semiconductor die 104 to die pad 252.
Semiconductor die 104 is larger than die pad 252 resulting in a
significant extension or overhang of base substrate material 102
beyond the die pad. Die pad 252 is partially contained with
alignment notch 210 to securely hold semiconductor die 104 to the
die pad. A portion of die pad 252 extends vertically outside notch
210. The smaller die pad 252 allows for smaller semiconductor
package dimensions and package footprint to meet industry demands.
Backside metal conductive layer 216 provides electrical
interconnect or heat dissipation. Even with the smaller die pad
252, semiconductor die 104 is robust against laterally slippage,
tilting, shifting, or detachment with respect to the die pad
because the surfaces of the die pad are disposed within notch 210.
Semiconductor die 104 can be significantly larger than die pad 252
with the use of alignment notch 210, while avoiding the
manufacturing slippage, tilt, rotation, or detachment defect noted
in FIGS. 1a-1b.
[0051] Bond wire 254 is connected between conductive layer 112 on
active surface 110 and wire bond pad 256. Die pad 252 and wire bond
pad 256 represent a portion of a leadframe, substrate, interposer,
or semiconductor die. An encapsulant or molding compound 260 is
deposited over semiconductor die 104, bond wire 254, and wire bond
pad 256 using a compressive molding, transfer molding, liquid
encapsulant molding, vacuum lamination, or other suitable
applicator. Encapsulant 260 can be polymer composite material, such
as epoxy resin with filler, epoxy acrylate with filler, or polymer
with proper filler. Encapsulant 260 is non-conductive, provides
physical support, and environmentally protects the semiconductor
device from external elements and contaminants.
[0052] FIGS. 10a-10c illustrate semiconductor die with elongated
alignment notches formed in the back surface of the die and mounted
to mating protrusions formed over a substrate. FIG. 10a is an
orthogonal view of semiconductor die 270 including an elongated
alignment notch 272 formed in back surface 274 between side
surfaces 276 of the semiconductor die using plasma etching, wet
etching, milling, laser, or dry etching. Likewise, semiconductor
die 278 includes an elongated alignment notch 279 formed in back
surface 280 between side surfaces 281 of the semiconductor die
using plasma etching, wet etching, milling, laser, or dry etching.
Semiconductor die 270 and 278 can be rectangular, circular, oval,
or other geometric shape. Semiconductor die 270 and 278 can be an
ASIC, sensor, optical device, detector, VCSEL, waveguide, and
multi-chip module. Semiconductor die 270 and 278 are positioned
over substrate 282 with alignment protrusions 283. Substrate 282
can be a printed circuit board (PCB), flexible wiring harness,
ceramic board, or glass substrate. Substrate 282 can also be a
leadframe, interposer, or semiconductor die. Notches 272 and 279
are aligned with substrate protrusions 283.
[0053] FIG. 10b is a bottom view of semiconductor die 270 with
alignment notch 272 formed in back surface 274 between side
surfaces 276 of the semiconductor die, and semiconductor die 278
with alignment notch 279 formed in back surface 280 between side
surfaces 281 of the semiconductor die.
[0054] In FIG. 10c, semiconductor die 270 and 278 are mounted to
substrate 282 with precise alignment as notches 272 and 279 are
inserted into substrate protrusions 283. Alignment notches 272 and
279 and substrate protrusions 283 provide a keyed recess for easy
placement and precise alignment of semiconductor die 270 and 278 on
substrate 282 to lock the semiconductor die in position on the
substrate in the y-z directions.
[0055] FIGS. 11a-11c illustrate semiconductor die with cross-shaped
alignment notches formed in the back surface of the die and mounted
to mating cross-shaped protrusions formed over a substrate. FIG.
11a is an orthogonal view of semiconductor die 284 including a
cross-shaped alignment notch 285 formed in back surface 286 between
side surfaces 287 of the semiconductor die using plasma etching,
wet etching, milling, laser, or dry etching. Likewise,
semiconductor die 288 includes a cross-shaped alignment notch 290
formed in back surface 292 between side surfaces 294 of the
semiconductor die using plasma etching, wet etching, milling,
laser, or dry etching. Semiconductor die 284 and 288 can be
rectangular, circular, oval, or other geometric shape.
Semiconductor die 284 and 288 can be an ASIC, sensor, optical
device, detector, VCSEL, waveguide, and multi-chip module.
Semiconductor die 284 and 288 are positioned over substrate 296
with cross-shaped alignment protrusions 298. Substrate 296 can be a
PCB, flexible wiring harness, ceramic board, or glass substrate.
Substrate 296 can also be a leadframe, interposer, or semiconductor
die. Cross-shaped notches 285 and 290 are aligned with cross-shaped
substrate protrusions 298.
[0056] FIG. 11b is a bottom view of semiconductor die 284 with
cross-shaped alignment notch 285 formed in back surface 286 between
side surfaces 287 of the semiconductor die, and semiconductor die
288 with cross-shaped alignment notch 290 formed in back surface
292 between side surfaces 294 of the semiconductor die.
[0057] In FIG. 11c, semiconductor die 284 and 288 are mounted to
substrate 296 with precise alignment as cross-shaped notches 285
and 290 are inserted into cross-shaped substrate protrusions 298.
Cross-shaped alignment notches 285 and 290 and cross-shaped
substrate protrusions 298 provide a keyed recess for easy placement
and precise alignment of semiconductor die 284 and 288 on substrate
296. Cross-shaped notches 285 and 290 inserted into cross-shaped
substrate protrusions 298 lock semiconductor die 284 and 288 in
position on substrate 296 in x-y-z directions.
[0058] FIGS. 12a-12c illustrate semiconductor die with elongated
alignment protrusions formed in the back surface of the die and
mounted to mating recesses formed in a substrate. FIG. 12a is an
orthogonal view of semiconductor die 300 including an elongated
alignment protrusion 302 formed over back surface 304 between side
surfaces 306 of the semiconductor die using plasma etching, wet
etching, milling, laser, or dry etching. Likewise, semiconductor
die 308 includes an elongated alignment protrusion 309 formed over
back surface 310 between side surfaces 311 of the semiconductor die
using plasma etching, wet etching, milling, laser, or dry etching.
Semiconductor die 300 and 308 can be rectangular, circular, oval,
or other geometric shape. Semiconductor die 300 and 308 can be an
ASIC, sensor, optical device, detector, VCSEL, waveguide, and
multi-chip module. Semiconductor die 300 and 308 are positioned
over substrate 312 with alignment notches 313. Substrate 282 can be
a PCB, flexible wiring harness, ceramic board, or glass substrate.
Substrate 312 can also be a leadframe, interposer, or semiconductor
die. Protrusions 302 and 309 are aligned with substrate notches
313.
[0059] FIG. 12b is a bottom view of semiconductor die 300 with
alignment protrusion 302 formed over back surface 304 between side
surfaces 306 of the semiconductor die, and semiconductor die 308
with alignment protrusion 309 formed over back surface 310 between
side surfaces 311 of the semiconductor die.
[0060] In FIG. 12c, semiconductor die 300 and 308 are mounted to
substrate 312 with precise alignment as protrusions 302 and 309
insert into substrate notches 313. Alignment protrusions 302 and
309 formed in back surfaces 304 and 310 of semiconductor die 300
and 308 provide a keyed recess for easy placement and precise
alignment of the semiconductor die on substrate 312 to lock the
semiconductor die in position on the substrate in the y-z
directions.
[0061] FIGS. 13a-13c illustrate semiconductor die with cross-shaped
alignment protrusions formed in the back surface of the die and
mounted to mating cross-shaped recesses formed in a substrate. FIG.
13a is an orthogonal view of semiconductor die 314 including
cross-shaped alignment protrusion 315 formed over back surface 316
between side surfaces 317 of the semiconductor die using plasma
etching, wet etching, milling, laser, or dry etching. Likewise,
semiconductor die 318 includes cross-shaped alignment protrusion
320 formed over back surface 322 between side surfaces 324 of the
semiconductor die using plasma etching, wet etching, milling,
laser, or dry etching. Semiconductor die 314 and 318 can be
rectangular, circular, oval, or other geometric shape.
Semiconductor die 314 and 318 can be an ASIC, sensor, optical
device, detector, VCSEL, waveguide, and multi-chip module.
Semiconductor die 314 and 318 are positioned over substrate 326
with cross-shaped alignment notches 328. Substrate 326 can be a
PCB, flexible wiring harness, ceramic board, or glass substrate.
Substrate 326 can also be a leadframe, interposer, or semiconductor
die. Cross-shaped protrusions 315 and 320 are aligned with
cross-shaped substrate notches 328.
[0062] FIG. 13b is a bottom view of semiconductor die 314 with
cross-shaped alignment protrusion 315 formed over back surface 316
between side surfaces 317 of the semiconductor die, and
semiconductor die 318 with cross-shaped alignment protrusion 320
formed over back surface 322 between side surfaces 324 of the
semiconductor die.
[0063] In FIG. 13c, semiconductor die 314 and 318 are mounted to
substrate 326 with precise alignment as cross-shaped protrusions
315 and 320 insert into cross-shaped substrate notches 328.
Cross-shaped alignment protrusions 315 and 320 and cross-shaped
substrate notches 328 provide a keyed recess for easy placement and
precise alignment of semiconductor die 314 and 318 on substrate
326. Cross-shaped protrusions 315 and 320 inserted into
cross-shaped substrate notches 328 lock semiconductor die 314 and
318 in position on substrate 326 in x-y-z directions.
[0064] FIGS. 14a-14b illustrate semiconductor die with alignment
recesses (or protrusions) formed in the back surface of the die and
mounted to mating structures formed in a PCB. In FIG. 14a,
semiconductor die 330 and 332 are positioned over PCB 340 with
corresponding alignment protrusions (or recesses) 342 and 344
formed by plasma etching, wet etching, milling, laser, or dry
etching. Recesses 346 and 348 in semiconductor die 330 and 332 are
also formed by plasma etching, wet etching, milling, laser, or dry
etching. Recess 346 in semiconductor die 330 is aligned with PCB
protrusion 342, and recess 348 in semiconductor die 332 is aligned
with PCB protrusion 344. In FIG. 14b, semiconductor die 330 and 332
are mounted to PCB 340 with precise alignment as recesses 346 and
348 are inserted into the PCB protrusions 342 and 344,
respectively. Alignment recesses 346 and 348 formed in the back
surfaces of semiconductor die 330 and 332 provide a keyed recess
for easy placement and precise alignment of the semiconductor die
on PCB 340.
[0065] FIGS. 15a-15c illustrate semiconductor die 350a-350b with
alignment protrusions 352 formed in back surface 354 of the die
using plasma etching, wet etching, milling, laser, or dry etching
and inserted into mating openings 358 formed through substrate 360.
FIG. 15a shows semiconductor die 350a-350b positioned over
substrate 360 with alignment protrusions 352 aligned with openings
358. Substrate 360 can be a PCB, flexible wiring harness, ceramic
board, or glass substrate. Substrate 360 can also be a leadframe,
interposer, or semiconductor die. FIG. 15b is a bottom view of
semiconductor die 350a-350b with alignment protrusions 352 formed
over back surface 354.
[0066] In FIG. 15c, semiconductor die 350a-350b are mounted to
substrate 360 with alignment protrusions 352 extending through
openings 358. Alignment protrusions 352 and openings 358 provide a
keyed mating structure for easy placement and precise alignment of
semiconductor die 350a-350b on substrate 360. Fasteners 362 are
attached to protrusions 352 on the back side of substrate 360
opposite semiconductor die 350. Fasteners 362 securely hold
semiconductor die 350a-350b to substrate 360. The alignment
arrangement in FIGS. 15a-15c allows semiconductor die 350a-350b to
positioned on substrate 360 so that side surface 364 of
semiconductor die 350a is in direct physical contact with side
surface 364 of semiconductor die 350b. Fasteners 362 eliminate the
need for die attach adhesive so no material will occupy the space
between semiconductor die 350a-350b. Alternatively, alignment
protrusions 352 extend into openings 358 partially through
substrate 360. An electrical connection is made to alignment
protrusions 352 for fastening in place structurally, thermal,
and/or for electrical connection.
[0067] While one or more embodiments have been illustrated and
described in detail, the skilled artisan will appreciate that
modifications and adaptations to those embodiments may be made
without departing from the scope of the present disclosure.
* * * * *