U.S. patent application number 14/088861 was filed with the patent office on 2015-05-28 for method of making a finfet device.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Hung-Chang Hsieh, Ming-Feng Shieh, Han-Wei Wu.
Application Number | 20150147867 14/088861 |
Document ID | / |
Family ID | 53054602 |
Filed Date | 2015-05-28 |
United States Patent
Application |
20150147867 |
Kind Code |
A1 |
Shieh; Ming-Feng ; et
al. |
May 28, 2015 |
Method Of Making a FinFET Device
Abstract
A method of fabricating a fin-like field-effect transistor
(FinFET) device is disclosed. A plurality of mandrel features are
formed on a substrate. First spacers are formed along sidewalls of
the mandrel feature and second spacers are along sidewalls of the
first spacers. Two back-to-back adjacent second spacers separate by
a gap in a first region and merge together in a second region of
the substrate. A dielectric feature is formed in the gap and a
dielectric mesa is formed in a third region of the substrate. A
first subset of the first spacer is removed in a first cut. Fins
and trenches are formed by etching the substrate using the first
spacer and the dielectric feature as an etch mask.
Inventors: |
Shieh; Ming-Feng; (Tainan
County, TW) ; Hsieh; Hung-Chang; (Hsin-Chu City,
TW) ; Wu; Han-Wei; (Tainan City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsin-Chu |
|
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd.
Hsin-Chu
TW
|
Family ID: |
53054602 |
Appl. No.: |
14/088861 |
Filed: |
November 25, 2013 |
Current U.S.
Class: |
438/424 ;
438/696 |
Current CPC
Class: |
H01L 21/823431 20130101;
H01L 21/3086 20130101; H01L 21/3088 20130101; H01L 21/31055
20130101; H01L 21/823821 20130101; H01L 21/30604 20130101; H01L
21/845 20130101; H01L 29/66545 20130101; H01L 29/66795
20130101 |
Class at
Publication: |
438/424 ;
438/696 |
International
Class: |
H01L 21/308 20060101
H01L021/308; H01L 21/762 20060101 H01L021/762; H01L 21/306 20060101
H01L021/306 |
Claims
1. A method for making an integrated circuit (IC), the method
comprising: providing a substrate having a first region, a second
region and a third region; forming a plurality of mandrel features
in the first region with a first spacing and the second region with
a second spacing; forming first spacers along sidewalls of the
mandrel features with a targeted width A; forming second spacers
with a first width W.sub.1 along sidewalls of the first spacer,
wherein two back-to-back adjacent second spacers are separate by a
gap in the first region, and merge together in the second region;
forming a dielectric feature in the gap; performing a first cut to
remove a first subset of the first spacers; coincident with
removing the first subset of the first spacers, forming a
dielectric mesa with a second width w.sub.2 in the third region,
the second width W.sub.2 is substantially larger than the first
width W.sub.1; removing the mandrel features and the second
spacers; and etching the substrate using the first spacers, the
dielectric feature, and the dielectric mesa as an etch mask.
2. The method of claim 1, wherein the mandrel features are formed
such that: in the first region, the mandrel features have the first
width W.sub.1 and a first spacing S.sub.1 between two adjacent
mandrel features, wherein S.sub.1 is set to be equal to about
(2.times.W.sub.1)+(3.times.A); in the second region, the mandrel
features have the first width W.sub.1 and a second spacing S.sub.2
between two adjacent mandrel features, wherein S.sub.2 is set to be
smaller than (2.times.W.sub.1)+(2.times.A) and larger than
(2.times.A).
3. The method of claim 2, wherein in the first region, the gap is
left between two back-to-back second spacers, wherein the gap has a
width which is about the same as the targeted width A.
4. The method of claim 2, wherein in the second region, the second
spacer material fully fills in the spacing between two back-to-back
first spacers.
5. The method of claim 1, wherein the forming of the dielectric
feature includes: filling in the gap with the dielectric layer; and
recessing the dielectric layer by a chemical mechanical polishing
(CMP) process.
6. The method of claim 5, wherein the dielectric feature is formed
with the same width as the targeted width A.
7. The method of claim 1, wherein the performing the first cut
includes: forming a patterned resist layer over the mandrel feature
and the first and second spacers, wherein the patterned resist
layer has openings to expose the first subset of the first spacers;
removing the first subset of the first spacers; and removing the
patterned resist layer.
8. The method of claim 7, wherein the forming of the dielectric
mesa in the third region, includes: covering a portion of the
dielectric layer in the third region by the patterned resist layer;
and coincident with removing the first subset of the first spacers,
removing uncovered portion of the dielectric layer in the third
region.
9. The method of claim 1, wherein the mandrel feature and the
second spacer are removed together by an etching process, which has
selectivity with respect to the first spacers, the dielectric
feature and the dielectric mesa.
10. The method of claim 1, further comprising: after etching the
substrate, forming a second cut resist layer over the first spacers
and the dielectric feature with openings to expose the second
subset of the first spacers; and performing a second cut to remove
the second subset of the first spacers to form an isolation trench
in the substrate.
11. The method of claim 10, wherein the second cut is in a
direction which is perpendicular to the first cut.
12. A method for fabricating a fin-type field-effect transistor
(FinFET) device, the method comprising: providing a substrate
having a first region, a second region and a third region; forming
a plurality of mandrel features in the first region with a first
spacing and the second region with a second spacing; forming first
spacers along sidewalls of the mandrel features with a targeted
width A; forming second spacers with a first width W.sub.1 along
sidewalls of the first spacer, wherein two back-to-back adjacent
second spacers are separate by a gap in the first region, and merge
together in the second region; forming a dielectric feature in the
gap; performing a first cut to remove a first subset of the first
spacers; coincident with removing the first subset of the first
spacers, forming a dielectric mesa with a second width W.sub.2 in
the third region, wherein the second width W.sub.2 is substantially
larger than the first width W.sub.1; removing the mandrel features
and the second spacers; and etching the substrate using the first
spacers, the dielectric features as an etch mask to form fins;
coincident with etching the substrate to form fins, etching the
substrate using the dielectric mesa as an etch mask to form a
substrate mesa; and performing a second cut to remove a subset of
the fins to form an isolation trench.
13. The method of claim 12, wherein the mandrel features are formed
such that: in the first region, the mandrel features have the first
width W.sub.1 and a first spacing S.sub.1 between two adjacent
mandrel features, wherein S.sub.1 is set to be equal to about
(2.times.W.sub.1)+(3.times.A); in the second region, the mandrel
features have the first width W.sub.1 and a second spacing S.sub.2
between two adjacent mandrel features, wherein S.sub.2 is set to be
smaller than (2.times.W.sub.1)+(2.times.A) and larger than
(2.times.A).
14. The method of claim 12, wherein the fin is formed with a width
same as the targeted width A.
15. The method of claim 12, wherein the mandrel feature and the
second spacer are removed together by an etching process, which
having an adequate selectivity with respect to the first spacer,
the dielectric feature and the dielectric mesa.
16. The method of claim 12, wherein the performing the first cut
includes: forming a patterned resist layer over the mandrel
feature, the first spacers, and the second spacers, wherein the
patterned resist layer has openings to expose the first subset of
the first spacers; removing the first subset of the first spacers;
and removing the patterned resist layer.
17. The method of claim 16, wherein the forming of the dielectric
mesa in the third region, includes: covering a portion of the
dielectric layer in the third region by the patterned resist layer;
and coincident with removing the first subset of the first spacers,
removing uncovered portions of the dielectric layer in the third
region.
18. The method of claim 13, further comprising: after the second
cut, removing the first spacers, the dielectric feature and the
dielectric mesa to reveal the fins in the first and the second
region, wherein the fin in the first region has a different pitch
with the fin in the second region, they are: a first pitch in the
first region, which is equal to the target width A+the first width
W.sub.1; a second pitch in the second region, which is equal to the
second spacing S.sub.2.
19. The method of claim 18, further comprising: coincident with
removing the first spacers and the dielectric feature, removing the
dielectric mesa to reveal a substrate mesa with the second width
W.sub.2.
20. A method for integrated circuit (IC), comprising: providing a
substrate having a first region and a second region; forming
mandrel features in the first region; forming first spacers on
sidewalls of the mandrel feature; forming second spacers on
sidewalls of the first spacer such that two adjacent second spacers
are separated by a gap having a same width as the first spacer;
depositing a dielectric layer over the substrate, including fully
filling in the gap; recessing the dielectric layer to form a
dielectric feature in the gap; forming a pattern resist layer to
expose a subset of the first spacer and a portion of the dielectric
layer in the second region; performing an etch through the pattern
resist layer to remove the subset of the first spacer and form a
dielectric mesa in the third region; removing the mandrel features
and the second spacers; and etching the substrate using the first
spacers, the dielectric feature and the dielectric mesa as an etch
mask.
Description
BACKGROUND
[0001] The semiconductor integrated circuit (IC) industry has
experienced rapid growth. In the course of IC evolution, functional
density (i.e., the number of interconnected devices per chip area)
has generally increased while geometry size (i.e., the smallest
component (or line) that can be created using a fabrication
process) has decreased. This scaling down process generally
provides benefits by increasing production efficiency and lowering
associated costs.
[0002] Such scaling down has also increased the complexity of
processing and manufacturing ICs and, for these advances to be
realized, similar developments in IC processing and manufacturing
are needed. For example, a three dimensional transistor, such as a
fin-type field-effect transistor (FinFET), has been introduced to
replace a planar transistor. Although existing FinFET devices and
methods of fabricating FinFET devices have been generally adequate
for their intended purposes, they have not been entirely
satisfactory in all respects. For example, a more flexible
integration for forming fin and isolation structures is
desired.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The present disclosure is best understood from the following
detailed description when read with the accompanying figures. It is
emphasized that, in accordance with the standard practice in the
industry, various features are not drawn to scale and are used for
illustration purposes only. In fact, the dimensions of the various
features may be arbitrarily increased or reduced for clarity of
discussion.
[0004] FIG. 1 is a flow chart of an example method for fabricating
a semiconductor device according to various aspects of the present
disclosure.
[0005] FIGS. 2-13 are cross-sectional views of an example
semiconductor device at fabrication stages constructed according to
the method of FIG. 1.
DETAILED DESCRIPTION
[0006] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the invention. Specific examples of components and arrangements are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact.
[0007] The present disclosure is directed to, but not otherwise
limited to, a FinFET device. The FinFET device, for example, may be
a complementary metal-oxide-semiconductor (CMOS) device comprising
a P-type metal-oxide-semiconductor (PMOS) FinFET device and an
N-type metal-oxide-semiconductor (NMOS) FinFET device. The
following disclosure will continue with a FinFET example to
illustrate various embodiments of the present invention. It is
understood, however, that the application should not be limited to
a particular type of device, except as specifically claimed.
[0008] FIG. 1 is a flowchart of a method 100 for fabricating a
FinFET device according to aspects of the present disclosure. It is
understood that additional steps can be provided before, during,
and after the method, and some of the steps described can be
replaced or eliminated for other embodiments of the method. The
method 100 is discussed in detail below, with reference to a FinFET
device 200 shown in FIGS. 2 to 13 for the sake of example. The
present disclosure repeats reference numerals and/or letters in the
various embodiments. This repetition is for the purpose of
simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
[0009] Referring to FIGS. 1 and 2, the method 100 begins at step
102 by forming a plurality of mandrel features 220 on a substrate
210. Each mandrel feature 220 is a dummy feature and will be
removed at a later fabrication stage. Individual mandrel features
will be labeled 220A, 220B, etc. for the sake of further reference,
below.
[0010] The substrate 210 includes a semiconductor substrate, such
as a silicon wafer. Alternatively, the substrate 210 includes
germanium, silicon germanium or other proper semiconductor
materials. In one embodiment, the substrate 210 includes an epitaxy
(or epi) semiconductor layer. In another embodiment, the substrate
210 includes a buried dielectric material layer for isolation
formed by a proper technology, such as a technology referred to as
separation by implanted oxygen (SIMOX). In some embodiments, the
substrate 210 may be a semiconductor on insulator, such as silicon
on insulator (SOI).
[0011] The substrate 210 may include various doped regions
depending on design requirements as known in the art. The doped
regions may be doped with p-type dopants, such as boron or BF2;
n-type dopants, such as phosphorus or arsenic; or combinations
thereof. The doped regions may be formed directly on the substrate
210, in a P-well structure, in an N-well structure, in a dual-well
structure, or using a raised structure. The substrate 210 may
further include various active regions, such as regions configured
for an N-type metal-oxide-semiconductor transistor device and
regions configured for a P-type metal-oxide-semiconductor
transistor device.
[0012] In one embodiment, prior to forming the mandrel features
220, a hard mask 215 is formed over the substrate 210 to provide
protection to a fin structure in subsequent processes. The hard
mask 215 may include multiple layers to gain process flexibility.
For example, the hard mask 215 includes a first oxide layer
deposited over the substrate 210, a silicon nitride layer deposited
over the first oxide layer and a second silicon oxide layer
deposited over the silicon nitride layer. One or more of the layers
may be formed by various methods, including thermal oxidation, a
chemical vapor deposition (CVD) process, plasma enhanced CVD
(PECVD), atomic layer deposition (ALD), and/or other methods known
in the art.
[0013] In the present embodiment, the substrate 210 has three
regions: a first region 230, a second region 240 and a third region
250. The mandrel features 220 are then formed over the hard mask
215 in the first and the second regions. In one embodiment, the
mandrel features 220 are formed by depositing a mandrel material
layer, such as a dielectric material (silicon oxide, silicon
nitride for examples); forming a patterned photo resist layer over
the mandrel material layer; and etching the mandrel material layer
using the patterned resist layer as an etch mask, thereby forming
the mandrel features 220. In another embodiment, the mandrel
features 220 are resist patterns.
[0014] The mandrel features 220 are oriented in the Y direction and
spaced away in the X direction perpendicular to the Y direction.
The mandrel features 220 are characterized with a width L and a
first spacing S. The width L and the first spacing S may be a
constant or alternatively be a variable that changes from mandrel
feature to mandrel feature. For the sake of clarity to better
describing the method 100, now labeling the mandrel features 220 in
the first region 230 and second region 240 with the reference
number 220A and 220B, respectively.
[0015] In the present embodiment, the mandrel features 220A and
220B have the same width, a first width W.sub.1, but have different
spacing. In the first region, the mandrel features 220A have a
first spacing S.sub.1 and in the second region, the mandrel
features 220B have a second spacing S.sub.2. With a targeted width
of fin features, the first spacing S.sub.1 is designed be equal to
(2.times.W.sub.1)+(3.times.A), where A is the width of a fin to be
formed, which will be described in detail below. The second spacing
S.sub.2 is designed to be less than or equal to
(2.times.W.sub.1)+(2.times.A), and larger than 2.times.A, which
will also be described in detail below.
[0016] Referring to FIGS. 1 and 3, the method 100 proceeds to step
104 by forming a first spacer 310 on sidewalls of the mandrel
features 220. In one embodiment, the formation of the first spacer
310 includes depositing a first spacer material layer on the
substrate 210 and the mandrel features 220, and thereafter
performing a first anisotropic etch to the first spacer material
layer, thereby forming the first spacer 310. The first spacer
material layer may include a dielectric material (such as silicon
oxide, silicon nitride or silicon carbide) but is different from
the mandrel material layer to achieve etching selectivity during
the first anisotropic etch. The deposition of the first spacer
material layer includes a suitable technique, such as chemical
vapor deposition (CVD). The first anisotropic etch may include a
plasma etch in one example. The first spacer 310 is oriented in the
Y direction and spaced from each other in the X direction.
[0017] In the present embodiment, the first spacer 310 is formed
with the same width as the fin, which is the targeted width A. In
one embodiment, a thickness of the first spacer material along
sidewalls of the mandrel features, 220A and 220B, is controlled to
be the same as the targeted width A.
[0018] Referring to FIGS. 1 and 4, the method 100 proceeds to step
106 by forming a second spacer 320 on sidewalls of the first spacer
310. In one embodiment, the formation of the second spacer 320
includes depositing a second spacer material layer over the
substrate 210 and the first spacer 310, and thereafter performing a
second anisotropic etch to the second spacer material layer,
thereby forming the second spacer 320. The second spacer material
layer may include a dielectric material (such as silicon oxide,
silicon nitride or silicon carbide) but is different from the first
spacer material layer to achieve etching selectivity during the
second anisotropic etch. In one embodiment, the second spacer
material layer includes a same material layer as the mandrel
feature 220. The deposition of the second spacer material layer
includes a suitable technique, such as CVD. The second anisotropic
etch may include a plasma etch in one example. The second spacer
320 is oriented in the Y direction and spaced from each other in
the X direction. In the present embodiment,
[0019] In the present embodiment, the second spacer 320 is formed
to have the same width as the first spacing W.sub.1. Therefore, in
the first region 230, a gap 325 is left between two back-to-back
second spacers 320, and a width of the gap 325 is about the same as
the targeted width A. Also in the second region 240, the two
back-to-back second spacers 320 merge with each other at a merging
space 326.
[0020] Referring to FIGS. 1 and 5, the method 100 proceeds to step
108 by depositing a dielectric layer 410 over the substrate 210,
including fully filling in the gap 325. The dielectric layer 410
may include silicon oxide, silicon nitride, silicon carbide, or
other suitable material. The dielectric layer 410 is deposited by a
suitable technique, such as CVD and ALD. In one embodiment, the
dielectric layer 410 has same dielectric material as the first
spacer material to achieve etching selectivity in a subsequent
etch, which will be described later.
[0021] Referring to FIGS. 1 and 6, the method 100 proceeds to step
110 by etching back the dielectric layer 410 to expose top surfaces
of the mandrel feature 220, the first spacer 310 and the second
spacer 320 in the first and the second regions, 230 and 240. After
etching back, a remaining portion of the dielectric layer 410
filled in the gap 325 forms a dielectric feature 415 and another
remaining portion of the dielectric layer 410 covers the third
region 250 as well. In one embodiment, the dielectric layer 410 is
etched back by a chemical mechanical polishing (CMP) process.
[0022] Referring to FIGS. 1 and 7, the method 100 proceeds to step
112 by forming a first cut pattern 510 having first openings 515,
such that a first subset of the first spacers 310 within the first
openings 515 are uncovered. Also in the third region 250, the first
cut pattern 510 covers a portion of the dielectric layer 410 with a
mesa width W.sub.2. The mesa width W.sub.2 is substantial larger
than the first spacing S.sub.1. In one embodiment, the mesa width
W.sub.2 defines a wide active region. In one embodiment, a subset
of the second spacers 320 may be uncovered in the first openings
515 as well. The first cut pattern 510 is used as an etch mask
during a subsequent etch process to selectively remove the first
subset of the first spacer 310. The first cut pattern 510 may
include a resist layer patterned by a second lithography process.
Alternatively, the cut pattern 510 includes a hard mask material
(dielectric material such as silicon oxide or silicon nitride)
different from the first spacer material layer and the dielectric
layer 410 to achieve etch selectivity and is patterned by a
procedure that includes depositing a dielectric material layer,
forming a resist pattern on the dielectric material layer, and
etching the dielectric material layer using the resist pattern as
an etch mask.
[0023] Referring to FIGS. 1 and 8, the method 100 proceeds to step
114 by performing a first cut to remove the first subset of the
first spacer 310 and etch the dielectric layer 410 in the third
region to form a dielectric mesa 416, through the first cut pattern
510. The first subset of the first spacer 310 (including the
dielectric feature 415) and the dielectric layer 410 are removed by
an etch process that selectively removes the first spacer material
layer and the dielectric layer 410 but substantially does not etch
the first cut pattern 510. In one embodiment, the etch process is
configured to not etch the second spacer material layer as well
during removing the first spacer 310 through the first cut pattern
510. Thereafter, the first cut pattern 510 is removed by a suitable
process. In one example where the first cut pattern 510 is a resist
pattern, the first cut pattern 510 is removed by wet stripping or
plasma ashing. In another example wherein the cut pattern 510 is a
hard mask pattern of a dielectric material, the cut pattern 510 may
be removed by a wet etching process to selectively remove the hard
mask material.
[0024] Referring to FIGS. 1 and 9, the method 100 proceeds to step
116 by removing the mandrel features 220 and the second spacers
320. In one embodiment, the mandrel features 220 and the second
spacers 320 are removed by a selective etch process. The etch
process selectively removes the mandrel features 220 and the second
spacers 320, but substantially does not etch the first spacers 310,
the dielectric features 415 and the dielectric mesa 416. The etch
process may include a dry etching, a wet etching, and/or a
combination thereof.
[0025] Referring to FIGS. 1 and 10, the method 100 proceeds to step
118 by etching the substrate 210 to form fins 610, a substrate mesa
620 and a first trench 630. In one embodiment, by using the first
spacer 310, the dielectric feature 415 and the dielectric mesa 416
as an etch mask, a selective etch is performed to remove a portion
of the substrate 210 to form the fins 610 having the targeted width
A, the substrate mesa 620 having the mesa width W.sub.2 and the
first trench 630. The selective etch process may include a
selective wet etch or a selective dry etch. A wet etching solution
includes a tetramethylammonium hydroxide (TMAH), a
HF/HNO.sub.3/CH.sub.3COOH solution, or other suitable solution. Dry
etching processes include a biased plasma etching process that uses
a chlorine-based chemistry. Other dry etchant gasses include
CF.sub.4, NF.sub.3, SF.sub.6, and He. The etch process may include
multiple etch steps to optimize the etch effect. In another
embodiment, the fins 610 are formed having a width less than the
targeted width A by a trimming the fins 610 further.
[0026] Referring to FIGS. 1 and 11, the method 100 proceeds to step
120 by forming a second cut pattern 710 having second openings 715
such that a second subset of the first spacer 310 (not shown)
within the second openings 715 are uncovered. The second cut
pattern 710 may be formed similarly in many respects to the first
cut pattern 510 discussed above in association with FIG. 7. In one
embodiment, the second cut pattern 710 is along a direction which
is perpendicular to the direction of first cut pattern 510.
[0027] Referring to FIGS. 1 and 12, the method 100 proceeds to step
122 by performing a second cut to remove the second subset of the
first spacers 310 and a portion of the substrate 210 through the
second cut pattern 710, to form a second trench 720. In one
embodiment, the second trench 720 is deeper than the first trench
630. The second cut may be performed by a suitable etch process,
such as a wet etch, a dry etch, or a combination thereof.
Thereafter, the second cut pattern 710 is removed by a suitable
process.
[0028] Referring to FIGS. 1 and 13, the method 100 proceeds to step
124 by removing the first spacer 310, the first dielectric feature
415 and the dielectric mesa 416 to reveal fins, now labeled with
the reference number 810 having the first spacer width a, and a
substrate mesa 815 having the mesa width W.sub.2. The first spacer
310, the first dielectric feature 415, and the second dielectric
feature 416 may be removed by a suitable etch process, such as a
selective wet etch, a selective dry etch, or a combination
thereof.
[0029] In the present embodiment, in the first region 240, a first
pitch P.sub.1 is equal to A+W.sub.1 In the second region 240, a
second pitch P.sub.2 is equal to the second spacing S.sub.2. The
pitch is a dimension from an edge of one fin 810 to the same edge
of an adjacent fin 810. Different pitches may be needed for
different device components, such as an input/output component, a
logic circuit, or a static random-access memory (SRAM).
[0030] Additional steps can be provided before, during, and after
the method 100, and some of the steps described can be replaced or
eliminated for other embodiments of the method.
[0031] The FinFET device 200 undergoes further CMOS or MOS
technology processing to form various features and regions. The
FinFET device 200 may include a high-k (HK)/metal gate (MG) over
the substrate 210, including wrapping over a portion of the fins
810 in a gate region, where the fins 810 may serve as gate channel
region. In a gate first process scheme, the HK/MG is all or part of
a functional gate. Conversely, in a gate last process scheme, a
dummy gate is formed first and is replaced later by the HK/MG after
high thermal temperature processes are performed, such as thermal
processes during sources/drains formation.
[0032] The FinFET device 200 may include isolation features formed
by filling in the first and second trenches 630 and 720 with an
isolation dielectric layer. The isolation dielectric layer may
include silicon oxide, silicon nitride, silicon oxynitride, or
other suitable materials, or combinations thereof. In some
examples, the isolation dielectric layer has a multi-layer
structure.
[0033] The FinFET device 200 may also include a source/drain
feature in a source/drain regions in the substrate 210, including
in another portion of the fins 810. As an example, a portion of the
fins 810 in the source/drain regions is recessed first. Then, a
semiconductor material epitaxially grows in the recessed portion of
the fins 810 to form the source/drain feature. The semiconductor
material includes Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, or other
suitable material.
[0034] The FinFET device 200 may also include an interlayer
dielectric (ILD) layer formed between the HK/MG over the substrate
210. The ILD layer includes silicon oxide, oxynitride or other
suitable materials. The ILD layer includes a single layer or
multiple layers.
[0035] The FinFET device 200 may also includes various
contacts/vias/lines and multilayers interconnect features (e.g.,
metal layers and interlayer dielectrics) over the substrate 210.
For example, a multilayer interconnection includes vertical
interconnects, such as conventional vias or contacts, and
horizontal interconnects, such as metal lines. The various
interconnection features may implement various conductive materials
including copper, tungsten, and/or silicide. In one example, a
damascene and/or dual damascene process is used to form a copper
related multilayer interconnection structure.
[0036] Based on the above, the present disclosure offers a method
for fabricating a FinFET device. The method employs a scheme of
forming mandrel features, first spacers, and second spacers to
achieve forming different pitches. The method also employs forming
a dielectric feature with a same width as a fin to gain additional
fins. The method also employs forming a wide substrate mesa during
performing a first cut. The method provides a integration of
forming fins and pitches with big flexibility.
[0037] The present disclosure provides many different embodiments
of fabricating a semiconductor device that provide one or more
improvements over existing approaches. In one embodiment, a method
for fabricating an integrated circuit includes providing a
substrate with a first region, a second region and a third region,
and a targeted width A. The method also includes forming a
plurality of mandrel features in the first and the second regions.
The mandrel features are formed such that: in the first region, the
mandrel feature has a first width W.sub.1 and a first spacing
S.sub.1 between two adjacent mandrel features. The first spacing
S.sub.1 is set to be equal to (2.times.W.sub.1)+(3.times.A), in the
second region, the mandrel feature has the first width W.sub.1 and
a second spacing S.sub.2 between two adjacent mandrel features,
wherein S.sub.2 is set to be smaller than
(2.times.W.sub.1)+(2.times.A) and larger than (2.times.A). The
method also includes forming a first spacer along sidewalls of the
mandrel feature, forming a second spacer along sidewalls of the
first spacer. Two back-to-back adjacent second spacers separate by
a gap in the first region and merge together in the second region.
The method also includes depositing a dielectric layer over the
substrate, including the mandrel features, the first and the second
spacers, forming a dielectric feature in the gap, performing a
first cut to remove a first subset of the first spacer and at the
same time forming a dielectric mesa in the third region. The method
also includes removing the mandrel features and the second spacers
and etching the substrate using the first spacer, the dielectric
feature and the dielectric mesa as an etch mask.
[0038] In another embodiment, a method for fabricating a FinFET
device includes providing a substrate having first, second and
third regions and a targeted width A for a to-be-made fin. The
method also includes forming a plurality of mandrel features in the
first region and the second regions. The mandrel features are
formed such that: in the first region, the mandrel feature has a
first width W.sub.1 and a first spacing S.sub.1 between two
adjacent mandrel features. The S.sub.1 is set to be equal to
(2.times.W.sub.1)+(3.times.A), in the second region, the mandrel
feature has the first width W.sub.1 and a second spacing S.sub.2
between two adjacent mandrel features. The S.sub.2 is set to be
smaller than (2.times.W.sub.1)+(2.times.A) and larger than
(2.times.A), The method also includes forming first spacers along
sidewalls of the mandrel feature with the targeted width A, forming
second spacers along sidewalls of the first spacers such that: in
the first region, a gap with the targeted width A is left between
two back-to-back second spacers and in the second region, two
back-to-back second spacers are merged together. The method also
includes depositing a dielectric layer over the substrate,
including fully filling in the gap, recessing the dielectric layer
to form a dielectric feature in the gap. The dielectric feature is
formed with a same width as the targeted width A. The method also
includes performing a first cut to remove a first subset of the
first spacers, coincident with removing the first subset of the
first spacers, forming a dielectric mesa in the third region. The
dielectric mesa has a second width W.sub.2, which is substantial
larger than the first width W.sub.1. The method also includes
removing the mandrel features and the second spacers, etching the
substrate using the first spacers, the dielectric features as an
etch mask to form fins, coincident with etching the substrate to
form fins, etching the substrate using the dielectric mesa as an
etch mask to form a substrate mesa and performing a second cut to
remove a subset of the fins to form an isolation trench.
[0039] In yet another embodiment, a method for fabricating an
integrated circuit includes providing a substrate having a first
region and a second region, forming mandrel features in the first
region, forming a first spacer on sidewalls of the mandrel
features, forming a second spacer on sidewalls of the first spacer
such that two adjacent second spacers are separated by a gap which
having same width as the first spacer, depositing a dielectric
layer over the substrate, including fully filling in the gap,
recessing the dielectric layer to form a dielectric feature in the
gap, forming a pattern resist layer to expose a subset of the first
spacer and a portion of the dielectric layer in the second region,
performing an etch through the pattern resist layer to remove the
subset of the first spacer and form a dielectric mesa in the third
region, removing the mandrel features and the second spacers and
etching the substrate using the first spacer, the dielectric
feature and the dielectric mesa as an etch mask.
[0040] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *