U.S. patent application number 14/027571 was filed with the patent office on 2015-03-19 for microelectronic element with bond elements to encapsulation surface.
This patent application is currently assigned to INVENSAS CORPORATION. The applicant listed for this patent is Invensas Corporation. Invention is credited to Richard Dewitt Crisp, Belgacem Haba, Wael Zohni.
Application Number | 20150076714 14/027571 |
Document ID | / |
Family ID | 51627374 |
Filed Date | 2015-03-19 |
United States Patent
Application |
20150076714 |
Kind Code |
A1 |
Haba; Belgacem ; et
al. |
March 19, 2015 |
MICROELECTRONIC ELEMENT WITH BOND ELEMENTS TO ENCAPSULATION
SURFACE
Abstract
A microelectronic structure includes a semiconductor having
conductive elements at a first surface. Wire bonds have bases
joined to the conductive elements and free ends remote from the
bases, the free ends being remote from the substrate and the bases
and including end surfaces. The wire bonds define edge surfaces
between the bases and end surfaces thereof. A compliant material
layer extends along the edge surfaces within first portions of the
wire bonds at least adjacent the bases thereof and fills spaces
between the first portions of the wire bonds such that the first
portions of the wire bonds are separated from one another by the
compliant material layer. Second portions of the wire bonds are
defined by the end surfaces and portions of the edge surfaces
adjacent the end surfaces that are extend from a third surface of
the compliant later.
Inventors: |
Haba; Belgacem; (Saratoga,
CA) ; Crisp; Richard Dewitt; (Hornitos, CA) ;
Zohni; Wael; (San Jose, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Invensas Corporation |
San Jose |
CA |
US |
|
|
Assignee: |
INVENSAS CORPORATION
San Jose
CA
|
Family ID: |
51627374 |
Appl. No.: |
14/027571 |
Filed: |
September 16, 2013 |
Current U.S.
Class: |
257/784 ;
438/669 |
Current CPC
Class: |
H01L 2224/05572
20130101; H01L 2224/73203 20130101; H01L 21/4846 20130101; H01L
2224/05573 20130101; H01L 2224/92142 20130101; H01L 2224/97
20130101; H01L 2224/13624 20130101; H01L 2224/16145 20130101; H01L
2224/92143 20130101; H01L 24/745 20130101; H01L 2224/742 20130101;
H01L 2924/12042 20130101; H01L 24/16 20130101; H01L 2224/1369
20130101; H01L 2224/05555 20130101; H01L 2224/32145 20130101; H01L
2224/92142 20130101; H01L 2225/06582 20130101; H01L 24/11 20130101;
H01L 2224/13124 20130101; H01L 2224/13144 20130101; H01L 2224/13147
20130101; H01L 2224/9202 20130101; H01L 2224/13005 20130101; H01L
2224/131 20130101; H01L 2224/16108 20130101; H01L 2224/17051
20130101; H01L 2224/73203 20130101; H01L 2224/1184 20130101; H01L
2224/13012 20130101; H01L 2224/13013 20130101; H01L 2924/181
20130101; H01L 2224/05644 20130101; H01L 2224/1134 20130101; H01L
2224/13005 20130101; H01L 2225/06513 20130101; H01L 2224/0401
20130101; H01L 24/13 20130101; H01L 2224/05644 20130101; H01L
2224/13655 20130101; H01L 2224/16105 20130101; H01L 2224/73103
20130101; H01L 2225/06506 20130101; H01L 2924/12042 20130101; H01L
23/3128 20130101; H01L 2224/05647 20130101; H01L 2224/13014
20130101; H01L 2225/06589 20130101; H01L 2224/05555 20130101; H01L
2224/73103 20130101; H01L 2224/81191 20130101; H01L 2225/06555
20130101; H01L 2224/1357 20130101; H01L 2224/9202 20130101; H01L
21/565 20130101; H01L 2224/05571 20130101; H01L 2224/05655
20130101; H01L 2225/06568 20130101; H01L 23/49 20130101; H01L
24/742 20130101; H01L 2224/13124 20130101; H01L 2224/16227
20130101; H01L 2224/13017 20130101; H01L 2224/13155 20130101; H01L
2224/81193 20130101; H01L 2224/13076 20130101; H01L 2224/13014
20130101; H01L 2224/131 20130101; H01L 24/81 20130101; H01L
2224/05572 20130101; H01L 2224/13147 20130101; H01L 2224/73253
20130101; H01L 23/293 20130101; H01L 2224/73267 20130101; H01L
25/50 20130101; H01L 2224/05571 20130101; H01L 2224/1134 20130101;
H01L 2224/13013 20130101; H01L 2224/13624 20130101; H01L 2224/1369
20130101; H01L 2224/14051 20130101; H01L 2224/81815 20130101; H01L
2224/13012 20130101; H01L 2224/13022 20130101; H01L 2224/13155
20130101; H01L 2224/05647 20130101; H01L 2224/13655 20130101; H01L
2224/05655 20130101; H01L 25/0657 20130101; H01L 2924/181 20130101;
H01L 2225/06517 20130101; H01L 23/3171 20130101; H01L 2224/1191
20130101; H01L 2224/1703 20130101; H01L 2224/13005 20130101; H01L
2224/13144 20130101; H01L 2224/16225 20130101; H01L 2224/81815
20130101; H01L 2924/00012 20130101; H01L 2224/97 20130101; H01L
2924/00 20130101; H01L 2924/00012 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2224/11 20130101; H01L
2924/00012 20130101; H01L 2924/00014 20130101; H01L 2924/00014
20130101; H01L 2924/207 20130101; H01L 2224/11 20130101; H01L
2924/00012 20130101; H01L 2924/00014 20130101; H01L 2924/00012
20130101; H01L 2224/81 20130101; H01L 2224/11 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 2924/014
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2224/83 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2924/00012 20130101; H01L 2924/00014
20130101; H01L 2924/00012 20130101 |
Class at
Publication: |
257/784 ;
438/669 |
International
Class: |
H01L 23/49 20060101
H01L023/49; H01L 21/48 20060101 H01L021/48 |
Claims
1. A microelectronic structure, comprising: a semiconductor die
having first and second oppositely facing surfaces and a plurality
of electrically conductive elements at the first surface; wire
bonds having bases joined to respective ones of the conductive
elements, the wire bonds further having free ends remote from the
bases, the free ends being remote from the substrate and the bases
and including end surfaces thereon, the wire bonds defining edge
surfaces extending between the bases and end surfaces thereof; and
a compliant material layer overlying and extending from the first
surface of the semiconductor die outside of the bases of the wire
bonds, the compliant material layer further extending along first
portions of the edge surfaces of the wire bonds at least adjacent
the bases thereof and filling spaces between the first portions of
the wire bonds such that the first portions of the wire bonds are
separated from one another by the compliant material layer, the
compliant material layer further having a third surface facing away
from the first surface of the semiconductor die, wherein second
portions of the wire bonds extend away from the third surface, the
second portions including the free ends of the wire bonds.
2. The microelectronic structure of claim 1, wherein the first
portions of the wire bonds are encapsulated entirely by the
compliant material, and wherein the second portions of the wire
bonds are moveable with respect to the bases thereof.
3. The microelectronic structure of claim 1, wherein the compliant
material layer has a Young's modulus of 2.5 GPa or less.
4. The microelectronic structure of claim 1, wherein the second
portions of the wire bonds extend along axes of the wire bonds that
are disposed at angles of at least 30 degrees with respect to the
third surface.
5. The microelectronic structure of claim 1, wherein the end
surfaces of the wire bonds are positioned above the third surface
by a distance of at least 50 microns.
6. The microelectronic structure of claim 1, wherein the
semiconductor die further defines edge surfaces extending between
the first and second surfaces, and wherein the compliant material
layer further includes edge surfaces extending from the third
surface thereof to the first surface of the semiconductor die so as
to be substantially coplanar with the edge surfaces of the
semiconductor die.
7. The microelectronic structure of claim 1, wherein at least one
of the wire bonds has a shape such that the wire bond defines an
axis between the free end and the base thereof and such that the
wire bond defines a plane, a bent portion of the at least one wire
bond extending away from the axis within the plane.
8. The microelectronic structure of claim 7, wherein the shape of
the at least one wire bond is further such that a substantially
straight portion of the wire bond extends between the free end and
the bent portion along the axis.
9. The microelectronic structure of claim 1, further including
conductive metal masses joined with the second portions of the wire
bonds and contacting the third surface of the compliant material
layer.
10. The microelectronic structure of claim 9, wherein at least one
of the conductive metal masses encapsulates at least some of the
second portion of a respective one of the wire bonds.
11. The microelectronic structure of claim 9, wherein the
conductive metal masses are configured to join the second portions
of the wire bonds with external conductive features by reflow
thereof.
12. The microelectronic structure of claim 1, wherein: the
semiconductor die is a first semiconductor die having a first
region and a second region surrounding the first region; the
electrically conductive elements of the first semiconductor die are
within the second region; the microelectronic structure further
includes a second semiconductor die mounted on the first
semiconductor die within the first region, the second semiconductor
die being electrically connected with at least some of the
conductive elements of the first semiconductor die; and the
compliant material layer covers the second semiconductor die.
13. The microelectronic structure of claim 1, wherein: the
semiconductor die is a first semiconductor die having a first
region and a second region surrounding the first region; the
electrically conductive elements of the first semiconductor die are
within the second region; the microelectronic structure further
includes a second semiconductor die mounted on the first
semiconductor die within the first region, the second semiconductor
die having first and second oppositely facing surfaces and a
plurality of electrically conductive elements at the first surface
facing away from the first surface of the first semiconductor die,
and wherein additional wire bonds have bases joined to respective
ones of the conductive elements of the second semiconductor die,
the additional wire bonds further having free ends remote from the
bases, the free ends being remote from the first surface of the
second semiconductor die and the bases and including the end
surfaces thereon, the wire bonds defining edge surfaces extending
between the bases and end surfaces thereof; and the compliant
material layer further overlies and extends from the first surface
of the second semiconductor die outside of the bases of the
additional wire bonds, the compliant material layer further
extending along first portions of the edge surfaces of the
additional wire bonds, wherein second portions of the additional
wire bonds are defined by the end surfaces and portions of the edge
surfaces extending from the end surfaces that are uncovered by and
extend away from the compliant material layer at the third
surface.
14. A microelectronic package, comprising: a microelectronic
element, including a first semiconductor die having first and
second oppositely facing surfaces and a plurality of electrically
conductive elements at the first surface; wire bonds having bases
joined to respective ones of the conductive elements at the first
surface and end surfaces, the end surfaces being remote from the
substrate and the bases, each of the wire bonds extending from the
base to the end surface thereof; and a compliant material layer
overlying and extending from the first portion of the first surface
of the substrate and filling spaces between first portions of the
wire bonds such that the first portions of the wire bonds are
separated from one another by the compliant material layer, the
compliant material layer having a third surface facing away from
the first surface of the substrate, wherein second portions of the
wire bonds extend away from the third surface, the second portions
including the free ends of the wire bonds; and a substrate having a
fourth surface and a plurality of terminals exposed at the fourth
surface; wherein the microelectronic element is mounted on the
substrate with the third surface facing the fourth surface and at
least some of the wire bonds are joined, at the second portions
thereof, to respective ones of the terminals.
15. The microelectronic package of claim 14, wherein the second
portions of the wire bonds are electrically and mechanically joined
to the terminals by conductive metal masses.
16. The microelectronic package of claim 14, further including a
molded dielectric layer formed over at least a portion of the
fourth surface of the substrate and extending away therefrom so as
to extend along at least a portion of the microelectronic
element.
17. The microelectronic package of claim 16, wherein the Young's
modulus of the molded dielectric layer is greater than the Young's
Modulus of the compliant material layer.
18. The microelectronic package of claim 14, wherein the compliant
material layer has a Young's modulus of less than 2.5 GPa.
19. The microelectronic package of claim 14, wherein the wire bonds
further define edge surfaces extending between the bases and end
surfaces thereof, and wherein the compliant material layer extends
along portions of the edge surfaces of the wire bonds at least
adjacent the bases thereof and within the first portions of the
wire bonds.
20. The microelectronic package of claim 19, wherein portions of
the edge surfaces of the wire bonds that extend from the end
surfaces thereof are uncovered by the compliant material layer
around entire circumferences thereof at the third surface
thereof.
21. A method for making a microelectronic structure, comprising:
forming wire bonds on a semiconductor die, the semiconductor die
having first and second oppositely facing surfaces and a plurality
of electrically conductive elements at the first surface, the wire
bonds being formed having bases joined to respective ones of the
conductive elements and having end surfaces remote from the
substrate and the bases, edge surfaces of the wire bonds extending
between the bases and the end surfaces; and forming a compliant
material layer overlying and extending from the first surface of
the semiconductor die outside of the bases of the wire bonds, the
compliant material further being formed to extend along portions of
the edge surfaces of first portions of the wire bonds to fill
spaces between the first portions of the wire bonds and to separate
the first portions of the wire bonds from one another, wherein the
compliant material layer is further formed to have a third surface
facing away from the first surface of the substrate with second
portions of the wire bonds extending away from the third surface,
the second portions including the free ends of the wire bonds.
Description
BACKGROUND OF THE INVENTION
[0001] The subject matter of the present application relates to a
microelectronic element including a semiconductor chip with
structures to achieve improved reliability when assembled with
external microelectronic components, including compliant connection
structures, and methods of fabricating the microelectronic
element.
[0002] Semiconductor chips are flat bodies with contacts disposed
on a front surface that are connected to internal electrical
circuitry of the chip. The chips are typically packaged to form a
microelectronic package having terminals that are electrically
connected to the chip contacts. The terminals of the package may
then be connected to an external microelectronic component, such as
a circuit panel.
[0003] Microelectronic devices such as semiconductor chips
typically require many input and output connections to other
electronic components. The input and output contacts of a
semiconductor chip or other comparable device are generally
disposed in grid-like patterns that substantially cover a surface
of the device (commonly referred to as an "area array") or in
elongated rows which may extend parallel to and adjacent each edge
of the device's front surface, or in the center of the front
surface. Typically, devices such as chips must be physically
mounted on a substrate such as a printed circuit board, and the
contacts of the device must be electrically connected to
electrically conductive features of the circuit board.
[0004] Semiconductor chips are commonly provided in packages that
facilitate handling of the chip during manufacture and during
mounting of the chip on an external substrate such as a circuit
board or other circuit panel. For example, many semiconductor chips
are provided in packages suitable for surface mounting. Numerous
packages of this general type have been proposed for various
applications. Most commonly, such packages include a dielectric
element, commonly referred to as a "chip carrier" with terminals
formed as plated or etched metallic structures on the dielectric.
These terminals typically are connected to the contacts of the chip
itself by features such as thin traces extending along the chip
carrier itself and by fine leads or wires extending between the
contacts of the chip and the terminals or traces. In a surface
mounting operation, the package is placed onto a circuit board so
that each terminal on the package is aligned with a corresponding
contact pad on the circuit board. Solder or other bonding material
is provided between the terminals and the contact pads. The package
can be permanently bonded in place by heating the assembly so as to
melt or "reflow" the solder or otherwise activate the bonding
material.
[0005] Many packages include solder masses in the form of solder
balls, typically about 0.1 mm and about 0.8 mm (5 and mils) in
diameter, attached to the terminals of the package. A package
having an array of solder balls projecting from its bottom surface
is commonly referred to as a ball grid array or "BGA" package.
Other packages, referred to as land grid array or "LGA" packages
are secured to the substrate by thin layers or lands formed from
solder. Packages of this type can be quite compact. Certain
packages, commonly referred to as "chip scale packages," occupy an
area of the circuit board equal to, or only slightly larger than,
the area of the device incorporated in the package. This is
advantageous in that it reduces the overall size of the assembly
and permits the use of short interconnections between various
devices on the substrate, which in turn limits signal propagation
time between devices and thus facilitates operation of the assembly
at high speeds.
[0006] Mismatches or differences between coefficients of thermal
expansion ("CTE") of the components in such a package can adversely
impact their reliability and performance. In an example, a
semiconductor chip may have a lower CTE than that of a substrate or
printed circuit board to which it is mounted. As the chip undergoes
heating and cooling due to the use cycle thereof, the components
will expand and contract according to their differing CTEs. In this
example, the substrate will expand more and at a greater rate than
the semiconductor die. This can cause stress in the solder masses
(or other structures) used to both mount and electrically connect
the semiconductor die and the substrate. Such stress can cause the
solder mass to disconnect from either or both of the semiconductor
die or the substrate, thereby interrupting the signal transmission
that it otherwise facilitates. Various structures have been used to
compensate for such variations in CTE, yet many fail to offer a
significant amount of compensation on a scale appropriate for the
fine pitch arrays being increasingly utilized in microelectronic
packages.
BRIEF SUMMARY OF THE INVENTION
[0007] An aspect of the present disclosure relates to a
microelectronic structure including a first semiconductor die
having first and second oppositely facing surfaces and a plurality
of electrically conductive elements at the first surface. The
structure also includes wire bonds having bases joined to
respective ones of the conductive elements. The wire bonds further
have free ends remote from the bases, the free ends being remote
from the substrate and the bases and including end surfaces
thereon. The wire bonds define edge surfaces extending between the
bases and end surfaces thereof. A compliant material layer overlies
and extends from the first surface of the semiconductor die outside
of the bases of the wire bonds. The compliant material layer
further extends along first portions of the edge surfaces of the
wire bonds at least adjacent the bases thereof and fills spaces
between the first portions of the wire bonds such that the first
portions of the wire bonds are separated from one another by the
compliant material layer. The compliant material layer further has
a third surface facing away from the first surface of the
semiconductor die. Second portions of the wire bonds are defined by
the end surfaces and portions of the edge surfaces adjacent the end
surfaces that are uncovered by the third surface and extend away
therefrom.
[0008] The first portions of the wire bonds can be encapsulated
entirely by the compliant material. Further, the second portions of
the wire bonds can be moveable with respect to the bases thereof.
In an example, the compliant material layer can have a Young's
modulus of 2.5 GPa or less.
[0009] The second portions of the wire bonds can extend along axes
of the wire bonds that are disposed at angles of at least 30
degrees with respect to the third surface. The end surfaces of the
wire bonds can be positioned above the third surface by a distance
of at least 50 microns. Further, the end surfaces of the wire bonds
can be positioned above the third surface at a distance of less
than 200 microns.
[0010] The semiconductor die can further define edge surfaces
extending between the first and second surfaces, and the compliant
material layer can further include edge surfaces extending from the
third surface thereof to the first surface of the semiconductor die
so as to be substantially coplanar with the edge surfaces of the
semiconductor die. At least one of the wire bonds can have a shape
such that the wire bond defines an axis between the free end and
the base thereof and such that the wire bond defines a plane. In
such an example a bent portion of the at least one wire bond can
extending away from the axis within the plane. The shape of the at
least one wire bond can be further such that a substantially
straight portion of the wire bond extends between the free end and
the bent portion along the axis.
[0011] The microelectronic structure can further include conductive
metal masses joined with the second portions of the wire bonds and
contacting the third surface of the compliant material layer. In
such an example, at least one of the conductive metal masses
encapsulates at least some of the second portion of a respective
one of the wire bonds. The conductive metal masses can be
configured to join the second portions of the wire bonds with
external conductive features by reflow thereof.
[0012] In an example, the semiconductor die can be a first
semiconductor die having a first region and a second region
surrounding the first region. The electrically conductive elements
of the first semiconductor die can be within the second region. The
microelectronic structure in such an example, can further include a
second semiconductor die mounted on the first semiconductor die
within the first region. The second semiconductor die can be
electrically connected with at least some of the conductive
elements of the first semiconductor die. The compliant material
layer can cover the second semiconductor die.
[0013] In another example, the semiconductor die can be a first
semiconductor die having a first region and a second region
surrounding the first region. The electrically conductive elements
of the first semiconductor die can be within the second region. The
microelectronic structure can further include a second
semiconductor die mounted on the first semiconductor die within the
first region. The second semiconductor die can have first and
second oppositely facing surfaces and a plurality of electrically
conductive elements at the first surface facing away from the first
surface of the first semiconductor die. Additional wire bonds can
have bases joined to respective ones of the conductive elements of
the second semiconductor die. The additional wire bonds can further
have free ends remote from the bases, and the free ends can be
remote from the first surface of the second semiconductor die and
the bases and including the end surfaces thereon. The wire bonds
can define edge surfaces extending between the bases and end
surfaces thereof. The compliant material layer can further overlie
and extend from the first surface of the second semiconductor die
outside of the bases of the additional wire bonds, and the
compliant material layer can further extending along first portions
of the edge surfaces of the additional wire bonds. Second portions
of the additional wire bonds can be defined by the end surfaces and
portions of the edge surfaces extending from the end surfaces that
are uncovered by and extend away from the compliant material layer
at the third surface.
[0014] Another aspect of the present disclosure can relate to a
microelectronic package including a microelectronic element having
a first semiconductor die with first and second oppositely facing
surfaces and a plurality of electrically conductive elements at the
first surface. The element can further have wire bonds with bases
joined to respective ones of the conductive elements at the first
surface and end surfaces, the end surfaces being remote from the
substrate and the bases. Each of the wire bonds extends from the
base to the end surface thereof. A compliant material layer
overlies and extends from the first portion of the first surface of
the substrate and fills spaces between first portions of the wire
bonds such that the first portions of the wire bonds are separated
from one another by the compliant material layer. The compliant
material layer has a third surface facing away from the first
surface of the substrate, and second portions of the wire bonds are
defined by at least portions of the end surfaces of the wire bonds
that are uncovered by the compliant material layer at the third
surface. The package further includes a substrate having a fourth
surface and a plurality of terminals exposed at the fourth surface.
The microelectronic element is mounted on the substrate with the
third surface facing the fourth surface and at least some of the
wire bonds are joined, at the second portions thereof, to
respective ones of the terminals.
[0015] The second portions of the wire bonds can be electrically
and mechanically joined to the terminals by conductive metal
masses. The microelectronic package can further include a molded
dielectric layer formed over at least a portion of the fourth
surface of the substrate and extending away therefrom so as to
extend along at least a portion of the microelectronic element. The
Young's modulus of the molded dielectric layer can be greater than
the Young's Modulus of the compliant material layer. The compliant
material layer can have a Young's modulus of less than 2.5 GPa.
[0016] The wire bonds can further define edge surfaces extending
between the bases and end surfaces thereof, and the compliant
material layer can extend along portions of the edge surfaces of
the wire bonds at least adjacent the bases thereof and within the
first portions of the wire bonds. Portions of the edge surfaces of
the wire bonds that extend from the end surfaces thereof can be
uncovered by the compliant material layer around entire
circumferences thereof at the third surface thereof.
[0017] Another aspect of the present disclosure relates to a method
for making a microelectronic structure. The method includes forming
wire bonds on a semiconductor die, the semiconductor die having
first and second oppositely facing surfaces and a plurality of
electrically conductive elements at the first surface. The wire
bonds are formed having bases joined to respective ones of the
conductive elements and having end surfaces remote from the
substrate and the bases. Edge surfaces of the wire bonds extend
between the bases and the end surfaces. The method further includes
forming a compliant material layer overlying and extending from the
first surface of the semiconductor die outside of the bases of the
wire bonds. The compliant material is further formed to extend
along portions of the edge surfaces of first portions of the wire
bonds to fill spaces between the first portions of the wire bonds
and to separate the first portions of the wire bonds from one
another. The compliant material layer is further formed to have a
third surface facing away from the first surface of the substrate
with second portions of the wire bonds being defined by at least
the end surfaces and portions of the edge surfaces of the wire
bonds that are uncovered by the conductive material layer at the
third surface so as to extend away therefrom.
[0018] The method can further include the step of mounting the
microelectronic package on a substrate with the third surface
facing a surface of the substrate. The surface of the substrate can
have terminals at the surface thereof, and the mounting can include
joining at least some of the second portions of the wire bonds with
the terminals. The second portions of the wire bonds can be joined
with the terminals including reflowing of conductive metal masses
joined with the second portions of the wire bonds. At least one of
the conductive metal masses can encapsulate at least some of the
second portion of a respective one of the wire bonds at least after
the reflowing thereof. In an alternative example, the second
portions of the wire bonds can be joined with the terminals
including reflowing of conductive metal masses joined with the
terminals.
[0019] The method can further include forming a molded dielectric
over at least a portion of the surface of the substrate and
extending away therefrom so as to extend along at least a portion
of the compliant material layer and along at least a portion of the
semiconductor die.
[0020] The compliant material layer can be deposited over the
semiconductor die so as to cover the wire bonds, including the end
surfaces thereof, and forming the compliant material layer can
further include removing a portion thereof to form the third
surface thereof and to uncover the second portions of the wire
bonds. Alternatively, forming the compliant material layer can
include molding the compliant material over the semiconductor die
so as to form the third surface thereof such that the second
portions of the wire bonds extend therefrom.
[0021] Forming the wire bond can include severing a wire segment
joined with one of the conductive elements at least by pressing the
wire segment into contact with a secondary surface using a
capillary of a bonding tool so as to form the end surface of the
wire bond remote from the base.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIG. 1 is a sectional view depicting a microelectronic
element according to an aspect of the disclosure.
[0023] FIG. 2 is a sectional view of a microelectronic package
including the microelectronic element of FIG. 1.
[0024] FIGS. 3A-3C are schematic views of example wire bonds that
can be used in the microelectronic element of FIG. 1.
[0025] FIG. 4 is a detail view of a tip of the example wire bonds
of FIGS. 3A-3C.
[0026] FIG. 5 is a sectional view of an alternative microelectronic
element according to another example of the disclosure.
[0027] FIG. 6 is a sectional view of an alternative microelectronic
element according to another example of the disclosure.
[0028] FIGS. 7-12 show various sectional views of an in process
unit during steps of a method for fabricating a microelectronic
element according to another aspect of the disclosure.
[0029] FIG. 13 shows a method step that can be used in a variation
of the method depicted in FIGS. 7-12
[0030] FIGS. 14 and 15 show schematic views of successive steps in
a method for fabricating a wire bond that can be incorporated in
the method depicted in FIGS. 7-12 and the variation incorporating
the step of FIG. 13.
DETAILED DESCRIPTION
[0031] Turning now to the figures, where similar numeric references
are used to indicate similar features, there is shown in FIG. 1 a
microelectronic structure 10 that can be in the form of a
microelectronic element according to an embodiment of the present
invention. The embodiment of FIG. 1 is a microelectronic element in
the form of a semiconductor die 12 (also referred to as a
semiconductor chip) having a plurality of wire bonds 32 extending
from contacts 28 thereof to extending portions 40 thereof that
extend above a compliant material layer 42 that covers and
separates remaining portions of the wire bonds 32 from each other,
including portions thereof adjacent semiconductor die 12. The
structure 10 can then used in computer or other electronic
applications either alone or in an assembly with further
components.
[0032] The microelectronic element 10 of FIG. 1 includes
semiconductor die 12 having a first surface 14 and a second surface
16. For purposes of this discussion, the first surface 14 may be
described as being positioned opposite or remote from second
surface 16. Such a description, as well as any other description of
the relative position of elements used herein that refers to a
vertical or horizontal position of such elements is made for
illustrative purposes only to correspond with the position of the
elements within the Figures, and is not limiting.
[0033] Conductive elements 28 are at the first surface 14 of
semiconductor die 12. As used in the present description, when an
electrically conductive element is described as being "at" the
surface of another element having dielectric structure, it
indicates that the electrically conductive structure is available
for contact with a theoretical point moving in a direction
perpendicular to the surface of the dielectric structure toward the
surface of the dielectric structure from outside the dielectric
structure. Thus, a terminal or other conductive structure that is
at a surface of a dielectric structure may project from such
surface; may be flush with such surface; or may be recessed
relative to such surface and exposed through a hole or depression
in the dielectric. Conductive elements 28 can be flat, thin
elements of a solid metal material such as copper, gold, nickel, or
other materials that are acceptable for such an application,
including various alloys including one or more of copper, gold,
nickel or combinations thereof. In one example, conductive elements
28 can be substantially circular.
[0034] Microelectronic element 10 further includes a plurality of
wire bonds 32 joined to at least some of the conductive elements
28. Wire bonds 32 are joined at a base 34 thereof to the conductive
elements 28 and extend to a corresponding free end 36 remote from
the base 34 and from the first surface 14 of semiconductor die 12,
the free ends 36 being within the extending portions 40 of the wire
bonds 32. The ends 36 of wire bonds 32 are characterized as being
free in that they are not connected or otherwise joined to
semiconductor die 12 or any other conductive features within
microelectronic element 10 that are, in turn, connected to
semiconductor die 12. In other words, free ends 36 are available
for electronic connection, either directly or indirectly as through
a solder ball or other features discussed herein, to a conductive
feature of a component external to microelectronic element 10, such
as, for example, a printed circuit board ("PCB") or another
substrate with conductive contacts or terminals thereat. The fact
that ends 36 held in a predetermined neutral position by, for
example, compliant material layer 42 (as described further below)
or otherwise joined or electrically connected to another external
component does not mean that they are not "free". Conversely, base
34 is not free as it is either directly or indirectly electrically
connected to semiconductor die 12, as described herein. As shown in
FIG. 1, base 34 can be substantially rounded in shape, extending
outward from an edge surface 37 (as shown, for example, in FIGS.
3A-C) of wire bond 32 defined between base 34 and end 36.
[0035] The particular size and shape of base 34 can vary according
to the type of material used to form wire bond 32, the desired
strength of the connection between wire bond 32 and conductive
element 28, or the particular process used to form wire bond 32.
Example methods for making wire bonds 32 are and are described in
U.S. Pat. No. 7,391,121 to Otremba and in U.S. Pat. App. Pub. Nos.
2012/0280386 ("the '386 Publication") and 2005/0095835 ("the '835
Publication," which describes a wedge-bonding procedure that can be
considered a form of wire bonding) the disclosures of which are
incorporated herein by reference in their entireties.
[0036] Wire bonds 32 can be made from a conductive material such as
copper, gold, nickel, solder, aluminum or the like. Additionally,
wire bonds 32 can be made from combinations of materials, such as
from a core of a conductive material, such as copper or aluminum,
for example, with a coating applied over the core. The coating can
be of a second conductive material, such as aluminum, nickel or the
like. Alternatively, the coating can be of an insulating material,
such as an insulating jacket. In an example, the wire used to form
wire bonds 32 can have a thickness, i.e., in a dimension transverse
to the wire's length, of between about 15 .mu.m and 150 .mu.m. In
other examples, including those in which wedge bonding is used,
wire bonds 32 can have a thickness of up to about 500 .mu.m. In
general, a wire bond is formed on a conductive element, such as
conductive element 28 within contact portion 30 using specialized
equipment.
[0037] As described further below, during formation of a wire bond
of the type shown and described herein, a leading end of a wire
segment is heated and pressed against the receiving surface to
which the wire segment bonds, typically forming a ball or ball-like
base 34 joined to the surface of the conductive element 28. The
desired length of the wire segment to form the wire bond is drawn
out of the bonding tool, which can then cut the wire bond at the
desired length. Wedge bonding, which can be used to form wire bonds
of aluminum, for example, is a process in which the heated portion
of the wire is dragged across the receiving surface to form a wedge
that lies generally parallel to the surface. The wedge-bonded wire
bond can then be bent upward, if necessary, and extended to the
desired length or position before cutting. In a particular
embodiment, the wire used to form a wire bond can be cylindrical in
cross-section. Otherwise, the wire fed from the tool to form a wire
bond or wedge-bonded wire bond may have a polygonal cross-section
such as rectangular or trapezoidal, for example.
[0038] The extending portions 40 of the wire bonds 32 can form at
least a part of a connection feature in an array formed by
respective extending portions 40 of a plurality of wire bonds 32.
Such an array can be formed in an area array configuration,
variations of which could be implemented using the structures
described herein. Such an array can be used to electrically and
mechanically connect the microelectronic element 10 to another
microelectronic structure, such as to a printed circuit board
("PCB"), a substrate (in a packaged configuration for
microelectronic element 10, an example of which is shown in FIG.
2), or to other external components or structures. Solder masses 66
(FIG. 2) can be used to connect the wire bonds 32 to conductive
features of such components or structures such as by electronically
and mechanically attaching extending portions 40 thereof, including
free ends 36 and corresponding end surfaces 38 (FIGS. 3A-3C),
thereto.
[0039] Microelectronic element 10 further includes a compliant
material layer 42 formed from a dielectric material having a
Young's modulus of less than about 2.5 GPa. As shown in FIG. 1,
compliant material layer 42 extends over the portions of first
surface 14 of semiconductor die 12 that are not otherwise covered
by or occupied by bases 34 of wire bonds 32. Similarly, compliant
material layer 42 extends over the portions of conductive elements
28 that are not otherwise covered by bases 34 of wire bonds 32.
Compliant material layer 42 can also partially cover wire bonds 32,
including the bases 34 and at least a portion of edge surfaces 37
thereof. Extending portion 40 of wire bonds 32 remains uncovered by
compliant material layer 42, thereby making the wire bonds 32
available for electrical connection to a feature or element located
outside of compliant material layer 42, as discussed above. In the
examples shown in the Figures, a surface, such as major surface 44
of compliant material layer 42 can be spaced apart from first
surface 14 of semiconductor 12 at a distance great enough to cover,
for example, bases 34 and portions of the edge surfaces 37 of wire
bonds 32 to provide some level of mechanical support therefor and
to separate and electrically insulate the wire bonds 32 from each
other. Other configurations for compliant material layer 42 are
possible. For example, a compliant material layer can have multiple
surfaces with varying heights.
[0040] The example of wire bonds 32 shown in FIG. 1, which are
shown in further detail in FIGS. 3A and 4, define a particular
curved shape that can be imparted on the wire bonds 32 by a process
of making the wire bonds 32 that utilizes a secondary surface. Such
a method is further described below in connection with FIGS. 7-13.
The shape of wire bonds 32 can be such that the end surfaces 38 are
aligned along an axis 50 with a base end 35 of the wire bond 32
that is immediately adjacent the base 34. In the example of wire
bond 32 shown in FIG. 3A, the axis is generally perpendicular to
the conductive element 28 such that the end surface 38 is
positioned directly above the base end 35. Such a configuration can
be useful for a plurality of wire bonds 32 in an array wherein the
array of connections on major surface 44 of compliant material
layer 42 are intended to have a pitch that generally matches a
pitch of the conductive elements 28 to which the wire bonds 32 are
respectively joined. In such a configuration, the axis 50 can also
be angled with respect to contact portion 30 such that end surface
38 is offset slightly from the base end 35 but is still positioned
above base 34. In such an example, the axis 50 can be at an angle
of 85.degree. to 90.degree. with respect to contact portion 30.
[0041] Wire bond 32 can be configured such that a first portion 52
thereof, on which the end surface 38 is defined, extends generally
along a portion of the axis 50. The first portion 52 can have a
length that is between about 10% and 50% of the total length of
wire bond 32 (as defined by the length of axis 50, for example). A
second portion 54 of the wire bond 32 can be curved, or bent, so as
to extend away from the axis from a location adjacent the first
portion 52 to an apex 56 that is spaced apart from the axis 50. The
second portion 54 is further curved so as to be positioned along
axis 50 at a location at or near base end 35 and to also extend
away from the axis 50 to apex 56 from the side of base end 35. It
is noted that first portion 52 need not be straight or follow axis
50 exactly and that there may be some degree of curvature or
variation therein. It is also noted that there may be abrupt or
smooth transitions between first portion 52 and second portion 54
that may themselves be curved. It is noted, however, that the wire
bonds 32 depicted in FIGS. 1 and 3A, including second portion 54,
are further configured to lie on a single plane on which axis 50
also lies.
[0042] Further, both first 52 and second 54 portions of the wire
bond 32 can be configured such that any portions thereof that do
not intersect axis 50 are all on the same, single side of axis 50.
That is, some of first and second portions 52 and 54 may be, for
example, on a side of axis 50 opposite the apex 56 of the curved
shape defined by second portion 54; however, any such portions
would be in areas of the wire bond 32 that axis 50 intersects at
least partially. In other words, first and second portions 52 and
54 of wire bond 32 can be configured to not fully cross axis 50
such that the edge surface 37 within those portions is only spaced
apart from axis 50 on a single side of axis 50. In the example of
FIG. 3A the plane can be along the page on which the illustration
of wire bond 32 is presented.
[0043] FIGS. 3B and 3C show examples of wire bonds 32 with ends 36
that are not positioned directly above the respective bases 34
thereof. That is, considering first surface 14 of semiconductor die
12 as extending in two lateral directions, so as to substantially
define a plane, an end 36 of one of the wire bonds 32 can be
displaced in at least one of these lateral directions from a
corresponding lateral position of base 34. As shown in FIGS. 3B and
3C, wire bonds 32 can be of the same general shape as the wire
bonds of FIG. 3A and can have an end 36 that is aligned with the
portion of the wire bond 32 immediately adjacent the base 34
thereof to define an axis 50. The wire bonds 32 can, similarly,
include a first portion 52 that extends generally along axis 50 and
a second portion 54 that is curved so as to define an apex 56 that
is spaced apart from axis 50 on a single side thereof to define a
plane that extends along axis 50. The wire bonds 32 of FIGS. 3B and
3C, however, can be configured such that the axis 50, defined as
described above, is angled with respect to contact portion 30 at an
angle of, for example, less than 85.degree.. In another example,
angle 58 can be between about 30.degree. and 75.degree..
[0044] Wire bond 32 can be such that the apex 56 defined within
second portion 54 of wire bond can be either exterior to the angle
58, as shown in FIG. 3B, or interior thereto, as shown in FIG. 3C.
Further, axis 50 can be angled with respect to contact portion 30
such that end surface 38 of wire bond 32 is laterally displaced
relative to contact portion 30 in multiple lateral directions. In
such an example, the plane defined by second portion 54 and axis 50
can itself be angled with respect to conductive element 28 and/or
first surface 14. Such an angle can be substantially equal to or
different than angle 58. That is the displacement of end 36
relative to base 34 can be in two lateral directions and can be by
the same or a different distance in each of those directions.
[0045] In an example, various ones of wire bonds 32 can be
displaced in different directions and by different amounts
throughout microelectronic element 10. Such an arrangement allows
for microelectronic element 10 to have an array of extending
portions 40 that is configured differently on the level of surface
44 compared to on the level of first surface 14 of semiconductor
die 12. For example, an array can cover a smaller overall area or
have a smaller pitch on surface 44 than at the first surface 14 of
semiconductor die 12. In a variation of the microelectronic element
10 of FIG. 1, wire bonds 32 can be angled as shown in FIG. 3B, FIG.
3C, or a combination thereof.
[0046] As shown in FIG. 4, the free ends 36 of at least some of the
wire bonds can have an asymmetrical configuration the end surfaces
38 thereof defined on tips 62 of the wire bonds 32 that are
narrower than the adjacent portions of thereof, at least in one
direction. The narrow tip 62 of the free end 36 can be imparted on
wire bond 32 by a process used for manufacture thereof, an example
of which is discussed further below. As shown, the narrow tip 62
can be offset such that an axis 60 through the center thereof is
offset from an axis 62 through the center of the adjacent portion
of the wire bond 32. Further, a centroid 64 of the end surface 38
can be along axis 60 such that it is offset from the adjacent wire
bond portion. The tip 62 of wire bond 32 may also be narrowed in a
direction perpendicular to the dimensions shown in FIG. 11 or can
be the same width as the adjacent portion of wire bond 32 or can be
somewhat wider. The extending portions 40 of the wire bonds 32 may
include all or part of the tips 62 of wire bonds having such tips
or may include the entire tips 62 and portions of the wire bonds
extending beyond the tips 62.
[0047] As discussed above, wire bonds 32 can be used to connect
microelectronic element 10 with an external component. FIG. 2 shows
an example of an assembly 24 of a microelectronic element 10 that
can be as described in connection with FIG. 1, or any of the
variations thereof described in connection therewith. The extending
portions 40 of wire bonds 32 are joined with contact pads 48 of a
substrate 46 by solder masses 66 that extend along the extending
portions 40 of wire bonds 32 and along contact pads 48. Substrate
46 can be in the form of a dielectric element that is substantially
flat. The dielectric element may be sheet-like and may be thin. In
particular embodiments, the dielectric element can include one or
more layers of organic dielectric material or composite dielectric
materials, such as, without limitation: polyimide,
polytetrafluoro-ethylene ("PTFE"), epoxy, epoxy-glass, FR-4, BT
resin, thermoplastic, or thermoset plastic materials. The thickness
of substrate 46 is preferably within a range of generally
acceptable thicknesses for the desired application and, in an
example, can be between about 25 and 500 .mu.m. The substrate 46
can further include terminals 49 opposite the contact pads 48 in
the same or different array configuration. The terminals 49 can be
connected with the contact pads 48 by routing circuitry 64 within
substrate 46.
[0048] The assembly 24 can further include a molded dielectric
layer 68 that can, for example, be molded over the surface of the
substrate 46 facing microelectronic element 10. The molded
dielectric layer 68 be an encapsulant, for example, and can fill
spaces between the solder masses 66 and can contact the substrate
46 and the third surface 44 of the compliant material layer 42 in
the area therebetween. Molded dielectric 68 can further extend
outwardly along substrate 46 and upwardly along the edge surfaces
45 and 23 of the compliant material layer 42 and of semiconductor
die 12, respectively, and can optionally cover microelectronic
element 10 by extending over second surface 16 of semiconductor die
12. Substrate 46 can include package terminals opposite contact
pads 48 or other structures to facilitate connection of the package
assembly 24 with an external component.
[0049] In another example, a microelectronic element can similarly
be joined directly with a printed circuit board ("PCB") in place of
substrate 46. Such a PCB can be assembled within an electronic
device such that connection of microelectronic element 10 with the
PCB can be done in assembling microelectronic element 10 with such
a device. Further, such assembling can be carried out without the
incorporation of a molded dielectric.
[0050] In either such assembly or application of a microelectronic
element 10 as described herein, the structure of the wire bonds 32,
along with the incorporation of compliant material layer 42
according to the principles described herein, can help improve the
reliability of the attachment of microelectronic element 10 with a
substrate in a package assembly or with a PCB (or other component).
In particular, the reliability of the connections therebetween,
which in the case of microelectronic element 10, is made between
the extending portions 40 of wire bonds 32 and corresponding
conductive features of the connected component (e.g. contact pads
48) can be improved relative to, for example, a direct connection
between contacts of a semiconductor die and terminals of a
substrate. This improvement can be accomplished by the ability of
wire bonds 32 to flex or bend to accommodate relative movement
between the conductive elements 28 of semiconductor die 12 and the
contact pads 48 of substrate 46 (or PCB or other similar
structure). Such movement can be caused by handling of the
components, movement of the device, e.g., in which microelectronic
element 10 or an assembly thereof is used, or testing of the
microelectronic element 10 or assembly 24. Further, such relative
movement can be caused by expansion and corresponding contraction
of the components during the use cycle thereof caused by heat
generated by the components and/or surrounding structures. Such
thermal expansion is related to the coefficient of thermal
expansion ("CTE") of the components, and the relative movement
between components in different structures can be caused by a
difference, or mismatch, in the CTEs of the various structures or
the materials thereof. For example, a semiconductor die can have a
CTE of between about 2 and 5 parts per million per degree, Celsius
(ppm/.degree. C.). In the same assembly, a PCB or substrate can
have a CTE of 15 ppm/.degree. C. or greater.
[0051] The CTE of either component can be a "composite" CTE, which
refers to a the CTE of the finished structure, which can
approximate, but may not exactly match, the CTE of the primary
material from which such a structure is constructed and can depend
on the construction of the structure and the presence of other
materials with different CTEs. In an example, the CTE of the
semiconductor die can be on the order of Silicon or another
semiconductor material, from which the die is primarily
constructed. In another example, substrate 46 can have a CTE on the
order of PTFE or another dielectric material, from which substrate
46 can be constructed.
[0052] Accordingly, a CTE mismatch between materials can cause
relative movement between the conductive elements 28 of
semiconductor die 12 and the contact pads 48 of substrate 46 (or
another structure, such as a PCB or the like) as the semiconductor
die 12 and the substrate 46 expand and contract during thermal
cycling of the assembly 24 thereof because the semiconductor die 12
and substrate 46 expand at different rates and by different amounts
in response to the same temperature change. This can cause
displacement of the contact pads 48 with respect to the conductive
elements 28, particularly in the peripheral areas of the substrate
46 or the semiconductor die 12 (i.e. toward edge surfaces 23
thereof) or in other areas depending on the particular
configurations of the components and/or conductive elements 28 and
contact pads 46.
[0053] The flexibility of wire bonds 32 along the respective
lengths thereof can allow the end surfaces 38 thereof to displace
with respect to the bases 34 in a resilient manner. Such
flexibility can be used to compensate for relative movement of the
associated conductive elements 28 and contact pads 46 between which
the wire bonds 32 are connected. Because wire bonds 32 are
flexible, however, they may not themselves be able to reliably
support semiconductor die 12 relative to substrate 46 or other
structure. For example, the flexing of unsupported wire bonds 32
could lead to adjacent wire bonds 32 coming into contact with one
another, which could cause shorting or otherwise damage wire bonds
32 or the associated components. Accordingly, compliant material
layer 42 is configured to separate wire bonds 32 from each other
and to adding to the structural rigidity along the height thereof,
while permitting desired flexing of wire bonds 32 to compensate for
displacement of contact pads 46 relative to conductive elements 28.
Accordingly, compliant material layer 42 can be made of a
resiliently deformable (i.e. compliant) composition such as a
material with a Young's modulus of less than 2.5 GPa. Further,
compliant material layer 42, as mentioned above, can be dielectric
so as to electrically insulate the wire bonds 32 from one another
without requiring additional coatings or the like. Suitable
materials for compliant material layer include silicone,
benzocyclobutene ("BCB"), epoxy, or the like.
[0054] In such a structure, it may be beneficial to configure
microelectronic element 10 to be able to make a connection with
substrate 12 with the connection being robust enough to cause and
flexing of wire bonds 32 within compliant layer 42 (which requires
deformation of compliant layer 42). The extending portions 40 of
wire bonds 132 can be configured to achieve such a connection. For
example, by being uncovered by compliant material layer 42 so as to
be physically separated therefrom, extending portions 40 allow
conductive metal masses 66 to completely surround at least some of
the edge surfaces 37 of wire bonds 32 within extending portions 40,
which can provide a more robust connection than one achieved by a
mass 66 that simply extends along a side thereof, for example. To
allow adequate access for a conductive metal mass 66 to surround a
extending portion 40, the extending portions 40 can be oriented
relative compliant material layer 42 such that the axes 50 of wire
bonds 32 within extending portions 40 are at an angle of between
about 30.degree. and 90.degree. with respect to surface 44.
Further, the strength of the bond can be increased by structuring
wire bonds 32 and compliant material layer 42 such that extending
portions have a height above surface 44 of 200 .mu.m or less. In an
example, extending portions 40 can have heights of between 50 and
200 .mu.m.
[0055] In some examples where a molded dielectric 68 is also
included in an assembly 24 with microelectronic element 10, the
molded dielectric can itself be compliant, with a Young's modulus
that, in an example, can be greater than that of compliant material
layer 42 and, in a further example, less than that of either
semiconductor die 12 or substrate 46.
[0056] FIGS. 5 and 6 show examples of microelectronic elements 110
and 210 that incorporate multiple semiconductor dies in a stacked
arrangement. In the example of FIG. 5, first surface 114 of
semiconductor die 112 is considered as being divided into a first
region 118 and a second region 120. The first region 118 lies
within the second region 120 and includes a central portion of
first surface 114 and extends outwardly therefrom. The second
region 120 substantially surrounds the first region 118 and extends
outwardly therefrom to the outer edges of semiconductor die 112. In
this example, no specific characteristic of the semiconductor die
112 physically separates the two regions; however, the regions are
demarked for purposes of discussion herein with respect to
treatments or features applied thereto or contained therein. The
wire bonds 132 are connected with conductive elements 128 at
surface 114 within the second region 120.
[0057] A second semiconductor die 122 is mounted on semiconductor
die 112 within first region 118. In the example shown in FIG. 5,
semiconductor die 122 is mounted face down on semiconductor die 112
and is electrically and mechanically joined therewith by conductive
metal masses 66 that can be solder masses, for example. In such a
structure, conductive elements at the surface of semiconductor die
122 that faces first surface 114 can be connected with routing
circuitry at face 114 of semiconductor die 112 that extends within
first region 118. Such routing circuitry can include traces, for
example, that extend into second region 120 and connect with some
of the conductive elements 128 at face 114 within second region
120. Other conductive elements 128 are connected to the internal
components of semiconductor die 112. As such, wire bonds 132 can be
used to facilitate connections with both semiconductor die 112 and
semiconductor die 122 at third surface 144 of compliant layer 142.
To achieve such a structure, both wire bonds 132 and compliant
layer 142 can be of a height sufficient for extending portions 140
of wire bonds 132 to be positioned above semiconductor die 122,
which can be covered by compliant layer 142. Microelectronic
element 110 can be mounted to a substrate, PCB, or other structure
in a manner similar to microelectronic element 10, described above,
in which wire bonds 132 within compliant layer 142 can compensate
for a CTE mismatch between components in a similar manner.
[0058] In the example of FIG. 6, second semiconductor die 222 is
mounted on semiconductor die 212 within first region 218.
Semiconductor die has conductive elements 228a disposed within
second region 220 surrounding semiconductor die 222 with wire bonds
232a connected therewith. In this example, however, semiconductor
die 222 is mounted face-up on semiconductor die 212 such that the
conductive elements 228b thereof face away from surface 214 of
semiconductor die 212. In this structure, second wire bonds 232b
are connected with conductive elements 228b and extend to ends 238
remote from the conductive elements 228b. Compliant material layer
242 covers surface 214 of semiconductor die 212 in areas outside of
wire bonds 232a and outside of semiconductor die 222. Compliant
material layer further covers semiconductor die 222 such that
compliant material layer 242 separates and extends between the edge
surfaces 237 of wire bonds 232a and 232b. As such, microelectronic
element 210 can be mounted on a substrate, PCB, or other structure
by connecting the extending portions 240 of wire bonds 232a and
232b with features of that structure in a manner similar to
microelectronic element 10, described above.
[0059] In such a structure, it may be desired to configure wire
bonds 232a and 232b with heights sufficient to compensate for a CTE
mismatch among components, as described above. In this structure,
wire bonds 232a and 232b can be configured with a height sufficient
to provide a desired height for extending portions 240 and
sufficient compensation for displacement of features with which
they are connected due to CTE mismatch. Displacement of contact
pads on a substrate, for example, relative to the conductive
elements 228a may be greater than with respect to conductive
elements 228b because displacement is greater towards the
peripheries of such structures. Accordingly, wire bonds 232b may
have heights that are less than would be necessary within a
similarly-sized microelectronic element including only one
semiconductor die.
[0060] FIGS. 7-12 show a microelectronic element 10 in various
steps of a fabrication method thereof. FIG. 7 shows in-process unit
10' consisting of semiconductor die 12, as described above, with
conductive elements 28 at first surface 14 thereof. In FIG. 8, in
process unit 10'' is shown having a wire bonds 32 formed on
conductive element 28 of the semiconductor die 12. Such wire bonds
can be formed using specially-adapted equipment that can be
configured to form a plurality of successive wire bonds in an
assembly by heating a leading end of a wire that passes through a
bonding capillary. The capillary is aligned with one of the
conductive elements 28, which accordingly aligns the leading end of
the wire therewith. The base 34 of a wire bond is then formed
joined to the conductive element 28 by pressing the heated free end
thereagainst by appropriate movement of the capillary.
[0061] After a desired length of the wire has been drawn out of the
capillary so as to extend above first surface 14 of semiconductor
die 12 at an appropriate distance for the height of the wire bond
to be formed (which can also include positioning of the wire to
achieve a desired location for the free end 36 thereof and/or
shaping of the wire bond 32 itself), the wire is severed to detach
the wire bond 32 at the end surface 38 from a portion of the wire
that remains in the capillary and is used in the formation of a
successive wire bond. This process is repeated until the desired
number of wire bonds is formed. Various steps and structures can be
used to sever the wire bonds 32, including electronic flame-off
("EFO"), various forms of cutting or the like, examples of which
are provided in U.S. patent application Ser. Nos. 13/462,158 and
13/404,408, and in U.S. Pat. No. 8,372,741. A further example of
wire bond severing is discussed below with respect to FIGS. 14 and
15. In variations of the above-described wire bond formation steps,
wire bonds 32 can be formed on the in-process unit 10'' by edge
bonding steps, including wedge bonding or stitch bonding, using
specially-adapted equipment, as described in U.S. patent
application Ser. No. 13/404,408.
[0062] After formation of the desired number of wire bonds 32,
compliant material layer 42 can be formed by depositing the desired
material in a flowable state over in-process unit 10'', as shown in
FIG. 9, before being allowed to harden or cure in place. This can
be done by placing the unit 10' in an appropriately-configured mold
having a cavity in the desired shape of the compliant material
layer 42 that can receive unit 10'. Such a mold and the method of
forming a compliant material layer therewith can be done in a
procedure similar to the procedure for forming an encapsulation
layer over wire bonds on a substrate that is shown and described in
U.S. Pat. App. Pub. No 2010/0232129, the disclosure of which is
incorporated by reference herein in its entirety. Compliant
material layer 42 can be formed such that, initially, surface 44
thereof is spaced above end surfaces 38 of wire bonds 32. To form
extending portions 40, including end surfaces 38, the portion of
encapsulation layer 42 that is above end surfaces can be removed,
creating a new surface 44 that is positioned below end surfaces 38.
Alternatively, compliant material layer 42 can be formed such that
surface 44 is initially below end surfaces 38 at a distance to
define the desired height of detached portions 40. Removal, if
necessary, of a portion of encapsulation layer 42 can be achieved
by grinding, dry etching, laser etching, wet etching, lapping, or
the like. If desired, a portion of the free ends 36 of wire bonds
32 can also be removed in the same, or an additional, step to
achieve substantially planar end surfaces 38 that are substantially
even with each other.
[0063] As discussed above, the microelectronic element 10 resulting
from the above steps, or variations thereof, can be packaged on a
substrate or mounted on a PCB. Either of these subsequent steps can
be carried out in a similar manner. In an example shown in FIG. 10,
microelectronic element 10 can be prepared for bonding with an
external component by depositing conductive metal masses 66, which
can be of solder or the like over the extending portions 40 of wire
bonds 32. The masses 66 can be allowed to cool and solidify so that
the masses 66 remain at least temporarily fixed in the locations on
respective extending portions 40. As shown in FIG. 11, the
microelectronic element 10 from FIG. 10 can be aligned with a PCB
90 with the masses 66, and accordingly the extending portions 40 of
the wire bonds 32, aligned with contact pads 92 of the PCB. The
masses 66 can then be brought into contact with the pads 92 and
heated to reflow the conductive material to join it with the pads
92 and to fix microelectronic element 10 to PCB 90, as shown in
FIG. 12.
[0064] In a variation of the mounting steps of FIGS. 10-12,
conductive metal masses 66 can be deposited on contact pads 92, as
shown in FIG. 13 in preparation for microelectronic element
mounting. Microelectronic element 10 can then be positioned over
PCB 90 with extending portions 40 of wire bonds 32 aligned with the
masses 66 (and, thus, with contact pads 92). The masses 66 can be
heated to cause reflow and microelectronic element 10 can be moved
toward PCB 90 such that extending portions 40 are positioned within
masses 66, which can then be allowed to cool to join with extending
portions 40.
[0065] Either of the above-discussed steps (from FIGS. 10-12 and
13) can also be used to join a microelectronic element 10, formed
as described above, to a substrate 46 in a package assembly 24, as
described above with respect to FIG. 2. Such a package 24 can be
further processes to deposit molded dielectric 68 thereon, as shown
in FIG. 2, which can be done using molding or other methods used
elsewhere for molded dielectric formation in microelectronic
packaging. Alternatively, an underfill can be deposited in the area
between the microelectronic element 10 and the substrate 46
surrounding the conductive metal masses 66.
[0066] Variations of the above-described method steps can also be
used to form and package or mount the multi-die arrangements shown
in FIGS. 5 and 6. In such variations, second die 22 can be mounted
on die 12 before or after wire bond formation (which can be done by
any of the methods discussed herein). In the example of FIG. 6,
mounting die 222 on die 212 before wire bond formation could result
in the wire bonds 232 being formed all at once, instead of in
subsequent steps. After die mounting and wire bond formation, the
compliant layers 242 and 342 can be deposited as discussed above,
and the packages can be mounted, as previously discussed and in the
same manner as single die microelectronic device 10.
[0067] FIGS. 14 and 15 show an in-process unit 10' during
particular method steps that can be used in wire bond formation. As
shown in FIG. 14, capillary 70 of a wire bonding tool in proximity
to the first surface 14 of substrate 12. The capillary 70 shown
schematically in FIG. 4, along with the bonding tool (not shown)
with which it is associated can be of the type generally described
above and can join the bases 34 of wire bonds 32 to the conductive
elements 28 of semiconductor die 12.
[0068] In this particular set of method steps, after a desired
length of the wire 74 has been drawn out of capillary 70 for the
desired height of the wire bond to be formed, the wire 77 is
severed and appropriately positioned using a face 76 of the
capillary 70 and a secondary surface 80. As shown in FIG. 14, the
severing and positioning is started by moving capillary 70 to a
position over a secondary surface 80, which is shown schematically
as a surface of an element in FIG. 14. In various applications, the
secondary surface 80 can be on an element of sufficient hardness
for the severing application described below such as metal or the
like. Such an element can be attached with the bonding tool in a
position to follow capillary 70 as it is moved during the wire
bonding process.
[0069] In another example, the element can be fixed relative to the
bonding tool in the area of the semiconductor die 12.
[0070] In the example shown in FIG. 14, the capillary 70 is
positioned over the secondary surface 80. After capillary 70 is
appropriately positioned, it is pressed toward secondary surface 80
with a portion of the wire 74 between secondary surface 80 and a
face 76 of capillary 70 that extends outwardly from wire 74.
Pressure is then applied to the wire to move face 76 toward
secondary surface 80, which compresses wire 74 therebetween,
causing plastic deformation of wire 74, e.g., flattening or
constriction of the wire, in area 78. Through such deformation,
area 78 of wire 74 becomes somewhat weaker than the remaining
portions of wire 74 on either side thereof and weaker than the
joint between base 34 and contact portion 30. For example, area 78
may be somewhat flattened, constricted, or twisted relative to
other portions of the wire 74 on either side thereof.
[0071] After deformation of area 78 of wire 74, the capillary 70 is
then moved back toward a final desired position for the free end 36
of the wire bond 32 to-be formed. This position can be directly
above base 43 or can be laterally displaced therefrom, as discussed
above with respect to the examples of FIGS. 3B and 3C. The position
of capillary 70 can be generally in the desired lateral area of
free end 36 and can be just somewhat closer to first surface 14
than the desired final position. Further, the wire may remain
partially bent, including a shape similar to the shape of the
finished wire bonds 32 discussed above including a first portion 52
and second portion 54.
[0072] Capillary 70 can then be moved away from surface 14 to apply
tension to the segment of wire 74 (which can be clamped or
otherwise secured within capillary 70) between capillary 70 and
base 34. This tension causes wire 74 to break within area 78, as
shown in FIG. 15, which separates wire bond 32 from the remaining
portion of wire 74 with a portion of area 78 forming the tip 62 of
free end 36 with end surface 38 defined thereon. A remaining
portion of area 78 remains on a new leading end 72' of the wire 74.
These steps can be repeated on other conductive elements 28 at the
surface 14 of the semiconductor die 12 to form an array of wire
bonds 32 in a desired pattern.
[0073] Although the invention herein has been described with
reference to particular embodiments, it is to be understood that
these embodiments are merely illustrative of the principles and
applications of the present invention. It is therefore to be
understood that numerous modifications may be made to the
illustrative embodiments and that other arrangements may be devised
without departing from the spirit and scope of the present
invention as defined by the appended claims.
* * * * *