U.S. patent application number 14/097214 was filed with the patent office on 2015-02-19 for electronic device package structure and method fabricating the same.
This patent application is currently assigned to Amkor Technology, Inc.. The applicant listed for this patent is Amkor Technology, Inc.. Invention is credited to Young Suk Chung, Yoon Joo Kim, Jong Sik Paek, Doo Hyun Park, Seong Min Seo.
Application Number | 20150049421 14/097214 |
Document ID | / |
Family ID | 52466665 |
Filed Date | 2015-02-19 |
United States Patent
Application |
20150049421 |
Kind Code |
A1 |
Paek; Jong Sik ; et
al. |
February 19, 2015 |
ELECTRONIC DEVICE PACKAGE STRUCTURE AND METHOD FABRICATING THE
SAME
Abstract
In one embodiment, an electronic device package structure
includes an electronic die having conductive pads on one surface.
The one surface is further attached to at least one lead. A
conductive layer covers at least one conductive pad and at least
portion of the lead thereby electrically connecting the lead to the
conductive pad.
Inventors: |
Paek; Jong Sik; (Incheon,
KR) ; Park; Doo Hyun; (Gyeonggi-do, KR) ; Kim;
Yoon Joo; (Seoul, KR) ; Seo; Seong Min;
(Seoul, KR) ; Chung; Young Suk; (Seoul,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Amkor Technology, Inc. |
Chandler |
AZ |
US |
|
|
Assignee: |
Amkor Technology, Inc.
Chandler
AZ
|
Family ID: |
52466665 |
Appl. No.: |
14/097214 |
Filed: |
December 4, 2013 |
Current U.S.
Class: |
361/676 ;
29/825 |
Current CPC
Class: |
H01L 23/49582 20130101;
H01L 23/4951 20130101; H01L 23/49517 20130101; H01L 21/561
20130101; H01L 2224/16245 20130101; H01L 23/16 20130101; H01L
2224/24245 20130101; Y10T 29/49117 20150115; H01L 2924/181
20130101; H01L 23/49548 20130101; H01L 23/3107 20130101; H01L 24/82
20130101; H01L 2924/181 20130101; H01L 2924/00012 20130101 |
Class at
Publication: |
361/676 ;
29/825 |
International
Class: |
H05K 1/11 20060101
H05K001/11; H05K 1/18 20060101 H05K001/18 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 13, 2013 |
KR |
10-2013-0096196 |
Claims
1. An electronic device comprising: an electronic die including a
conductive pad on a major surface; a lead including a first region
in spaced relationship with the electronic die and a second region
extending from the first region in a direction away from the
electronic die; a conductive layer overlapping the conductive pad
and the lead thereby electrically connecting the conductive pad to
the lead; and a package body covering the electronic die and at
least portions of lead.
2. The device of claim 1, further comprising a mounting board
attached to the electronic die.
3. The device of claim 1, wherein the major surface contacts the
lead.
4. The device of claim 1, wherein the conductive pad and the lead
are spaced apart.
5. The device of claim 1, wherein the first region is thinner than
the second region.
6. The device of claim 1, wherein the conductive layer comprises a
plated material covering the conductive pad and at least a portion
of the first region.
7. The device of claim 1, wherein the conductive layer comprises a
solder material covering the conductive pad and at least a portion
of the first region.
8. The device of claim 1, wherein: the first region includes a
hole; the conductive pad is within the hole; and the conductive
layer overlaps the hole.
9. The device of claim 1, wherein an outer laterals surface and a
bottom surface of the second region are exposed in encapsulant.
10. An electronic package device comprising: an electronic die
having a plurality of conductive pads on a major surface; a
plurality of leads, each lead being in spaced relationship with the
major surface; a conductive layer covering each conductive pad and
at least a portion of each lead; and a package body encapsulating
at least portions of the electronic die and at least portions of
the plurality of leads.
11. The device of claim 10, wherein at least some leads comprises a
first region and a second region extending from the first region in
a direction away from the electronic die; the first region is
thinner than the second region; and the first region is proximate
to one of the plurality of conductive pads.
12. The device of claim 11, wherein the first region includes hole
surrounding one of the plurality of conductive pads.
13. The device of claim 10, wherein the conductive layer comprises
a solder material
14. The device of claim 10, wherein the conductive layer comprises
a plated material.
15. A method for forming an electronic device comprising: providing
a lead frame including a plurality of leads, the plurality of leads
each having a first region and a second region extending from the
first region; attaching an electronic die including a plurality of
conductive pads on a major surface to the lead frame; forming a
conductive layer connecting the conductive pads to the leads; and
encapsulating the electronic die and at least portions of the leads
and with an encapsulant.
16. The method of claim 15, wherein encapsulating includes leaving
side portions of the leads exposed side portions of the leads; the
method further comprising singulating through the exposed side
portions of the leads.
17. The method of claim 15, wherein: providing the lead frame
includes providing the lead frame where at least a portion of the
leads include first regions that are thinner than the second
regions; attaching the electronic device includes attaching the
major surface to the leads, wherein the conductive pads are spaced
apart from the leads; and forming the conductive layer includes
covering the conductive pads.
18. The method of claim 17, wherein forming the conductive layer
includes plating the conductive layer.
19. The method of claim 17, wherein forming the conductive layer
including forming a solder layer.
20. The method of claim 17, wherein: providing the lead frame
includes providing the lead frame where at least some of the first
regions include a hole; attaching the electronic device includes
attaching the electronic device so that a conductive pad is within
one of the holes; and forming the conductive layer comprises
covering each hole with the conductive layer.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to Korean Patent
Application No. 10-2013-0096196 filed on Aug. 13, 2013, which is
expressly incorporated by reference herein.
BACKGROUND
[0002] The present invention relates to electronic devices and,
more specifically, to electronic device package structures and
methods of fabricating the same.
[0003] Electronic devices, such as semiconductor dies, are
conventionally enclosed in plastic packages that protect the
semiconductor die from hostile environments and that enable
electrical interconnection between the semiconductor die and a next
level of assembly, such as a printed circuit board (PCB) or
motherboard. The elements of a typical electronic package include a
conductive leadframe and an integrated circuit or semiconductor
die. In order to electrically connect the semiconductor die to
leads of the leadframe, conductive structures are necessary to
connect bond pads on the semiconductor die to the leads. A hard
plastic encapsulant material typically covers the other components
and forms an exterior package body. In the past, the bond pads on
the semiconductor die and the leads were connected to each other by
connective wires forming using wire bonding techniques. However,
wire bonding has been a costly and complicated process, and the
resultant wire bonds have been a source of reliability issues and
have added undesired thickness to package bodies because of the
need to cover them.
[0004] Accordingly, it is desirable to have a structure and method
that provides an improved electrical interconnection between
electronic chips and the substrates used to support them. It is
also desirable to have a structure a method that is cost effective,
easy to integrate into assembly process flows, and reliable.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 illustrates a cross-sectional view of an electronic
device in accordance with an embodiment of the present
invention;
[0006] FIG. 2 illustrates a cross-sectional view of an electronic
device in accordance with another embodiment of the present
invention;
[0007] FIG. 3 illustrates a cross-sectional view of an electronic
device in accordance with a further embodiment of the present
invention;
[0008] FIG. 4 illustrates a cross-sectional view of an electronic
device in accordance with a still further embodiment of the present
invention;
[0009] FIG. 5 illustrates a flowchart of a fabricating method of an
electronic device in accordance with an embodiment of the present
invention;
[0010] FIGS. 6A to 6G illustrate bottom views and cross-sectional
views of an electronic device at various stages of fabrication in
accordance with an embodiment of the present invention;
[0011] FIGS. 7A to 7C illustrate cross-sectional views of an
electronic device and various stages of fabrication in accordance
with another embodiment of the present invention;
[0012] FIGS. 8A to 8E illustrate cross-sectional views and bottom
views of an electronic device at various stages of fabrication in
accordance with a further embodiment of the present invention;
and
[0013] FIGS. 9A to 9C illustrate cross-sectional views of an
electronic device at various stages of fabrication in accordance
with a still further embodiment of the present invention.
[0014] For simplicity and clarity of the illustration, elements in
the figures are not necessarily drawn to scale, and the same
reference numbers in different figures can denote the same
elements. Additionally, descriptions and details of well-known
steps and elements may be omitted for simplicity of the
description.
DETAILED DESCRIPTION OF THE DRAWINGS
[0015] The aspects of the present invention and methods for
achieving the aspects will be apparent by referring to the
embodiments to be described herein with reference to the
accompanying drawings. It is understood that the embodiments
described herein are illustrative only and that the present
invention is not limited thereto, but can be implemented in
alternative forms. Also, it is understood that the features of the
various embodiments described herein can be combined with each
other, unless specifically noted otherwise.
[0016] In accordance with the present embodiments, an electronic
device can include an electronic die having a plurality of
conductive connection pads on one surface. In one embodiment, the
electronic die can be a semiconductor die and the conductive
connection pads can be bond pads. At least one lead includes first
and second regions with the first region attached to or proximate
to the surface of the semiconductor die having the bond pads formed
thereon. The second region extends from the first region and can
extend in a direction away from the semiconductor die. A conductive
layer overlaps or covers the bonds pads and at least a portion of
the lead and is configured to electrically connect at least one
bond pad to the lead. A package body can encapsulate the
semiconductor and at least portions of die while other portions of
the lead can be exposed in the package body for connecting to a
next level of assembly. In one embodiment, the conductive layer can
be plated layer. In another embodiment, the conductive layer can be
a solder material. The present embodiments are configured to
provide a simplified, cost effective, and more reliable conductive
connective structure and method that overcome problems associated
with previous connective structures.
[0017] FIG. 1 illustrates a cross-sectional view of an electronic
device in accordance with a first embodiment. In the present
embodiment, the electronic device is configured as a semiconductor
device 100. In one embodiment, semiconductor device 100 includes a
semiconductor die 120, which can have a plurality of conductive
connection pads, connection pads, or bond pads 121, and leads 113
including a first region 113a contacting or proximate to
semiconductor die 120 and a second region 113b extending from first
region 113a in a direction generally away from semiconductor die
120. In accordance with the present embodiment, semiconductor die
120 further includes a conductive layer 130 electrically connecting
bond pads 121 to leads 113 and an encapsulant 140 encapsulating
semiconductor die 120 and at least portion leads 113 to provide a
package body.
[0018] In one embodiment, semiconductor device 100 can further
include an optional mounting board 111, which is configured for
mounting semiconductor die 120 thereto. In one embodiment, an
adhesive layer (not shown) can be used to attach semiconductor die
120 to mounting board 111. In one embodiment, mounting board 111 is
smaller is size than semiconductor die 120.
[0019] As generally illustrated in FIG. 1, leads 113 are spaced
apart from mounting board 111 and in one embodiment can be
configured to surround mounting board 111. In one embodiment, at
least one of leads 113 has a lower surface (for example, the
surface spaced apart from semiconductor die 120), which is
positioned generally on the same horizontal plane as the lower
surface of mounting board 111. In the present embodiment, first
region 113a of leads 113 is configured to contact or attach to
semiconductor die 120, and second region 113b of leads 113 is
configured to extend from first region 113a in a direction away
from semiconductor die 120. In one embodiment, first region 113a
has a thinner profile or has a cross-section that is smaller than
that of second region 113b, but aspects of the present embodiment
are not limited thereto. Leads 113 are configured to provide a path
for transmitting electrical signals between one or more external
devices to semiconductor device 100. Leads 113 can be made of one
or more conductive materials, such as alloys of copper (Cu), nickel
(Ni) or iron (Fe), and other materials as known by those of
ordinary skill in the art.
[0020] In accordance with the present embodiment, semiconductor die
120 is mounted or attached to mounting board 111 and first regions
113a of leads 113 using, for example, an adhesive material.
Semiconductor die 120 is generally made of silicon, IIV-V
materials, or IV-IV materials, and typically is formed to include
multiple electronic devices in an integrated circuit configuration
or is formed to be a discrete device. In one embodiment, bond pads
121 are formed on one major surface of semiconductor die 120, and
can be configured to be input/output structures for transmitting
electrical signals to and from semiconductor die 120. Although not
shown, an insulating layer can be formed on the one major surface
of semiconductor die 120 to insulate or passivate certain regions
of semiconductor die 120, but can be patterned to expose bond pads
121 so that contact can be made thereto. In one embodiment, bond
pads 121 and first regions 113a of leads 113 are spaced apart from
each other. In an alternative embodiment, bond pads 121 and first
regions 113a of leads 113 can make contact at least in part with
each other.
[0021] In accordance with the present embodiment, conductive layer
130 is formed on semiconductor device 100 to overlap, cover,
surround, adjoin, or encapsulate exposed or outer surfaces of leads
113 and bond pads 121 and is configured to electrically connect
them together. In one embodiment, conductive layer 130 is a
conductive connective layer or a plating layer and can be formed
using a copper (Cu) plating process or other conductive plating
process. In one embodiment, conductive layer 130 can be further
formed over or formed to conform to the outer or exposed surfaces
of second regions 113b of leads 113. In one embodiment, conductive
layer 130 can be formed to surround the outer or exposed surfaces
of mounting board 111.
[0022] In accordance with the present embodiment, semiconductor
device 100 includes conductive layer 130 that covers at least
portions of the outer surfaces of leads 113 and bond pads 121
thereby facilitating a conductive connective structure between
leads 113 and semiconductor die 120. One benefit of conductive
layer 130 is that it reduces the need for additional structural
elements, such as wire bonds, and can be formed using, for example,
available process techniques, such as plating processes so that
fabrication costs can be reduced and reliability can be
increased.
[0023] In one embodiment, encapsulant 140 is configured as a
package body that encapsulates semiconductor die 120. In one
embodiment encapsulant 140 also encapsulates at least portions of
leads 113, mounting board 111, and conductive layer 130. In one
embodiment, encapsulant 140 is formed so that outer lateral
surfaces of second regions 113b of leads 113 are exposed. In one
embodiment, encapsulant 140 is formed so that lower or bottom
surfaces of mounting board 111 and leads 113, which can be
positioned on the same general horizontal plane, are exposed. In
one embodiment, encapsulant 140 is configured to cover the top and
lateral surfaces of semiconductor die 120. Encapsulant 140 is
configured to protect semiconductor device 100 from external
environments, such as heat, moisture or shock, by sealing the
semiconductor die 120. Encapsulant 140 can be a silicon resin, an
epoxy resin, or other materials as known by those of ordinary skill
in the art.
[0024] As described above, semiconductor device 100 according to
the present embodiment utilizes conductive layer 130 to
electrically connect leads 113 to semiconductor die 120. Conductive
layer 130 is disposed to surround or cover leads 113 and bond pads
121 on semiconductor die 120 thereby electrically connecting leads
113 to semiconductor die 120. In accordance with the present
embodiment, conductive layer 130 provides a simplified and cost
effective connective structure between leads 113 and semiconductor
die 120. In addition, because conductive layer 130 is fixedly
formed on the outer surfaces of leads 130 and bond pads 121,
semiconductor die 120 can be more easily sealed by encapsulant
140.
[0025] FIG. 2 illustrates a cross-sectional view of an electronic
device in accordance with another embodiment. In the present
embodiment, the electronic device is configured as a semiconductor
device 200. Semiconductor device 200 includes semiconductor die 120
including bond pads 121, leads 113 including first regions 113a
contacting semiconductor die 120 and second regions 113b extending
from the first region 113a in a direction generally away from
semiconductor die 120. Conductive layers 230 are configured to
electrically connect bond pads 121 to leads 113. An encapsulant 140
encapsulates the semiconductor die 120 and at least portions of
leads 113 to provide a package body. In the present embodiment, a
mounting board is not illustrated, but it is understood that a
mounting board, such as mounting board 111, can be included.
[0026] In one embodiment, conductive layer 230 is configured as a
conductive connective layer and can be formed using a solder
material. In one embodiment, conductive layer 230 can be formed to
cover, encapsulate, overlap, or adjoin bond pads 121 and portions
of leads 113, such as all of or only portions of first regions
113a. Conductive layer 230 is configured to electrically connect
semiconductor die 120 and leads 113 together. Conductive layer 230
can be made of solder materials, such as alloys of tin (Sn), lead
(Pb) or silver (Ag), or other materials as known by those of
ordinary skill in the art. Conductive layer 230 can be a solder
paste or pre-form solder material.
[0027] In accordance with the present embodiment, semiconductor
device 200 utilizes conductive layers 230 of solder material to
electrically connect leads 113 to semiconductor die 120. In one
embodiment, the solder material can be disposed to cover,
encapsulate, adjoin, or overlap first regions 113a of leads 113
thereby electrically connecting leads 113 to semiconductor die 120.
Conductive layer 230 facilitates a cost effective conductive
connective structure that does not require additional assembly
elements, such as wire bonds. Further, because conductive layer 230
can be a single layer of solder material fixedly formed on outer
surfaces of first regions 113a and bond pads 121, semiconductor die
120 can be more easily sealed by encapsulant 140.
[0028] FIG. 3 illustrates a cross-sectional view of an electronic
device in accordance with a further embodiment. In the present
embodiment, the electronic device is configured as a semiconductor
device 300. Semiconductor device 300 is similar to semiconductor
devices 100 and 200 and the following description will describe the
differences between the present embodiment and the previous
embodiments.
[0029] Semiconductor device 300 includes semiconductor die 120
including plurality of bond pads 121, leads 313 including a first
region 313a contacting semiconductor die 120 and a second region
313b extending from first region 313a in a direction away from
semiconductor die 120. A conductive layer 330 is provided to
electrically connect bond pads 121 to leads 313. An encapsulant 140
encapsulates semiconductor die 120 and at least portions of leads
313 to provide a package body. In the present embodiment, a
mounting board is not illustrated, but it is understood that a
mounting board, such as mounting board 111, can be included.
[0030] In the present embodiment, first regions 313a of leads 113
contact or are proximate to semiconductor die 120 and second
regions 313b of leads 113 extend from first regions 313a in a
direction away from semiconductor die 120. In one embodiment, first
regions 313a have a thinner profile or cross section that is
smaller than that of second region 313b, but aspects of the present
embodiment are not limited thereto. In addition, holes or windows
314 can be formed in leads 313 (for example, in first regions 313a)
at locations corresponding to locations of bond pads 121 on
semiconductor die 120. In the present embodiment, holes 314 within
first regions 313a are configured to expose bond pads 121. Leads
313 are configured to provide a path for transmitting electrical
signals between one ore more external devices and semiconductor
device 300. Leads 313 can be made of one or more conductive
materials, such as alloys of copper (Cu), nickel (Ni) or iron (Fe),
and other materials as known by those of ordinary skill in the
art.
[0031] In one embodiment, conductive layer 330 is configured as a
conductive connective layer and can be formed using a solder
material. In accordance with the present embodiment, conductive
layer 330 is formed on semiconductor device 300 to overlap, cover,
surround, adjoin, or encapsulate exposed or outer surfaces of bond
pads 121 and at least portions of leads 113, such as all of or only
portions of first regions 313a and is configured to electrically
connect these elements together. In one embodiment, conductive
layer 330 is formed to cover holes 314 within first regions 313a of
leads 313. In one embodiment, solder material is disposed or formed
to cover bond pads 121, which are positioned within holes 314. In
one embodiment, conductive layer 330 of solder material covers or
overlaps bond pads 121 and at least portions of first region 313a
thereby electrically connecting leads 313 to semiconductor die 120.
Conductive layer 330 can be made of solder materials, such as
alloys of tin (Sn), lead (Pb) or silver (Ag), or other materials as
known by those of ordinary skill in the art. Conductive layer 330
can be a solder paste or pre-form solder material.
[0032] Semiconductor device 300 in accordance with the present
embodiment includes holes 314 placed, for example, in first regions
313a of leads 313 at locations corresponding to bond pads 121 on
semiconductor die 120. Conductive layer 330 of solder material is
formed or disposed within holes 314 and disposed adjoining at least
portions of leads 313 thereby electrically connecting leads 313 to
the semiconductor die 120. Conductive layer 330 facilitates a cost
effective conductive connective structure that does not require
additional assembly elements, such as wire bonds. In addition,
because bond pads 121 are positioned within holes 314, which are
filled with solder material, the conductive connective structure
between leads 313 and bond pads 121 can be performed more
accurately. More particularly, the foregoing hole configuration of
the present embodiment can improve reliability. Further, because
conductive layer 330 can be a single layer of solder material
fixedly formed on outer surfaces of first regions 313a and bond
pads 121, semiconductor die 120 can be more easily sealed by
encapsulant 140.
[0033] FIG. 4 illustrates a cross-sectional view of an electronic
device in accordance with a still further embodiment. In the
present embodiment, the electronic device is configured as a
semiconductor device 400. Semiconductor device 400 is similar to
semiconductor devices 100, 200 and 300 and the following
description will describe the differences between the present
embodiment and the previous embodiments.
[0034] Semiconductor device 400 in accordance with the present
embodiment includes semiconductor die 120 including plurality of
bond pads 121, leads 313 including first regions 313a contacting
semiconductor die 120 and second regions 313b extending from first
regions 313a in a direction away from semiconductor die 120, a
conductive layer 430 configured to electrically connect bond pads
121 to leads 313, and an encapsulant 140 encapsulating
semiconductor die 120 and at least portions of leads 313. Similarly
to semiconductor device 300, holes or windows 314 can be formed in
leads 313 (for example, in first regions 313a) at locations
corresponding to locations of bond pads 121 on semiconductor die
120. In the present embodiment, a mounting board is not
illustrated, but it is understood that a mounting board, such as
mounting board 111, can be included.
[0035] In accordance with the present embodiment, conductive layer
430 is formed on semiconductor device 400 to overlap, cover,
surround, adjoin, or encapsulate exposed outer surfaces of bond
pads 121 and at least portions of leads 113 and is configured to
electrically connect them together. In one embodiment, conductive
layer 430 is a conductive connective layer or a plating layer and
can be formed using a copper (Cu) plating process or other
conductive plating process. In one embodiment, conductive layer 430
can be formed to surround outer surfaces of leads 313 and holes 314
in which bond pads 121 are positioned to electrically connect leads
313 and semiconductor die 120 together. In one embodiment,
conductive layer 430 can be further formed over or to conform to
the outer or exposed surfaces of second regions 313b of leads
313.
[0036] In accordance with the present embodiment, semiconductor
device 400 includes the holes 314 placed, for example, in first
regions 313a of leads 313 at locations corresponding to bond pads
121 on semiconductor die 120. Conductive layer 430 of plated
conductive material is formed or disposed within holes 314 in which
bond pads 121 are positioned and further formed to cover or
surround (at least in part) leads 313 thereby electrically
connecting leads 313 to semiconductor die 120. Conductive layer 430
facilities a cost effective conductive connective structure that
does not require additional assembly elements, such as wire bonds.
In addition, because bond pads 121 are positioned within holes 314,
which are covered with conductive plated material, the conductive
connective structure between leads 313 and bond pads 121 can be
performed more accurately. More particularly, the foregoing hole
configuration of the present embodiment can improve reliability.
Further, because conductive layer 430 can be a plated layer that
fixedly formed along outer surfaces of leads 330 and bond pads 121,
semiconductor die 120 can be easily sealed by encapsulant 140.
[0037] FIG. 5 illustrates a flowchart for fabricating an electronic
device in accordance with a first embodiment. In the present
embodiment, the electronic device is described as a semiconductor
device. As illustrated in FIG. 5, the fabrication method includes
providing or preparing a lead frame or substrate (S10), mounting a
semiconductor die in spaced relationship with the lead frame (S20),
connecting the semiconductor die to a lead of lead frame (30),
encapsulating the structure (S40) and singulating the structure
(S50) to provide packaged electronic or semiconductor devices.
[0038] FIGS. 6A to 6G illustrate cross-sectional views and bottom
views of an electronic device (for example, semiconductor device
100) at various stages of fabrication in accordance with a first
embodiment. By way of example, a method for fabricating
semiconductor device 100 will be described with reference to FIG. 5
and FIGS. 6A to 6G. As illustrated in FIGS. 5, 6A and 6B, in step
S10, a lead frame 110 is provided that includes a plurality of
leads 113. In one embodiment, lead frame 110 can further include a
mounting board or support structure 111 positioned generally on the
same plane as leads 113. In other embodiments, mounting board 111
is not included. In one embodiment, leads 113 are provided in lead
frame 110 and generally surround mounting board 111. In one
embodiment, mounting board 111 can be fixed within lead frame 110
using tie bars 112.
[0039] In one embodiment, leads 113 are spaced apart from mounting
board 111 and surround mounting board 111. In one embodiment, lower
surfaces (for example, surfaces that will be exposed within the
package body) of leads 113 are positioned generally on the same
plane as the lower surface (for example, the surface that will be
exposed within the package body) of mounting board 111. In one
embodiment, leads 113 are configured to include first regions 113a
and second regions 113b extending from first regions 113a in a
direction away from mounting board 111 (or semiconductor die 120 if
mounting board 111 is not used). In one embodiment and as generally
illustrated in FIG. 6B, first regions 113a can have a thinner
profile or a cross-section that is smaller than that of second
regions 113b in thickness, but aspects of the present embodiment
are not limited thereto. Lead frame 110 can be made of one or more
conductive materials, such as alloys of copper (Cu), nickel (Ni) or
iron (Fe), or other materials as known to those of ordinary skill
in the art.
[0040] As illustrated in FIGS. 5, 6C and 6D, in step S20,
semiconductor die 120, which includes bond pads 121, can be mounted
on or attached directly or indirectly to lead frame 110. In one
embodiment, semiconductor die 120 is connected to the lead frame
110 such that the surface thereof having bond pads 121 formed
thereon faces mounting board 111 and first regions 113a of leads
113. In one embodiment, semiconductor die 120 can be attached to
mounting board 111 by an adhesive layer. In one embodiment, first
regions 113a are brought into contact with edge regions of
semiconductor die 120 on the same surface as bond pads 121. In one
embodiment, semiconductor die 120 is larger than the mounting board
111 in size, but aspects of the present embodiment are not limited
thereto. In one embodiment, bond pads 121 and first regions 113a of
leads 113 are spaced apart from each other. In alternative
embodiment, bond pads 121 and first regions 113a of leads 113 can
overlap and make contact at least in part with each other.
[0041] As illustrated in FIGS. 5 and 6E, in step S30, semiconductor
die 120 and leads 113 are connected to each other using conductive
layer 130. In one embodiment, conductive layer 130 is formed by
electroplating or plating lead frame 110 having semiconductor die
120 mounted thereon using a conductive plating solution, such as a
copper (Cu) plating solution. In one embodiment, a copper sulfate
solution can be used. In one embodiment, conductive layer 130 is
formed to surround, overlap, conform to, adjoin, or cover outer or
exposed surfaces of leads 113 and bond pads 121 thereby
electrically connecting them together. In one embodiment, because
side portions of second regions 113a of leads 113 are connected to
another lead by lead frame 110, conductive layer 130 is formed on
leads 113 except for the side portions thereof. In one embodiment,
conductive layer 130 can be formed on outer or exposed surfaces of
mounting board 111.
[0042] As illustrated in FIGS. 5 and 6F, in step S40, mounting
board 111, leads 113 and semiconductor die 120 can be encapsulated
using encapsulant 140 to form a package body. In one embodiment,
side and bottom surfaces of lead 113 and bottom surface of mounting
board 111 are exposed through or within encapsulant 140 (that is,
not covered by encapsulant 140). In one embodiment, encapsulant 140
can be formed to encapsulate the structure from proximate to the
bottom surface of second regions 113b towards the direction of the
top surface of semiconductor die 120. In one embodiment,
encapsulant 140 entirely covers the top and lateral surfaces of
semiconductor die 120. In an alternative embodiment, the back
surface (that is, the surface opposite to bond pads 121) can be
exposed within encapsulant 140.
[0043] As illustrated in FIGS. 5 and 6G, in step S50, singulation
is performed to form an individual semiconductor device 100 by
cutting the side portions of leads 113 or lead frame 110 exposed by
encapsulant 140. In one embodiment, the side portions of leads 113
or lead frame 110 exposed by encapsulant 140 can be singulated,
thereby completing a single semiconductor device 100 from lead
frame 110.
[0044] In the method of fabricating semiconductor device 100
according to the present embodiment, conductive layer 130 is formed
to electrically connect leads 113 to semiconductor die 120. In one
embodiment, conductive layer 130 is formed as a plating layer on
certain outer surfaces of semiconductor device 100 to surround,
overlap, or cover portions of leads 113 and bond pads 121 of
semiconductor die 120, thereby electrically connecting leads 113 to
bond pads 121. This provides, a conductive connection structure
between leads 113 and bond pads 121 that can be achieved using
existing plating processes or other processes. Also, because
additional assembly elements, such as wire bonds, are not required
to connect leads 113 to bond pads 121, fabricating costs can be
reduced, reliability can be increased, and the thickness of the
electronic package can be reduced. Further, because conductive
layer 130 is formed directly on the outer surfaces of leads 113 and
bond pads 121, semiconductor die 120 can be more easily sealed
using encapsulant 140.
[0045] FIGS. 7A to 7C illustrate cross-sectional views of an
electronic device (for example, semiconductor device 200) at
various stages of fabrication in accordance with another
embodiment. By way of example, a method for fabricating
semiconductor device 200 will be described with reference to FIGS.
7A to 7C together with FIG. 5. As illustrated in FIG. 5, the
fabrication of semiconductor device 200 can be performed in
substantially the same manner as in the previous embodiment up to
step S20. In the present embodiment, the lead frame is illustrated
without a mounting board and a tie bar. It is understood that,
similar to the previous embodiment, the lead frame can include a
mounting board and one or more tie bars.
[0046] As illustrated in FIGS. 5 and 7A, in step S30, semiconductor
die 120 and leads 113 are electrically connected to each other
using conductive layer 230, which in the present embodiment can be
a solder material. In one embodiment, conductive layer 230 can
formed by coating a solder paste on first regions 113a of leads 113
and bond pads 121 and subjecting the resulting structure to a
reflow process at a temperature ranging from about 150 degrees
Celsius to about 200 degrees Celsius. In one embodiment, the solder
paste is applied with the leadframe having semiconductor die 120
facing upward in order to better control the application of the
solder paste. In one embodiment, conductive layer 230 covers or
overlaps first regions 113a and bond pads 121, thereby electrically
connecting leads 113 to semiconductor die 120.
[0047] As illustrated in FIGS. 5 and 7B, in step S40, semiconductor
die 120 and at least portions of leads 113 are encapsulated using
encapsulant 140 to form a package body. In one embodiment,
encapsulant 140 is configured so as to expose side portions of
leads 113. In one embodiment, encapsulant 140 can be formed to
expose side and bottom portions of the lead 113. In one embodiment,
encapsulant 140 is formed to encapsulate from proximate to the
bottom surface of second regions 113b towards the direction of the
top surface of semiconductor die 120 while exposing the side and
bottom portions of second regions 113b. In one embodiment,
encapsulant 140 entirely covers the top and lateral surfaces of
semiconductor die 120. In an alternative embodiment, the back
surface of semiconductor die 120 (that is, the surface opposite to
bond pads 121) can be exposed within encapsulant 140.
[0048] As illustrated in FIGS. 5 and 7C, in step S50, singulation
of an individual semiconductor device 200 is performed by cutting
the side portions of leads 113 exposed by encapsulant 140. In one
embodiment, the side portions of leads 113 or lead frame 110
exposed by encapsulant 140 can be singulated, thereby completing a
single semiconductor device 200 from lead frame 110.
[0049] In the method of fabricating semiconductor device 200
according to the present embodiment, conductive layer 230 including
a solder layer is formed to electrically connect leads 113 to
semiconductor die 120. In one embodiment, conductive layer 230 is
formed as a solder layer on certain outer surfaces of semiconductor
device 200 to surround, overlap, or cover portions of leads 113 and
bond pads 121 of semiconductor die 120, thereby electrically
connecting leads 113 to bond pads 121. This provides, a conductive
connection structure between leads 113 and bond pads 121 that can
be achieved using existing or other solder processes. Also, because
additional assembly elements, such as wire bonds, are not required
to connect leads 113 to bond pads 121, fabricating costs can be
reduced and reliability can be increased. Further, because
conductive layer 230 is formed directly on the outer surfaces of
leads 113 and bond pads 121, semiconductor die 120 can be more
easily sealed using encapsulant 140.
[0050] FIG. 8A to 8E illustrate cross-sectional views and bottom
views of an electronic device (for example, semiconductor device
300) at various stages of fabrication in accordance with a further
embodiment. By way of example, a method for fabricating
semiconductor device 300 will be described with reference to FIGS.
8A to 8E together with FIG. 5. As illustrated in FIG. 5, the
fabrication of semiconductor device 300 can be performed in
substantially the same manner as in the previous embodiment up to
step S10. In the present embodiment, the lead frame is illustrated
without a mounting board and a tie bar. It is understood that,
similar to the first embodiment, the lead frame can include a
mounting board and one or more tie bars. In semiconductor device
300 leads 313 are configured to include first regions 313a, second
regions 313b, and holes 314 formed in, for example, first regions
313a.
[0051] As illustrated in FIGS. 5, 8A and 8B, in step S20,
semiconductor die 120, which includes a plurality of bond pads 121,
can be mounted on leads 313. In one embodiment, second regions 313b
extend from first regions 313a in a direction away from
semiconductor die 120. In one embodiment and as generally
illustrated in FIG. 8A, first regions 313a can have a thinner
profile or a cross-section that is smaller than that of second
regions 113b in thickness, but aspects of the present embodiment
are not limited thereto. In accordance with the present embodiment,
holes 314 can be formed in leads 313 at locations corresponding to
the location of bond pads 121 on semiconductor die 120. In one
embodiment, holes 314 are in first regions 313a.
[0052] In one embodiment, semiconductor die 120 is connected to
leads 313 such that the surface of semiconductor die 120 that
includes bond pads 121 is adjacent to and faces leads 313. In one
embodiment, one surface of semiconductor die 120 is brought into
contact with first regions 313a of leads 313 with bond pads 121
exposed, framed, or surrounded by holes 314 within first regions
313a. In one embodiment, semiconductor die 120 is connected to
leads 313 such that bond pads 121 are positioned within holes 314
as generally illustrated in FIG. 8B. In one embodiment, bond pads
121 and first regions 313a are spaced apart from each other. In
another embodiment, bond pads 121 and first regions 313a can
overlap and can be in contact (at least in part) with each other by
reducing, for example, the width of holes 314.
[0053] As illustrated in FIGS. 5 and 8C, in step S30, bond pads 121
and leads 113 are connected to each other using a conductive layer
330, which in the present embodiment can be a solder material. In
one embodiment, conductive layer 330 can be formed by coating a
solder paste on first regions 313a of leads 313 within holes 314
and subjecting the resulting structure to a reflow process at a
temperature ranging from about 150 degrees Celsius to about 200
degrees Celsius. In one embodiment, the solder paste is applied
with the leadframe having semiconductor die 120 facing upward in
order to better control the application of the solder paste. In one
embodiment, solder 330 covers or overlaps first regions 313a and
bond pads 121, thereby electrically connecting leads 313 to
semiconductor die 120.
[0054] As illustrated in FIGS. 5 and 8D, in step S40, semiconductor
die 120 and at least portions of leads 313 are encapsulated using
the encapsulant 140 to provide a package body. In one embodiment,
encapsulant 140 is configured so as to expose side portions of
leads 313. In one embodiment, encapsulant 140 can be formed to
expose side and bottom portions of the lead 313. In one embodiment,
encapsulant 140 is formed to encapsulate from proximate to the
bottom surface of second regions 313b towards the direction of the
top surface of semiconductor die 120 while exposing the side and
bottom portions of second regions 313b. In one embodiment,
encapsulant 140 entirely covers the top and lateral surfaces of
semiconductor die 120. In an alternative embodiment, the back
surface of semiconductor die 120 (that is, the surface opposite to
bond pads 121) can be exposed within encapsulant 140.
[0055] As illustrated in FIGS. 5 and 8E, in step S50, singulation
of an individual semiconductor device 300 is performed by cutting
the side portions of leads 313 exposed by encapsulant 140. In one
embodiment, the side portions of leads 313 or lead frame 110
exposed by encapsulant 140 can be singulated, thereby completing a
single semiconductor device 300 from the lead frame.
[0056] In the method of fabricating semiconductor device 300
according to the present embodiment, conductive layer 330 is formed
to electrically connect leads 313 to semiconductor die 120. In one
embodiment, conductive layer 330 is formed as a solder layer on
certain outer surfaces of semiconductor device 300 to surround,
overlap, or cover portions of leads 313 and bond pads 121 of
semiconductor die 120, thereby electrically connecting leads 313 to
semiconductor die 120. This provides, a conductive connection
structure between leads 313 and bond pads 121 that can be achieved
using existing or other solder processes. Also, because additional
assembly elements, such as wire bonds, are not required to connect
leads 313 to bond pads 121, fabricating costs can be reduced and
reliability can be increased. In addition, bond pads 121 can be
positioned within holes 314 and holes 314 can be filled with
conductive layer 330, thereby more accurately achieving the
conductive connective structure between leads 313 and bond pads
121, which can also improve reliability. Further, because
conductive layer 330 is formed to cover holes 314 within first
regions 313a, semiconductor die 120 can be more easily sealed by
encapsulant 140.
[0057] FIGS. 9A to 9C illustrate cross-sectional views of an
electronic device (for example, semiconductor device 400) at
various stages of fabrication in accordance with a still further
embodiment. By way of example, a method for fabricating
semiconductor device 400 will be described with reference to FIGS.
9A to 9C together with FIG. 5. As illustrated in FIG. 5,
semiconductor device 400 can be fabricated in a similar manner as
semiconductor device 300 up to step S20. In the present embodiment,
lead frame 110 is illustrated without a mounting board and a tie
bar. It is understood that, similar to the first embodiment, lead
frame 110 can include a mounting board and one or more tie
bars.
[0058] As illustrated in FIGS. 5 and 9A, in step S30, bond pads 121
and leads 313 can be connected to each other using conductive layer
430, which in the present embodiment can be a plated conductive
layer. In one embodiment, conductive layer 430 can be formed by
electroplating or plating lead frame 110 having semiconductor die
120 mounted thereon using a conductive plating solution, such as a
copper (Cu) plating solution. In one embodiment, a copper sulfate
solution can be used. In one embodiment, conductive layer 430 is
formed to surround, overlap, conform to, adjoin, or cover outer or
exposed surfaces of leads 113 and bond pads 121 thereby
electrically connecting them together. In one embodiment,
conductive layer 430 is formed to surround or fill holes 314 in
leads 313 in which bond pads 121 are positioned. In one embodiment,
because side portions of leads 313 are connected to another lead by
lead frame 110, conductive layer 430 is formed on leads 313 except
for the side portions thereof. In accordance with the present
embodiment, bond pads 121 and leads 313 are electrically connected
to each other by conductive layer 430.
[0059] As illustrated in FIGS. 5 and 9B, in step S40, leads 313 and
semiconductor die 120 are encapsulated using encapsulant 140 to
form a package body. In one embodiment, side and bottom surfaces of
lead 313 are exposed through or within encapsulant 140. In one
embodiment, encapsulant 140 can be formed to encapsulate the
structure from proximate to the bottom surface of second regions
313b towards the direction of the top surface of semiconductor die
120. In one embodiment, encapsulant 140 entirely covers the top and
lateral surfaces of semiconductor die 120. In an alternative
embodiment, the back surface (that is, the surface opposite to bond
pads 121) can be exposed within encapsulant 140.
[0060] As illustrated in FIGS. 5 and 9C, in step S50, singulation
is performed to form an individual semiconductor device 400 by
cutting the side portions of leads 313 exposed by encapsulant 140.
In one embodiment, the side portions of leads 313 or lead frame 110
exposed by encapsulant 140 can be singulated, thereby completing a
single semiconductor device 400 from the lead frame.
[0061] In the method of fabricating semiconductor device 400
according to the present embodiment, conductive layer 430 is formed
to electrically connect leads 313 to semiconductor die 120. In one
embodiment, conductive layer 430 is formed as a plated layer on
certain outer surfaces of semiconductor device 400 to surround,
overlap, or cover portions of leads 313 and bond pads 121 of
semiconductor die 120, thereby electrically connecting leads 313 to
bond pads 121. This provides, a conductive connection structure
between leads 313 and bond pads 121 that can be achieved using
existing or other plating processes. Also, because additional
assembly elements, such as wire bonds, are not required to connect
leads 313 to bond pads 121, fabricating costs can be reduced and
reliability can be increased. In addition, because bond pads 121
are positioned within holes 314 and conductive layer 430 is formed
to surround holes 314, outer surfaces of bond pads 121, and leads
313, the conductive connective structure between leads 313 and bond
pads 121 can be performed more accurately, which can also improve
reliability. Further, because conductive layer 430 is fixedly
formed on the outer surfaces of leads 313 and bond pads 121,
semiconductor die 120 can be easily sealed by encapsulant 140.
[0062] From all of the foregoing, one skilled in the art can
determine that, according to an embodiment, an electronic device
(for example, elements 100, 200, 300, 400) comprises an electronic
die (for example, element 120) including a conductive pad (for
example, element 121) on a major surface. A lead (for example,
elements 113, 313) includes a first region (for example, elements
113a, 313a) in spaced relationship with the electronic die and a
second region (for example, elements 113b, 313b) extending from the
first region in a direction away from the electronic die. A
conductive layer (for example, elements 130, 230, 330, 430)
overlaps the conductive pad and the lead thereby electrically
connecting the conductive pad to the lead. A package body (for
example, element 140) covering the electronic die and at least
portions of lead.
[0063] In one embodiment of the foregoing device, a mounting board
(for example, element 111) can be positioned on the same plane as
the lead and can be spaced apart from the lead. In another
embodiment, the mounting board can be surrounded by a plurality of
leads. In a further embodiment the conductive pad can contact the
lead. In a still further embodiment, the conductive layer is a
plating layer (for example, elements 130, 430) that surrounds
conductive pad and at least portions of the lead. In yet a further
embodiment, an outer lateral surface of the lead is absent plated
material. In another embodiment, the conductive layer can be a
solder layer (for example, elements 230, 330) covering the
conductive pad and a hole (for example, element 314) in the first
region. In a further embodiment, the conductive layer can be a
solder material covering the conductive pad and the hole. In a
still further embodiment, the conductive layer can be a plated
material covering the conductive pad and at least portions of the
lead. In yet a further embodiment, the package body can entirely
encapsulate the electronic die.
[0064] From all of the foregoing, one skilled in the art can
determine that, according to an additional embodiment, an
electronic package device (for example, elements 100, 200, 300,
400) comprises an electronic die (for example, element 120) having
a plurality of conductive pads (for example, element 121) on a
major surface. A plurality of leads (for example, elements 113,
313), each lead being in spaced relationship with the major
surface. A conductive layer (for example, elements 130, 230, 330,
430) covers each conductive pad and at least a portion of each
lead. A package body (for example, element 140) encapsulates at
least portions of the electronic die and at least portions of the
plurality of leads.
[0065] From all of the foregoing, one skilled in the art can
determine that, according to a further embodiment, a method for
forming an electronic device (for example, elements 100, 200, 300,
400) includes providing a lead frame (for example, element 110)
including a plurality of leads (for example, elements 113, 313),
the plurality of leads each having a first region (for example,
elements 113a, 313a) and a second region (for example, elements
113b, 313b) extending from the first region. The method includes
attaching an electronic die (for example, element 120) including a
plurality of conductive pads (for example, element 121) on a major
surface to the lead frame. The method includes forming a conductive
layer (for example, elements 130, 230, 330, 430) to connect the
conductive pads to the leads and encapsulating the electronic die
and at least portions of the leads and with an encapsulant (for
example, element 140).
[0066] In one embodiment of the foregoing method, the method can
further include mounting the electronic die to a mounting board
(for example, element 111). In another embodiment, the method can
include attaching the conductive pads to the leads. In a further
embodiment, forming the conductive layer can include plating the
conductive layer in a copper plating solution. In a still further
embodiment, forming the conductive layer can include plating the
conductive layer to surround the conductive pads and at least
portions of the leads. In yet a further embodiment, forming the
conductive layer can include forming a solder layer covering the
conductive pads and at least portions of the leads. In another
embodiment, attaching the electronic die can include placing the
conductive pads within windows (for example, element 314) and
covering the windows with a solder layer or a plated layer. In a
further embodiment, encapsulating the electronic die includes
forming a package body that encapsulates from a bottom surface of
the second region towards a direction of a top surface of the
electronic die and entirely covering the electronic die.
[0067] In view of all the above, it is evident that a novel
structure and method are disclosed. Included, among other features,
is an electronic die having bond pads on at least one surface. The
one surface is attached to or proximate to a plurality of leads. A
conductive layer overlaps or covers the bond pads and at least
portions of the leads thereby electrically connective the leads to
the electronic die. The conductive layer provides a simplified,
cost effective, and more reliable conductive connective structure.
Additionally, the conductive layer provides a conductive connective
structure with a lower profile compared to previous connective
structures.
[0068] While the subject matter of the invention is described with
specific preferred embodiments and example embodiments, the
foregoing drawings and descriptions thereof depict only typical
embodiments of the subject matter and are not, therefore, to be
considered limiting of its scope. It is evident that many
alternatives and variations will be apparent to those skilled in
the art. For example, the conductive layer can be formed by other
processes, such as sputtering, chemical vapor deposition, or
evaporation processes.
[0069] As the claims hereinafter reflect, inventive aspects may lie
in less than all features of a single foregoing disclosed
embodiment. Thus, the hereinafter expressed claims are hereby
expressly incorporated into this Detailed Description of the
Drawings, with each claim standing on its own as a separate
embodiment of the invention. Furthermore, while some embodiments
described herein include some but not other features included in
other embodiments, combinations of features of different
embodiments are meant to be within the scope of the invention and
form different embodiments, as would be understood by those skilled
in the art.
* * * * *