U.S. patent application number 14/015559 was filed with the patent office on 2014-08-21 for mim capacitor in finfet structure.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Veeraraghavan S. Basker, Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh.
Application Number | 20140231891 14/015559 |
Document ID | / |
Family ID | 51350592 |
Filed Date | 2014-08-21 |
United States Patent
Application |
20140231891 |
Kind Code |
A1 |
Basker; Veeraraghavan S. ;
et al. |
August 21, 2014 |
MIM CAPACITOR IN FINFET STRUCTURE
Abstract
A FinFET structure which includes: silicon fins on a
semiconductor substrate, each silicon fin having two sides and a
horizontal surface; sequential layers of a first layer of titanium
nitride, a dielectric layer and a second layer of titanium nitride
on the sides and horizontal surface of the silicon fins; a
polysilicon gate layer over the second layer of titanium nitride on
the silicon fins and over the semiconductor substrate such that
first and second ends of the silicon fins protrude from the
polysilicon layer; spacers adjacent to the polysilicon gate layer;
epitaxial silicon over the first and second ends of the silicon
fins to form sources and drains, wherein the combination of the
first layer of titanium nitride, dielectric layer and second layer
of titanium nitride forms a metal-insulator-metal capacitor
situated between each silicon fin and the polysilicon layer.
Inventors: |
Basker; Veeraraghavan S.;
(Schenectady, NY) ; Leobandung; Effendi;
(Wappingers Falls, NY) ; Yamashita; Tenko;
(Schenectady, NY) ; Yeh; Chun-Chen; (Clifton Park,
NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
51350592 |
Appl. No.: |
14/015559 |
Filed: |
August 30, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13768248 |
Feb 15, 2013 |
|
|
|
14015559 |
|
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|
|
Current U.S.
Class: |
257/296 |
Current CPC
Class: |
H01L 27/1211 20130101;
H01L 27/0629 20130101; H01L 29/785 20130101; H01L 28/40 20130101;
H01L 21/845 20130101; H01L 29/66795 20130101 |
Class at
Publication: |
257/296 |
International
Class: |
H01L 27/06 20060101
H01L027/06; H01L 29/78 20060101 H01L029/78 |
Claims
1. A FinFET structure comprising: silicon fins on a semiconductor
substrate, each silicon fin having two sides and a horizontal
surface; sequential layers of a first layer of titanium nitride, a
dielectric layer and a second layer of titanium nitride on the
sides and horizontal surface of the silicon fins; a polysilicon
gate layer over the second layer of titanium nitride on the silicon
fins and over the semiconductor substrate such that first and
second ends of the silicon fins protrude from the polysilicon
layer, the polysilicon layer having a surface that faces each of
the first and second ends of the silicon fins; a spacer over each
of the two surfaces and a portion of the first and second ends of
the silicon fins such that the first and second ends of the silicon
fins protrude from the spacers; epitaxial silicon over the first
and second ends of the silicon fins to form sources and drains,
wherein the combination of the first layer of titanium nitride,
dielectric layer and second layer of titanium nitride forms a
metal-insulator-metal capacitor situated between each silicon fin
and the polysilicon layer.
2. The FinFET structure of claim 1 wherein the dielectric layer
comprises a material that is a high dielectric constant material
selected from the group consisting of hafnium oxide (HfO.sub.2),
aluminum oxide (Al.sub.2O.sub.3) and lanthanum oxide
(La.sub.2O.sub.3).
3. The FinFET structure of claim 1 further comprising epitaxial
silicon between the silicon fins and in contact with the epitaxial
silicon over the first and second ends of the silicon fins to form
merged sources and drains that connect adjacent sources and drains,
respectively.
4. The FinFET structure of claim 1 wherein the silicon fins and
polysilicon layer are doped.
5. The FinFET structure of claim 4 wherein the doped fins and doped
polysilicon are highly doped to a dopant level of 5.times.10.sup.20
to 1.times.10.sup.21 atoms/cm.sup.3.
6. The FinFET structure of claim 1 wherein the first and second
layers of titanium nitride have a thickness of 5 to 10 nanometers
(nm.) and the dielectric layer has a thickness of 2 to 5 nm.
7. The FinFET structure of claim 1 wherein the first and second
ends of the silicon fins that protrude from the polysilicon gate
layer are devoid of the sequential layers of the first layer of
titanium nitride, the dielectric layer and the second layer of
titanium nitride.
8. A FinFET structure comprising: silicon fins on a semiconductor
substrate, each silicon fin having two sides and a horizontal
surface; a metal-insulator-metal capacitor on the sides and
horizontal surface of the silicon fins comprising sequential layers
of a first layer of titanium nitride, a dielectric layer and a
second layer of titanium nitride on the sides and horizontal
surface of the silicon fins; a polysilicon gate layer over the
second layer of titanium nitride on the silicon fins and over the
semiconductor substrate such that first and second ends of the
silicon fins protrude from the polysilicon layer such that the
first and second ends of the silicon fins that protrude from the
polysilicon gate layer are devoid of the sequential layers of the
first layer of titanium nitride, the dielectric layer and the
second layer of titanium nitride, the polysilicon gate layer having
a surface that faces each of the first and second ends of the
silicon fins; a spacer over each of the two surfaces and a portion
of the first and second ends of the silicon fins such that the
first and second ends of the silicon fins protrude from the
spacers; and epitaxial silicon over the first and second ends of
the silicon fins to form sources and drains.
9. The FinFET structure of claim 8 wherein the dielectric layer
comprises a material that is a high dielectric constant material
selected from the group consisting of hafnium oxide (HfO.sub.2),
aluminum oxide (Al.sub.2O.sub.3) and lanthanum oxide
(La.sub.2O.sub.3).
10. The FinFET structure of claim 8 further comprising epitaxial
silicon between the silicon fins and in contact with the epitaxial
silicon over the first and second ends of the silicon fins to form
merged sources and drains that connect adjacent sources and drains,
respectively.
11. The FinFET structure of claim 8 wherein the silicon fins and
polysilicon layer are doped.
12. The FinFET structure of claim 11 wherein the doped fins and
doped polysilicon are highly doped to a dopant level of
5.times.10.sup.20 to 1.times.10.sup.21 atoms/cm.sup.3.
13. The FinFET structure of claim 8 wherein the first and second
layers of titanium nitride have a thickness of 5 to 10 nanometers
(nm.) and the dielectric layer has a thickness of 2 to 5 nm.
Description
RELATED APPLICATION
[0001] This application is a continuation of U.S. patent
application Ser. No. 13/768,248 (Attorney docket No.
YOR920120142US1), entitled "MIM CAPACITOR IN FINFET STRUCTURE",
filed Feb. 15, 2013, the disclosure of which is incorporated by
reference herein.
BACKGROUND
[0002] The present invention relates to FinFET structures and, more
particularly, relates to a metal-insulator-metal capacitor
fabrication process in a FinFET structure.
[0003] Semiconductor circuits typically include both active
semiconductor devices, such as but not limited to transistors and
diodes, as well as passive devices, such as but not limited to
resistors and capacitors. As semiconductor technology has advanced
over several decades, both the active semiconductor devices and the
passive devices have conventionally been scaled to increasingly
smaller dimensions to reduce costs.
[0004] Capacitors are one of the fundamental components in today's
electronic devices and operate by storing a charge. For example,
capacitors are often used in dynamic random access memory (DRAM)
and other similar devices.
[0005] FinFET devices and FinFET structures are nonplanar devices
and structures typically built on a semiconductor on insulator
(SOI) substrate. The FinFET devices may comprise a vertical
semiconductor fin, rather than a planar semiconductor surface,
having a single or double gate wrapped around the fin. In an effort
to provide for continued scaling of semiconductor structures to
continuously smaller dimensions while maintaining or enhancing
semiconductor device performance, the design and fabrication of
semiconductor fin devices and semiconductor fin structures has
evolved within the semiconductor fabrication art.
BRIEF SUMMARY
[0006] The various advantages and purposes of the exemplary
embodiments as described above and hereafter are achieved by
providing, according to a first aspect of the exemplary
embodiments, a a FinFET structure which includes silicon fins on a
semiconductor substrate, each silicon fin having two sides and a
horizontal surface; sequential layers of a first layer of titanium
nitride, a dielectric layer and a second layer of titanium nitride
on the sides and horizontal surface of the silicon fins; a
polysilicon gate layer over the second layer of titanium nitride on
the silicon fins and over the semiconductor substrate such that
first and second ends of the silicon fins protrude from the
polysilicon layer, the polysilicon layer having a surface that
faces each of the first and second ends of the silicon fins; a
spacer over each of the two surfaces and a portion of the first and
second ends of the silicon fins such that the first and second ends
of the silicon fins protrude from the spacers; epitaxial silicon
over the first and second ends of the silicon fins to form sources
and drains, wherein the combination of the first layer of titanium
nitride, dielectric layer and second layer of titanium nitride
forms a metal-insulator-metal capacitor situated between each
silicon fin and the polysilicon layer.
[0007] According to a second aspect of the exemplary embodiments,
there is provided a FinFET structure which includes: silicon fins
on a semiconductor substrate, each silicon fin having two sides and
a horizontal surface; a metal-insulator-metal capacitor on the
sides and horizontal surface of the silicon fins comprising
sequential layers of a first layer of titanium nitride, a
dielectric layer and a second layer of titanium nitride on the
sides and horizontal surface of the silicon fins; a polysilicon
gate layer over the second layer of titanium nitride on the silicon
fins and over the semiconductor substrate such that first and
second ends of the silicon fins protrude from the polysilicon layer
such that the first and second ends of the silicon fins that
protrude from the polysilicon gate layer are devoid of the
sequential layers of the first layer of titanium nitride, the
dielectric layer and the second layer of titanium nitride, the
polysilicon gate layer having a surface that faces each of the
first and second ends of the silicon fins; a spacer over each of
the two surfaces and a portion of the first and second ends of the
silicon fins such that the first and second ends of the silicon
fins protrude from the spacers; and epitaxial silicon over the
first and second ends of the silicon fins to form sources and
drains.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0008] The features of the exemplary embodiments believed to be
novel and the elements characteristic of the exemplary embodiments
are set forth with particularity in the appended claims. The
Figures are for illustration purposes only and are not drawn to
scale. The exemplary embodiments, both as to organization and
method of operation, may best be understood by reference to the
detailed description which follows taken in conjunction with the
accompanying drawings in which:
[0009] FIGS. 1A to 1H illustrate a process for forming fins on a
semiconductor substrate wherein:
[0010] FIG. 1A illustrates a starting structure including a
semiconductor on insulator (SOI) substrate, an oxide layer, an
amorphous silicon layer and a hard mask layer;
[0011] FIG. 1B illustrates the patterning of the amorphous silicon
layer and the hard mask layer;
[0012] FIG. 1C illustrates the removal of the hard mask layer,
leaving only stripes of amorphous silicon;
[0013] FIG. 1D illustrates the deposition of a conformal layer of
nitride;
[0014] FIG. 1E illustrates the etching of the nitride to form
sidewall spacers;
[0015] FIG. 1F illustrates the etching of the stripes of amorphous
silicon to leave only the sidewall spacers;
[0016] FIG. 1G illustrates the etching of the oxide layer and the
silicon layer of the SOI substrate using the sidewall spacers as a
mask to result in stripes of oxide on silicon fins; and
[0017] FIG. 1H illustrates the etching of the sidewall spacers and
the oxide stripes to result in silicon fins.
[0018] FIGS. 2A and 2B illustrate a starting structure of the
exemplary embodiments which include fins on a semiconductor
substrate.
[0019] FIGS. 3A and 3B illustrate forming sequential layers of a
first titanium nitride, a dielectric and a second titanium nitride
on the fins.
[0020] FIGS. 4A and 4B illustrate a next step of depositing a
polysilicon layer.
[0021] FIGS. 5A and 5B illustrate etching back the polysilicon
layer and sequential layers of a first titanium nitride, a
dielectric and a second titanium nitride from ends of the fins.
[0022] FIGS. 6A and 6B illustrate the forming of a spacer on the
polysilicon layer and portions of the ends of the fins.
[0023] FIG. 7 is a perspective view of the structure shown in FIGS.
6A and 6B.
[0024] FIGS. 8A and 8B illustrate the formation of epitaxial
silicon on the ends of the fins to form a merged source and merged
drain.
[0025] FIG. 9 is a perspective view of the structure shown in FIG.
8A and 8B.
DETAILED DESCRIPTION
[0026] Referring to the Figures in more detail, and particularly
referring to FIGS. 1A to 1H, there is illustrated a preferred
process for forming a semiconductor substrate having fins for
practicing the exemplary embodiments. The preferred process may be
referred to as the sidewall image transfer process.
[0027] In FIG. 1A, the process begins with a semiconductor on
insulator (SOI) substrate 102, also frequently referred to as a
silicon on insulator substrate. The SOI substrate 102 may comprise
a semiconductor base 104 (usually silicon but may be other
semiconductor materials), a dielectric layer 106, usually an oxide
layer (may also be called a buried oxide or BOX layer), and a
semiconductor material 108, which is usually silicon. For the
purposes of the present exemplary embodiments, it is preferred that
semiconductor material 108 is silicon and will be referred to as
such in the discussion that follows. On top of silicon 108 is an
oxide layer 110, followed by an amorphous silicon layer 112 and
hard mask layer 114, usually a nitride. Not shown in FIG. 1A are
photoresist and other layers which may be used to pattern the hard
mask layer 114.
[0028] Referring now to FIG. 1 B, the hard mask layer 114 has been
patterned and etched down through the amorphous silicon layer 112,
stopping on the oxide layer 110.
[0029] Referring now to FIG. 1C, the hard mask layer 114 has been
conventionally stripped, leaving only stripes of amorphous silicon
112. Shown in FIG. 1C are only the ends of the stripes of amorphous
silicon 112 which run perpendicular to the page.
[0030] Thereafter, a conformal layer of nitride 116 is deposited
over the stripes of amorphous silicon 112, as shown in FIG. 1D.
[0031] The conformal layer of nitride 116 is conventionally etched
to form sidewall spacers 118, as shown in FIG. 1E, followed by
conventionally etching the stripes of amorphous silicon 112 to
result in only the spacers 118 left on the surface of oxide layer
110, as shown in FIG. 1F.
[0032] Using the spacers 118 as a mask, the substrate is etched to
form fins 120 and stripes of oxide 122 on the fins 120 as shown in
FIG. 1G.
[0033] Referring now to FIG. 1H, the spacers 118 and stripes of
oxide 122 are conventionally etched to result in fins 120 on BOX
layer 106.
[0034] In the description of FIGS. 2A to 6A and 2B to 6B that
follows, the "A" Figure is a plan view of the FinFET structure as
it is being processed and the "B" Figure is a cross-section view of
the "A" Figure in the direction of the arrows B-B. FIG. 8A is a
plan view of the FinFET structure as it is being processed and FIG.
8B is a side view of FIG. 8A
[0035] Referring now to FIGS. 2A and 2B, there is shown a FinFET
structure 200 that starts with the structure shown in FIG. 1H
comprising a semiconductor material 202, a BOX layer 204 and
silicon fins 206. The silicon material is preferably uniformly
doped along the length of the silicon fins 206, most preferably
highly doped to a dopant level of about 5.times.10.sup.20 to
1.times.10.sup.21 atoms/cm.sup.3. The silicon material may be doped
by ion implantation or in-situ doped amorphous silicon deposition.
The dopants may be, for example, arsenic or boron.
[0036] A metal-insulator-metal (MIM) capacitor now may be
fabricated upon the silicon fins 206.
[0037] Referring now to FIGS. 3A and 3B, sequential layers are
deposited over the silicon fins 206 that will form the basis of the
MIM capacitor. A first layer of titanium nitride 208 is deposited
over the silicon fins 206, followed by a dielectric layer 210 and a
second layer of titanium nitride 212. The layers of first layer of
titanium nitride 208, dielectric layer 210 and second layer of
titanium nitride 212 may be deposited by atomic layer deposition
(ALD) to achieve conformal film deposition from the top of the
silicon fins 206 to the bottom of the silicon fins 206. The first
titanium nitride layer 208 may have a thickness of about 5 to 10
nanometers (nm), the dielectric layer 210 may have a thickness of
about 2 to 5 nm and the second titanium nitride layer 212 may have
a thickness of about 5 nm. For the sake of clarity, the first
titanium nitride layer 208 and dielectric layer 210 are not shown
in FIG. 3A and subsequent plan views. The dielectric layer 210 is
preferably a high-k (high dielectric constant) material in order to
enhance the dielectric constant and lower the gate tunneling
current. Some examples of suitable high-k dielectric materials may
be hafnium oxide (HfO.sub.2), aluminum oxide (Al.sub.2O.sub.3) and
lanthanum oxide (La.sub.2O.sub.3).
[0038] As shown in FIGS. 4A and 4B, a polysilicon gate layer 214
has been deposited over and around the silicon fins 206 having the
first layer of titanium nitride 208, dielectric layer 210 and
second layer of titanium nitride 212. The polysilicon gate layer
214 is preferably doped, most preferably highly doped to a dopant
level of about 5.times.10.sup.20 to 1.times.10.sup.21
atoms/cm.sup.3. The polysilicon layer may be deposited by a process
such as low pressure chemical vapor deposition (LPCVD). After
deposition, it may be doped by ion implantation with dopants such
as arsenic or boron.
[0039] Highly doped silicon for the silicon fins 206 and highly
doped polysilicon for the polysilicon gate layer 214 are preferred
to achieve adequate frequency response and to minimize capacitor
resistance.
[0040] In a next step, as shown in FIGS. 5A and 5B, polysilicon
gate layer 214 is etched back to expose the layered fins 206, 208,
210, 212. The polysilicon gate layer 214 may be etched by high
density plasma with chlorine-based chemistry. Precursors in the
plasma may include Cl.sub.2, CF.sub.4, CHF.sub.3, HBr and
SiF.sub.6.The etching of the polysilicon gate layer 214 is followed
by etching of the exposed second layer of titanium nitride 212,
dielectric layer 210 and first layer of titanium nitride 208 off of
the silicon fins 206. The etching of the exposed second layer of
titanium nitride 212, dielectric layer 210 and first layer of
titanium nitride 208 off of the silicon fins 206 may be also by
high density plasma with chlorine-based chemistry but with
different precursors. Precursors in the plasma may include Cl.sub.2
and BCl.sub.3. Protruding from the polysilicon gate layer 214 are
the silicon fins 206 without any of the layers previously
deposited.
[0041] In a next process, a spacer is formed on each surface 216
(shown best in FIG. 5B) facing the silicon fins 206. The spacer may
be formed by depositing silicon nitride or silicon oxide over the
silicon fins 206 and against surface 216 of the polysilicon gate
layer 214 and then etching away the excess spacer material to leave
spacer 218 against each surface 216 of the polysilicon gate layer
214. The spacer may be formed by, for example, plasma enhanced
chemical vapor deposition (PECVD) followed by a subsequent thermal
process at 700.degree. C. or more. The resulting FinFET structure
200 is shown in FIGS. 6A and 6B. FIG. 7 is a perspective view of
the FinFET structure 200 thus far.
[0042] In a next process as shown in FIGS. 8A, 8B and 9, epitaxial
silicon is grown on the silicon fins 206 to form a merged source
and drain 220. The epitaxial process to grow the epitaxial silicon
may start with a hydrofluoric acid (HF) pre-clean, followed by a
hydrogen (H.sub.2) anneal to purge out oxygen. The epitaxial
silicon is achieved through a silane-based precursor to deposit
epitaxial silicon on the silicon fins 206 and then form crystalline
bonding. The flat surface shown for merged source and drain 220 may
be achieved by an additional silicon etch back process.
[0043] Further semiconductor processing may now take place to
finish the FinFET structures 200.
[0044] The combination of the first layer of titanium nitride,
dielectric layer and second layer of titanium nitride forms a
metal-insulator-metal capacitor situated between each silicon fin
and the polysilicon layer. The present exemplary embodiments are
advantageous in that the MIM capacitor has greater capacitance than
a planar capacitor over the same planar area.
[0045] It will be apparent to those skilled in the art having
regard to this disclosure that other modifications of the exemplary
embodiments beyond those embodiments specifically described here
may be made without departing from the spirit of the invention.
Accordingly, such modifications are considered within the scope of
the invention as limited solely by the appended claims.
* * * * *