U.S. patent application number 14/151577 was filed with the patent office on 2014-05-08 for method of processing cavity of core substrate.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. The applicant listed for this patent is SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Yul-Kyo CHUNG, Jin-Soo JEONG, Doo-Hwan LEE, Jae-Kul LEE, Hwa-Sun PARK.
Application Number | 20140123486 14/151577 |
Document ID | / |
Family ID | 43623157 |
Filed Date | 2014-05-08 |
United States Patent
Application |
20140123486 |
Kind Code |
A1 |
JEONG; Jin-Soo ; et
al. |
May 8, 2014 |
METHOD OF PROCESSING CAVITY OF CORE SUBSTRATE
Abstract
A method of processing a cavity of a core substrate is
disclosed. The method of processing a cavity of a core substrate in
accordance with an embodiment of the present invention can include:
forming a first processing area on one surface of a core substrate,
the first processing area being demarcated by a circuit pattern;
forming a second processing area on the other surface of the core
substrate, the second processing area being demarcated by a circuit
pattern; and processing a cavity by removing the entire first
processing area from the one surface of the core substrate.
Inventors: |
JEONG; Jin-Soo; (Seoul,
KR) ; LEE; Doo-Hwan; (Euijungboo-si, KR) ;
PARK; Hwa-Sun; (Suwon-si, KR) ; LEE; Jae-Kul;
(Seoul, KR) ; CHUNG; Yul-Kyo; (Yongin-si,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRO-MECHANICS CO., LTD. |
Suwon |
|
KR |
|
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Suwon
KR
|
Family ID: |
43623157 |
Appl. No.: |
14/151577 |
Filed: |
January 9, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12860301 |
Aug 20, 2010 |
8633397 |
|
|
14151577 |
|
|
|
|
Current U.S.
Class: |
29/829 |
Current CPC
Class: |
H01L 24/82 20130101;
H05K 2201/09781 20130101; H01L 2924/3025 20130101; H01L 2224/82102
20130101; H01L 2924/15153 20130101; H01L 2924/351 20130101; H01L
2924/01006 20130101; H01L 2224/76155 20130101; H01L 2224/24227
20130101; Y10T 29/49124 20150115; H05K 3/4697 20130101; H01L 21/568
20130101; H01L 2924/351 20130101; H01L 2924/3511 20130101; H05K
2203/0156 20130101; H05K 2203/0554 20130101; H01L 2924/1517
20130101; H01L 23/5389 20130101; H01L 2924/01074 20130101; H01L
2224/24227 20130101; H01L 2924/01019 20130101; H01L 2924/01082
20130101; H01L 2924/01004 20130101; H01L 24/24 20130101; H01L
2224/04105 20130101; H05K 2203/1572 20130101; H05K 2201/10674
20130101; H05K 3/007 20130101; H01L 2924/12042 20130101; H01L
2924/12042 20130101; H01L 2924/01005 20130101; H01L 2924/1517
20130101; H05K 3/4602 20130101; H01L 2924/15153 20130101; H01L
2924/00 20130101; H05K 1/185 20130101; H01L 2924/1517 20130101;
H05K 3/0032 20130101; H01L 2924/01033 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
29/829 |
International
Class: |
H05K 3/00 20060101
H05K003/00 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 25, 2009 |
KR |
10-2009-0078738 |
Oct 27, 2009 |
KR |
10-2009-0102504 |
Claims
1. A method of processing a cavity of a core substrate, comprising:
forming a first processing area on one surface of a core substrate,
the first processing area being demarcated by a circuit pattern;
forming a second processing area on the other surface of the core
substrate, the second processing area being demarcated by a circuit
pattern; and processing a cavity by removing the entire first
processing area from the one surface of the core substrate.
2. The method of claim 1, wherein the second processing area is
wider than the first processing area.
3. The method of claim 2, wherein a center of the first processing
area and a center of the second processing area are placed on a
same vertical line.
4. The method of claim 3, wherein the first processing area and the
second processing area have a similar shape.
5-7. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of Korean Patent
Application No. 10-2009-0102504 and 10-2009-0078738, filed with the
Korean Intellectual Property Office on Oct. 27, 2009 and Aug. 25,
2009, respectively, the disclosure of which is incorporated herein
by reference in its entirety.
BACKGROUND
[0002] 1. Technical Field
[0003] The present invention is related to a method of processing a
cavity of a core substrate.
[0004] 2. Description of the Related Art
[0005] In order to manufacture an embedded substrate, in which an
electronic device is embedded in a substrate, it is necessary to
process a cavity, which is the space for mounting the electronic
device, in the substrate. The cavity can be processed in the
substrate by a punching method, which is a mechanical process using
a CNC drill or a mold, a drilling method using laser (CO2 laser or
YAG laser) and the like.
[0006] When the cavity is processed with a mechanical process, the
size of the cavity is not precise, and the mechanical friction with
the substrate can potentially cause defects such as burr, crack and
whitening on an inner wall of the cavity. For this reason, the
cavity is often processed by use of a laser drill.
[0007] In the conventional method, a circuit is formed on a core
substrate, and then a cavity is formed by directly laser-drilling
an exposed insulation layer. In this case, a laser beam removes a
portion of the exposed insulation layer to form the cavity, but
areas other than the cavity itself of the insulation layer are also
damaged (deformed) by the laser beam. Moreover, the shape of a beam
mask of the laser drill is transferred to the surface of the
insulation layer, thereby lowering the precision of the cavity
size.
SUMMARY
[0008] The present invention provides a method of processing a
cavity of a core substrate that can realize a precise cavity
shape.
[0009] An aspect of the present invention features a method of
processing a cavity of a core substrate. The method of processing a
cavity of a core substrate in accordance with an embodiment of the
present invention can include: forming a first processing area on
one surface of a core substrate, the first processing area being
demarcated by a circuit pattern; forming a second processing area
on the other surface of the core substrate, the second processing
area being demarcated by a circuit pattern; and processing a cavity
by removing the entire first processing area from the one surface
of the core substrate.
[0010] The second processing area can be wider than the first
processing area, and a center of the first processing area and a
center of the second processing area can be placed on a same
vertical line. The first processing area and the second processing
area can have a similar shape.
[0011] Additional aspects and advantages of the present invention
will be set forth in part in the description which follows, and in
part will be obvious from the description, or may be learned by
practice of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 to FIG. 3 illustrate a method of processing a cavity
of a core substrate in accordance with an embodiment of the present
invention.
[0013] FIG. 4 to FIG. 5 illustrate a method of processing a cavity
of a core substrate in accordance with another embodiment of the
present invention.
[0014] FIG. 6 illustrates a cavity with interlayer
eccentricity.
[0015] FIG. 7 illustrates an electronic device embedded in a core
substrate in which a cavity is processed in accordance with another
embodiment of the present invention.
[0016] FIG. 8A and FIG. 8B illustrate a first processing area and a
second processing area in accordance with another embodiment of the
present invention.
[0017] FIG. 9 is a modeling diagram for a stress test when an
electronic device and an insulation layer are stacked to each
other.
[0018] FIG. 10 is a graph illustrating the stress for different
thicknesses of an insulation layer.
[0019] FIG. 11 is a graph illustrating the warpage for different
thicknesses of an insulation layer.
[0020] FIG. 12 is a conception diagram illustrating an electronic
device embedded printed circuit board in accordance with an
embodiment of the present invention.
[0021] FIG. 13 to FIG. 19 illustrate a process of manufacturing an
electronic device embedded printed circuit board in accordance with
an embodiment of the present invention.
DETAILED DESCRIPTION
[0022] Since there can be a variety of permutations and embodiments
of the present invention, certain embodiments will be illustrated
and described with reference to the accompanying drawings. This,
however, is by no means to restrict the present invention to
certain embodiments, and shall be construed as including all
permutations, equivalents and substitutes covered by the ideas and
scope of the present invention. Throughout the description of the
present invention, when describing a certain technology is
determined to evade the point of the present invention, the
pertinent detailed description will be omitted.
[0023] Hereinafter, certain embodiments of a method of processing a
cavity of a core substrate will be described in detail with
reference to the accompanying drawings. Identical or corresponding
elements will be given the same reference numerals, regardless of
the figure number, and any redundant description of the identical
or corresponding elements will not be repeated.
[0024] FIG. 1 to FIG. 3 illustrate a method of processing a cavity
of a core substrate in accordance with an embodiment of the present
invention. Illustrated in FIG. 1 to FIG. 3 are a core substrate 10,
a first processing area A1, a second processing area A2, a circuit
pattern 12, a via 14, an insulator 16, a laser beam L.
[0025] First, as shown in FIG. 1, the first processing area A1
demarcated by the circuit pattern 12 is formed on one surface of
the core substrate 10, more specifically on one surface of the
insulator 16. Here, the first processing area A1 refers to a
surface on one side of the insulator 16 that is directly irradiated
by a laser beam. This first processing area A1 is demarcated by the
circuit pattern 12 formed on surfaces of the insulator 16. In other
words, an area that is exposed without being covered by the circuit
pattern 12 becomes the first processing area A1.
[0026] The circuit pattern 12 can be formed on one surface of the
insulator 16 by a subtractive process, an additive process, an
inkjet process, and other various processes.
[0027] On the other surface of the insulator 16, the second
processing area A2 demarcated by the circuit pattern 12 is formed.
Like the first processing area A1, the second processing area A2 is
demarcated by the circuit pattern 12 formed on a lower surface of
the insulator 16, and refers to an area that is exposed without
being covered by the circuit pattern 12 formed on the lower surface
of the core substrate 10. In the case of the present embodiment,
the second processing area A2 is formed to be symmetric with the
first processing area A1. That is, the first processing area A1 and
the second processing area A2 are formed at symmetrical locations
about the insulator 16 in the same size and shape.
[0028] The circuit patterns 12 formed on upper and lower surfaces
of the insulator 16 can be electrically connected to each other by
the via 14, which penetrates the insulator 16.
[0029] After the first processing area A1 and the second processing
area A2 are formed as described above, a cavity is formed by
removing the entire first processing area A1 from one surface of
the core substrate 10 by use of the laser beam L, as illustrated in
FIG. 2. By processing the cavity as described above, the
originally-designed shape and size W of the cavity can be stably
secured because the shape of the cavity is demarcated by the
circuit pattern 12, as illustrated in FIG. 3. In other words, the
size of the cavity is determined by the circuit pattern 12.
Therefore, the precision of the cavity size can be improved, and
the processing quality of inner walls and surfaces of the cavity
can be improved. FIG. 3 illustrates that a rectangular-shaped
processing area is demarcated by the circuit pattern 12 and a
cavity in the shape of a rectangular column is formed.
[0030] FIG. 4 to FIG. 6 illustrate a method of processing a cavity
of a core substrate 10 in accordance with another embodiment of the
present invention. This embodiment is different from the
earlier-described embodiment in that the second processing area A2
is formed wider than the first processing area A1. Hereinafter,
differences between the earlier-described embodiment and the
present embodiment will be mainly described.
[0031] According to the present embodiment, as illustrated in FIG.
4, the second processing area A2 is formed wider than the first
processing area A1. FIG. 4 illustrates that the first processing
area A1 has the size of W1 and the second processing area A2 has
the size of W2.
[0032] By designing and forming the second processing area A2 to be
bigger than the first processing area A1, even if there is some
interlayer eccentricity while circuit patterns 12a, 12b are formed
on upper and lower surfaces of the core substrate 10, it becomes
possible to prevent the size of the cavity from being reduced due
to the eccentricity and precisely process the cavity having a
desired size. FIG. 5 illustrates how the cavity is processed using
a laser beam L.
[0033] FIG. 6 illustrates a case of the cavity with a reduced size
due to the interlayer eccentricity. As shown in FIG. 6, when there
is eccentricity between upper and lower circuit patterns 12 of the
core substrate 10, it becomes inevitable that the cavity results in
a smaller size W3 than the originally designed cavity size W1 due
to a slope formed in the cavity. That is, the space for embedding
an electronic device 20 becomes reduced.
[0034] By forming the second processing area A2 to be bigger than
the first processing area A1, the difference in size between the
first processing area A1 and the second processing area A2 can
complement the eccentricity, as shown in FIG. 7, and the originally
designed cavity size can be obtained.
[0035] Since the eccentricity of the circuit patterns 12a, 12b can
occur in both an x-axis direction and a y-axis direction, the
center of the first processing area A1 and the center of the second
processing area A2 can be placed on a same vertical line in order
to complement the eccentricity of the circuit patterns 12a, 12b.
FIG. 8A illustrates that the center of the first processing area A1
is overlapped with the center of the second processing area A2.
[0036] In addition, by making the first processing area A1 and the
second processing area A2 in a similar shape, the eccentricity of
the circuit patterns 12a, 12b in every direction can be more fully
complemented. FIG. 8A and FIG. 8B show that both the first
processing area A1 and the second processing area A2 have the shape
of a square.
[0037] Hereinafter, an electronic device embedded printed circuit
board in accordance with another aspect of the present invention
will be described.
[0038] FIG. 9 is a modeling diagram for a stress test when an
electronic device and an insulation layer are stacked to each
other. FIG. 10 is a graph illustrating the stress according to the
thickness of an insulation layer. FIG. 11 is a graph illustrating
the warpage according to the thickness of an insulation layer. FIG.
12 is a conception diagram illustrating an electronic device
embedded printed circuit board in accordance with an embodiment of
the present invention.
[0039] The present embodiment features a geometrically symmetric
electronic device embedding structure and a method of embedding an
electronic device for such structure, in order to realize an
ultra-thin, highly-reliable electronic device embedded printed
circuit board that minimizes the warpage in a repeated thermal
stress environment. The warpage of a substrate under thermal stress
is determined by physical property values, such as the coefficient
of thermal expansion (CTE), Young's modulus and Poisson ratio, and
geometric factors of applied materials. For a printed circuit board
illustrated in FIG. 9, the neutral line can be expressed in the
following expression.
y _ = E I t 2 + t d 2 ( E d - E I ) 2 ( E d t d + E I t I ) ( 1 )
##EQU00001##
[0040] Here, E.sub.I is Young's modulus of the electronic device,
t.sub.I is the thickness (m) of the electronic device, E.sub.d is
Young's modulus (Pa) of the insulation layer, t.sub.d is the
thickness of the insulation layer, and t is the overall thickness
(=t.sub.d+t.sub.I) of the substrate.
[0041] The bending moment M (expressed in Nm) and the normal force
N (expressed in N) of the substrate calculated from the above
expression are expressed in the following expressions.
M.sub.1=M.sub.2=E.sub.I.alpha..sub.I.DELTA.Tt.sub.Iw(t.sub.d+t.sub.I/2-y-
)+E.sub.d.alpha..sub.d.DELTA.Tt.sub.dw(t.sub.d/2-y), M.sub.6=0
N.sub.1=N.sub.2=E.sub.I.alpha..sub.I.DELTA.Tt.sub.Iw+E.sub.d.alpha..sub.-
d.DELTA.Tt.sub.dw, N.sub.6=0 (2)
[0042] Here, E.sub.I is Young's modulus of the electronic device,
t.sub.I is the thickness of the electronic device, .alpha..sub.1 is
the CTE of the electronic device, E.sub.d is Young's modulus (Pa)
of the insulation layer, t.sub.d is the thickness of the insulation
layer, .alpha..sub.d is the CTE (m/K) of the insulation layer,
.DELTA.T is the change in temperature (K), and w is the width of
the substrate.
[0043] The compliance matrix calculated from the above expression
can be expressed in the following expression.
S = ( 1 E x - v xy E x 0 - v yx E y 1 E y 0 0 0 1 G xy ) ( 3 )
##EQU00002##
[0044] The stiffness matrix calculated from the above expression is
as follows.
Q=S.sup.-1 (4)
[0045] The ABD matrix can be expressed in the following
expression.
[ N 1 N 2 N 6 M 1 M 2 M 6 ] = [ A 11 A 12 A 16 B 11 B 12 B 16 A 21
A 22 A 26 B 21 B 22 B 26 A 61 A 62 A 66 B 61 B 62 B 66 B 11 B 12 B
16 D 11 D 12 D 16 B 21 B 22 B 26 D 21 D 22 D 26 B 61 B 62 B 66 D 61
D 62 D 66 ] [ 1 2 6 .kappa. 1 .kappa. 2 .kappa. 6 ] A ij = .intg. Q
ij z B ij = .intg. Q ij z z D ij = .intg. Q ij z 2 z ( 5 )
##EQU00003##
[0046] The strain and curvature of the substrate can be obtained by
the following expression.
[ .kappa. ] = [ ABD ] - 1 [ N M ] ( 6 ) ##EQU00004##
[0047] The stress evaluation obtained from the above calculation is
as follows.
mechanical strain
.epsilon..sub.x=.epsilon..sub.1+.kappa..sub.1z
total strain .epsilon..sub.x= .epsilon..sub.x-.alpha..DELTA.T
Stress .sigma.=Q.sub.11.epsilon..sub.x (7)
[0048] FIG. 10 is the stress evaluation rendered in a graph. That
is, FIG. 10 shows the change in stress on a top side and a bottom
side of the substrate according to the thickness of the insulation
layer, assuming that the electronic device has the fixed thickness
of 100 um.
[0049] FIG. 11 illustrates the dependence of the thickness of the
electronic device on the thickness of the insulation layer that is
calculated on the basis of the warpage. In other words, FIG. 11
shows the warpage of the substrate according to the thickness of
the insulation layer when the electronic device has the fixed
thicknesses of 50 um and 100 um.
[0050] In FIG. 11, assuming that the thickness of the insulation
layer is 50 um, while an IC having the thickness of 50 um has the
warpage of 0.26 mm, the warpage is reduced to 1/3 to 0.09 mm when
the thickness of the IC is doubled to 100 um. From this, it can be
inferred that the warpage of a substrate depends far more on the
thickness of the electronic device than on the thickness of the
insulation layer. Accordingly, it can be expected that, in a
geometrically asymmetric printed circuit board, reducing the
thickness of the substrate, as the electronic device becomes
thinner, will increase the warpage to an unbearable level.
[0051] To solve this problem, the warpage needs to be minimized by
adjusting the electronic device to be placed in the center about
the insulation layer of the substrate to make the electronic device
geometrically symmetric. In the present embodiment, the ultra-thin,
highly-reliable electronic device embedded printed circuit board
that minimizes the warpage under repeated thermal stress is
realized by giving a geometric symmetry to the electronic device
embedded printed circuit board.
[0052] FIG. 12 is a sectional view of an electronic device embedded
printed circuit board 100 in accordance with an embodiment of the
present invention. As illustrated in FIG. 12, the electronic device
embedded printed circuit board 100 in accordance with the present
embodiment includes a core substrate 110, in which a cavity 116 is
formed, an electronic device 120, which is embedded in the cavity
116 by a face-up method and has an electrode 122 formed on a
surface thereof, a first insulation layer 130a, which is stacked on
an upper surface of the core substrate 110, and a second insulation
layer 130b, which is stacked on a lower surface of the core
substrate 110 and has a same thickness as the first insulation
layer 130a. Here, the thickness (represented by "b") of the
electronic device including the thickness of the electrode 122 is
same as the thickness of the core substrate 110.
[0053] Here, the term "same" does not necessarily refer to a
mathematically precise identical numerical thickness, but a
substantially identical thickness in which a design error, a
manufacturing error and a measurement error are considered.
Hereinafter, the meaning of "same" used in this description will
refer to the substantial sameness described above.
[0054] The electronic device embedded printed circuit board 100 in
accordance with the present embodiment minimizes the warpage of the
substrate by designing and manufacturing the embedded electronic
device 120 in a symmetric structure. Furthermore, by designing the
thickness ("b") of the electronic device including the thickness of
the electrode 122 to be the same as that of the core substrate 110,
symmetry of the core substrate 110 itself can be provided, and as a
result the warpage of the core substrate 110 itself, in which the
electronic device 120 is embedded, can be minimized In other words,
in realizing the vertical symmetry of the core substrate 110, the
thickness of the electrode 122 formed on the surface of the
electronic device 120 is also considered, thereby maximizing the
symmetry of the core substrate 110 itself. This symmetric structure
functions to lower the risk of increasing the warpage as the
printed circuit board and the electronic device 120 embedded in the
printed circuit board become thinner.
[0055] Moreover, by mounting the electronic device 120 being
embedded in the core substrate 100 by a face-up method, the circuit
can be better matched. In an actual printed circuit board, an upper
surface and a lower surface are off-matched by about 20 um to 50
um, but the matching between the electrode of the electronic device
and the circuit on the board can be improved by embedding the
electronic device 120 with a face-up method and placing the
electrode 122 upward as in the case of the present embodiment.
[0056] In case inner circuits 114a, 114b are formed on the surface
of the core substrate 110, the thickness ("b") of the electronic
device 120 including the thickness of the electrode can be designed
to be same as the thickness ("a") of the core substrate 110
including the thicknesses of the inner layers 114a, 114b.
[0057] It is preferred that the sum of distances between vertical
sides on either end of the electronic device 120 and an inner wall
of the cavity 116 is at least 60 um. Since the cavity 116 is
processed by use of a punch or laser and the electronic device 120
can be chipped during a dicing process, the distance is based on an
outermost line of each rough interface.
[0058] Although the distance between the electronic device 120 and
the inner wall is designed to be 30 um at the minimum, it is
possible that the electronic device 120 makes contact with the
inner wall on one side due to equipment tolerance. Therefore, it is
preferable that the range of each of "c" and "d" is between 0 and
60 um, and the sum of "c" and "d" is at least 60 um.
[0059] When one side is designed to be less than 50 um, it is
observed that the electronic device 120 is not properly inserted in
the cavity 116 but is laid on one side of the cavity 116. Moreover,
according to a simulation and real data, the warpage was reduced as
the cavity 116 becomes bigger. However, if the cavity 116 becomes
too thin, it becomes difficult to secure the space for the circuit,
and thus it is preferable that the maximum value of "c+d" is 160 um
or less.
[0060] Hitherto, the structure of the electronic device embedded
printed circuit board in accordance with an embodiment of the
present invention has been described. Hereinafter, a method of
manufacturing the electronic device embedded printed circuit board
will be described with reference to FIG. 13 to FIG. 19. Since the
structure of the electronic device embedded printed circuit board
in accordance with the present embodiment is identical to that of
the above-description, no structural features will be described,
but the manufacturing process will be mainly described.
[0061] Firstly, the core substrate 110 is prepared (see FIG. 13).
Formed on the surface of the core substrate 110 can be the inner
circuits 114a, 114b, in which case the upper and lower surfaces of
the core substrate 110 are connected with each other through a via
112.
[0062] Next, the cavity 116 is perforated in the core substrate 110
(see FIG. 14). The cavity 116 is where the electronic device 120 is
embedded later, and can be processed in a proper size and shape by
considering the size and shape of the electronic device being
embedded. A mechanical drill or laser drill can be used for
processing the cavity 116 in the core substrate 110.
[0063] Then, an adhesive layer 140 is adhered to the lower surface
of the core substrate 110 (see FIG. 15). By adhering the adhesive
layer 140 on the lower surface of the core substrate, in which the
cavity 116 is perforated, a lower side of the cavity becomes sealed
by the adhesive layer 140.
[0064] Next, the electronic device 120 is adhered by a face-up
method to a surface of the adhesive layer 140 that is exposed
through the cavity 116 (see FIG. 16), and then the electronic
device 120 is covered by stacking the first insulation layer 130a
on the upper surface of the core substrate 110 (see FIG. 17). The
inside of the cavity 116, in which the electronic device 120 is
embedded, is also filled by the first insulation layer 130a being
stacked on the upper surface of the core substrate 110.
[0065] Then, the adhesive layer 140 adhered to the lower surface of
the core substrate 110 is removed, and the second insulation layer
130b is stacked on the lower surface of the core substrate 110 (see
FIG. 18).
[0066] Afterwards, circuit patterns 132a, 132b and vias 134a, 134b
are formed on the first insulation layer 130a and the second
insulation layer 130b (see FIG. 19).
[0067] Hitherto, some embodiments of the present invention have
been described. However, it shall be appreciated by anyone
ordinarily skilled in the art to which the present invention
pertains that there can be a variety of permutations and
modifications of the present invention without departing from the
technical ideas and scopes of the present invention that are
disclosed in the claims appended below.
[0068] A large number of embodiments in addition to the
above-described embodiments are present within the claims of the
present invention.
* * * * *