U.S. patent application number 13/527828 was filed with the patent office on 2013-12-19 for replacement metal gate processing with reduced interlevel dielectric layer etch rate.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. The applicant listed for this patent is Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang. Invention is credited to Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang.
Application Number | 20130334580 13/527828 |
Document ID | / |
Family ID | 49229823 |
Filed Date | 2013-12-19 |
United States Patent
Application |
20130334580 |
Kind Code |
A1 |
Cheng; Kangguo ; et
al. |
December 19, 2013 |
REPLACEMENT METAL GATE PROCESSING WITH REDUCED INTERLEVEL
DIELECTRIC LAYER ETCH RATE
Abstract
A semiconductor structure includes an interlevel dielectric
(ILD) layer disposed over a semiconductor substrate and a
transistor gate structure formed on the substrate; and a shallow
gas cluster ion beam (GCIB) layer infused in a top portion of the
ILD layer; wherein the GCIB layer has a slower etch rate with
respect to the ILD layer.
Inventors: |
Cheng; Kangguo;
(Schenectady, NY) ; Wang; Junli; (Singerlands,
NY) ; Wong; Keith Kwong Hon; (Wappingers Falls,
NY) ; Yang; Chih-Chao; (Glenmont, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Cheng; Kangguo
Wang; Junli
Wong; Keith Kwong Hon
Yang; Chih-Chao |
Schenectady
Singerlands
Wappingers Falls
Glenmont |
NY
NY
NY
NY |
US
US
US
US |
|
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
49229823 |
Appl. No.: |
13/527828 |
Filed: |
June 20, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13524576 |
Jun 15, 2012 |
8546209 |
|
|
13527828 |
|
|
|
|
Current U.S.
Class: |
257/288 ;
257/E29.255 |
Current CPC
Class: |
H01L 29/7833 20130101;
H01L 29/4966 20130101; H01L 29/66545 20130101; H01L 29/517
20130101; H01L 29/495 20130101; H01L 29/6659 20130101 |
Class at
Publication: |
257/288 ;
257/E29.255 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Claims
1. A semiconductor structure, comprising: an interlevel dielectric
(ILD) layer disposed over a semiconductor substrate and a
planarized replacement transistor gate structure formed on the
substrate; and a shallow gas cluster ion beam (GCIB) layer infused
in a top portion of the ILD layer; wherein the GOB layer has a
slower etch rate with respect to the ILD layer.
2. The structure of claim 1, wherein the ILD layer comprises an
oxide layer.
3. The structure of claim 2, wherein the transistor gate structure
comprises a high-K dielectric layer and a metal gate layer.
4. The structure of claim 3, wherein the etch rate of the GCIB is
about 5 times slower than that of the ILD layer.
5. The structure of claim 4, wherein the GCIB comprises a silicon
rich oxide.
6. The structure of claim 5, wherein the GCIB layer has a thickness
of about 10 nanometers (nm) or less.
7. The structure of claim 6, wherein the ILD layer has a thickness
of about 40 nm.
8. The structure of claim 1, further comprising a channel region
defined in the semiconductor substrate, below the planarized
replacement transistor gate structure, wherein the channel region
is free from ions of the shallow GCIB layer infused in the top
portion of the ILD layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of U.S. patent
application Ser. No. 13/524,576, filed Jun. 15, 2012, the
disclosure of which is incorporated by reference herein in its
entirety.
BACKGROUND
[0002] The present invention relates generally to semiconductor
device manufacturing and, more particularly, to implementing
replacement metal gate processing with a reduced interlevel
dielectric layer (ILD) etch rate.
[0003] Field effect transistors (FETs) are widely used in the
electronics industry for switching, amplification, filtering, and
other tasks related to both analog and digital electrical signals.
Most common among these are metal-oxide-semiconductor field effect
transistors (MOSFET or MOS), in which a gate structure is energized
to create an electric field in an underlying channel region of a
semiconductor body, by which electrons are allowed to travel
through the channel between a source region and a drain region of
the semiconductor body. Complementary MOS (CMOS) devices have
become widely used in the semiconductor industry, wherein both
n-type and p-type (NFET and PFET) FETs are used to fabricate logic
and other circuitry.
[0004] The source and drain regions of an FET are typically formed
by adding dopants to targeted regions of a semiconductor body on
either side of the channel. A gate structure is formed above the
channel, which includes a gate dielectric located over the channel
and a gate conductor above the gate dielectric. The gate dielectric
is an insulator material, which prevents large leakage currents
from flowing into the channel when a voltage is applied to the gate
conductor, while allowing the applied gate voltage to set up a
transverse electric field in the channel region in a controllable
manner. Conventional MOS transistors typically include a gate
dielectric formed by depositing or by growing silicon dioxide
(SiO.sub.2) or silicon oxynitride (SiON) over a silicon wafer
surface, with doped polysilicon formed over the SiO.sub.2 to act as
the gate conductor.
[0005] Continuing trends in semiconductor device manufacturing
include reduction in electrical device feature sizes (i.e.,
scaling), as well as improvements in device performance in terms of
device switching speed and power consumption. MOS transistor
performance may be improved by reducing the distance between the
source and the drain regions under the gate conductor of the
device, known as the gate or channel length, and by reducing the
thickness of the layer of gate dielectric that is formed over the
semiconductor surface. However, there are electrical and physical
limitations on the extent to which the thickness of SiO.sub.2 gate
dielectrics can be reduced. For example, thin SiO.sub.2 gate
dielectrics are prone to gate tunneling leakage currents resulting
from direct tunneling of electrons through the thin gate
dielectric.
[0006] Accordingly, recent MOS and CMOS transistor scaling efforts
have focused on high-k dielectric materials having dielectric
constants greater than that of SiO.sub.2 (e.g., greater than about
3.9). High-k dielectric materials can be formed in a thicker layer
than scaled SiO.sub.2, and yet still produce equivalent field
effect performance. The relative electrical performance of such
high-k dielectric materials is often expressed in terms equivalent
oxide thickness (EOT), since the high-k material layer may be
thicker, while still providing the equivalent electrical effect of
a much thinner layer of SiO.sub.2. Because the dielectric constant
"k" is higher than silicon dioxide, a thicker high-k dielectric
layer can be employed to mitigate tunneling leakage currents, while
still achieving the equivalent electrical performance of a thinner
layer of thermally grown SiO.sub.2.
SUMMARY
[0007] In one aspect, semiconductor structure includes an
interlevel dielectric (ILD) layer disposed over a semiconductor
substrate and a transistor gate structure formed on the substrate;
and a shallow gas cluster ion beam (GCIB) layer infused in a top
portion of the ILD layer; wherein the GCIB layer has a slower etch
rate with respect to the ILD layer.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0008] Referring to the exemplary drawings wherein like elements
are numbered alike in the several Figures:
[0009] FIG. 1 is a cross sectional view of a processing stage of a
high-K, metal gate (HKMG) transistor device using a replacement
gate (gate last) technique;
[0010] FIG. 2 illustrates the formation of an interlevel dielectric
(ILD) layer over the device of FIG. 1;
[0011] FIG. 3 illustrates removal of nitride cap and dummy
polysilicon portions of the dummy gate stack structure of FIG.
2;
[0012] FIG. 4 illustrates removal of the dummy gate oxide portion
of the dummy gate stack structure, as well as a portion of the ILD
layer of FIG. 3;
[0013] FIG. 5 illustrates the formation of a gas cluster ion beam
(GCIB) layer at the top of the ILD layer prior to dummy gate stack
removal, in accordance with an exemplary embodiment;
[0014] FIG. 6 illustrates the removal of the dummy gate stack
structure of FIG. 5, leaving the ILD layer substantially
intact;
[0015] FIG. 7 illustrates the formation of a replacement metal gate
structure for the device of FIGS. 6; and
[0016] FIG. 8 illustrates an exemplary processor for performing
GCIB processing.
DETAILED DESCRIPTION
[0017] With respect to high-k metal gate (HKMG) technology, the two
main approaches for introducing a metal gate into the standard CMOS
process flow are a "gate first" process or a "gate last" process.
The latter is also referred to as a "replacement gate" or
replacement metal gate (RMG) process. In a gate first process,
high-k dielectric and metal processing is completed prior to
polysilicon gate deposition. The metal gate material is
subtractively etched along with the polysilicon gate material prior
to source and drain formation.
[0018] The RMG process architecture, on the other hand, avoids the
problems of workfunction material stability seen in the gate first
architecture. Here, a dummy gate structure is used to self-align
the source and drain implant and anneals, followed by stripping out
the dummy gate materials and replacing them with the high-k and
metal gate materials. Although this process is more complex than
the gate first technique, advantages of a replacement gate flow
include the use of separate PMOS and NMOS metals for work function
optimization. In addition, the two metals are not exposed to high
temperatures, simplifying material selection. Further, the
polysilicon gate removal can actually be used to enhance strain
techniques, thereby increasing drive currents.
[0019] In current replacement metal gate (RMG) processing, an ILD
oxide is typically usually used to facilitate the dummy gate
removal process after the source/drain and source/drain extensions
are defined with the dummy gate in place. In this regard, an ILD
oxide (which is deposited oxide) has a high HF (hydrofluoric acid)
etch rate. Due to the high etch rate of ILD oxide, certain HF
processing operations during dummy gate stack removal (e.g., HF
precleaning before dummy poly removal, as well as HF etching to
remove dummy gate oxide) cause recessing/loss of ILD material,
which in turn results in variations in the final metal gate height
across the wafer. Another issue may be excess metal gate fill
material that does not get remove during planarization, which can
in turn lead to device shorting.
[0020] One possible way to reduce the etch rate of a deposited
oxide is by high temperature annealing (i.e., a densification
anneal). However, such a high temperature anneal is incompatible
with CMOS flow because it will cause excessive dopant diffusion.
Another technique may be to perform an ion implantation of a
material such as silicon to increase the etch rate of the
SiO.sub.2. Here, however, the depth of such an ion implantation is
difficult to precisely control. As a result, undesired dopant atoms
may reach locations such as the dummy polysilicon in the gate stack
and/or even the source/drain diffusion regions of the
substrate.
[0021] Accordingly, the exemplary embodiments disclosed herein
address the above described problems by improving the etch
resistivity of the deposited ILD oxide, but without the side
effects of a high temperature, dopant diffusing process or a high
energy ion implantation process. More specifically, the etch rate
of ILD oxide is reduced by a low temperature process, namely a gas
cluster ion beam (GCIB) implantation process.
[0022] Referring initially to FIG. 1, there is shown a cross
sectional view of a processing stage of a high-K, metal gate (HKMG)
transistor device 100 using a replacement gate (gate last)
technique. The transistor device 100 includes semiconductor
substrate 102 having shallow trench isolation (STI) regions 104
formed therein. The semiconductor substrate 102 includes a
semiconductor material, which may be selected from, but is not
limited to, silicon, germanium, silicon-germanium alloy, silicon
carbon alloy, silicon-germanium-carbon alloy, gallium arsenide,
indium arsenide, indium phosphide, III-V compound semiconductor
materials, II-VI compound semiconductor materials, organic
semiconductor materials, and other compound semiconductor
materials. Where the semiconductor material of the semiconductor
substrate 102 is a single crystalline silicon-containing
semiconductor material, the single crystalline silicon-containing
semiconductor material may be selected from single crystalline
silicon, a single crystalline silicon carbon alloy, a single
crystalline silicon germanium alloy, and a single crystalline
silicon germanium carbon alloy.
[0023] The semiconductor material of the semiconductor substrate
102 may be appropriately doped either with p-type dopant atoms or
with n-type dopant atoms. The dopant concentration of the
semiconductor substrate 102 may range from about
1.0.times.10.sup.15 atoms/cm.sup.3 to about 1.0.times.10.sup.19
atoms/cm.sup.3, and more specifically from about
1.0.times.10.sup.16 atoms/cm.sup.3 to about 3.0.times.10.sup.18
atoms/cm.sup.3, although lesser and greater dopant concentrations
are contemplated herein also. In addition, the semiconductor
substrate 102 may be a bulk substrate, a semiconductor-on-insulator
or silicon-on-insulator (SOI) substrate, a hybrid substrate, or a
finFET substrate.
[0024] The STI regions 104 may include an oxide material and be
formed by any techniques known in the art, such as by
patterning/etching/deposition, implantation, etc. The specific
point in processing depicted in FIG. 1 is following dummy gate
stack deposition, pattering, sidewall spacer formation, and
source/drain region and extension implant. Thus, FIG. 1 further
illustrates a dummy gate stack formed over the substrate 102,
including a dummy gate oxide layer 106, a dummy polysilicon layer
108 on the dummy gate oxide layer 106, and a dummy nitride cap
layer 110 on the dummy polysilicon layer 108. In addition, gate
sidewall spacers 112 (e.g., nitride) are formed adjacent the dummy
gate stack.
[0025] In accordance with a replacement gate process flow, the
definition of the patterned dummy gate stack allows for source and
drain extension region implantation, as shown at 114. Once the gate
sidewall spacers 112 are in place, the main source and drain
extension regions 116 can then be implanted as well. It should be
appreciated that, in addition to the specific structures depicted
in the embodiment of FIG. 1, the source/drain regions 116 may also
have embedded source/drain stressor layers and/or may comprised
raised source/drain for stress enhancement, carrier mobility and/or
resistivity reduction purposes (not shown).
[0026] FIG. 2 illustrates the formation of an interlevel dielectric
(ILD) layer 118 over the device of FIG. 1. This may include, for
example, a low temperature deposition of an oxide layer such as
SiO.sub.2. Following deposition of the oxide ILD material, the ILD
layer 118 is planarized such as by chemical mechanical polishing
(CMP), stopping on the dummy nitride cap layer 110. At this point,
the device is ready for dummy gate removal and HKMG formation.
[0027] Referring now to FIG. 3, the removal of nitride cap and
dummy polysilicon portions of the dummy gate stack structure of
FIG. 2 is illustrated. Here, suitable etch chemistries are applied
so as to remove the nitride and polysilicon layers. Although not
specifically depicted in FIG. 3, the directional (e.g., RIE) etch
of the gate stack material (including the dummy nitride cap) may
also result in a reduction in height of the sidewall spacers 112.
Upon removal of the dummy polysilicon, the etch chemistry is then
altered to remove the dummy gate oxide layer 106. However, as
shown, in FIG. 4, due to the high etch rate of the ILD oxide
material 118 (and perhaps also due to HF exposure during
precleaning prior to the dummy polysilicon removal), the removal of
dummy gate oxide layer may also causes a significant reduction in
the height of the ILD layer, now indicated at 118'. Such a
condition as depicted in FIG. 4 may lead to device problems such as
final metal gate height variations, as well as device shorting.
[0028] Accordingly, FIG. 5 illustrates the formation of a gas
cluster ion beam (GCIB) layer 120 infused at a top portion of the
ILD layer 118 prior to dummy gate stack removal, in accordance with
an exemplary embodiment. In GCIB processing, a surface is bombarded
by a beam of high energy, gas phase atomic clusters. The clusters
are formed when a high pressure gas (e.g., 10 atmospheres)
supersonically expands into a vacuum (e.g., 1.times.10.sup.-5
Torr), cools, and then condenses into weakly ionized clusters. The
ionized clusters are accelerated electrostatically to very high
velocities, and are focused into a tight beam that impacts a
substrate surface. As opposed to a more dispersed ion implant
process, atoms of a cluster ion impact interact nearly
simultaneously with the substrate atoms, which produces results
such as surface smoothing, pore sealing, shallow cratering, surface
chemistry alterations, thin film deposition, and shallow
implantation or infusing, depending upon whether the gas clusters
are inert or reactive.
[0029] A GCIB may include chemical beams of almost any species or
mixture, depending on the specific objectives of the processing.
Exemplary beams may include, for example, silicon (Si), nitrogen
(N) or carbon (C) for film deposition, fluorine (F) for etching,
and argon (Ar), N, C, or oxygen (O) for surface modification. In
the embodiment depicted, a silicon species is used in the GCIB
processing to form a silicon rich oxide GCIB layer 120. The silicon
rich oxide GCIB layer 120 has an etch rate of about 5 times slower
than that of the SiO.sub.2 ILD layer 118. In addition to being a
low temperature (e.g., room temperature) infusion process, the GCIB
formation results in the silicon rich oxide GCIB layer 120 having a
relatively shallow thickness, on the order of about 10 nm or less.
This may be compared to a total ILD layer height of, for example,
about 40 nm.
[0030] Accordingly, as shown in FIG. 6, upon removal of the dummy
gate structure, including the nitride cap, polysilicon and gate
oxide layers, the more etch resistant silicon rich oxide GCIB layer
120 allows the ILD layer 118 to remain substantially intact.
Finally, as shown in FIG. 7, replacement gate processing may
continue as known in the art, including formation and planarization
of one or more high-k gate dielectric layers 122 and metal gate
layers 124. In some examples, the high-K dielectric layer 122 may
include a dielectric metal oxide having a dielectric constant that
is greater than the dielectric constant (7.5) of silicon nitride,
and may be formed by methods well known in the art including, for
example, chemical vapor deposition (CVD), ALD, molecular beam
deposition (MBD), pulsed laser deposition (PLD), liquid source
misted chemical deposition (LSMCD), etc. In an exemplary
embodiment, the dielectric metal oxide of the high-k dielectric
layer 122 includes a metal and oxygen, and optionally nitrogen
and/or silicon. Specific examples of high-k dielectric materials
include, but are not limited to: HfO.sub.2, ZrO.sub.2,
La.sub.2O.sub.3, Al.sub.2O.sub.3, TiO.sub.2, SrTiO.sub.3,
LaAlO.sub.3, Y.sub.2O.sub.3, HfO.sub.xN.sub.y, ZrO.sub.xN.sub.y,
La.sub.2O.sub.xN.sub.y, Al.sub.2O.sub.xN.sub.y, TiO.sub.xN.sub.y,
SrTiO.sub.xN.sub.y, LaAlO.sub.xN.sub.y, Y.sub.2O.sub.xN.sub.y, a
silicate thereof, and an alloy thereof. Each value of x is
independently from 0.5 to 3 and each value of y is independently
from 0 to 2. The thickness of the high-k dielectric layer 122 may
be from about 1 nm to about 10 nm, and more specifically from about
1.5 nm to about 3 nm.
[0031] The metal gate layer 124, while schematically illustrated as
a single layer in FIG. 7, may be a metal gate material stack that
includes one or more layers of metal materials such as, for
example, Al, Ta, TaN, W, WN, Ti and TiN, having an appropriate
workfunction depending on whether the transistor is an NFET or a
PFET device.
[0032] In one specific embodiment of an NFET device, the metal gate
layer 124 may include workfunction setting metal layers selected to
set the workfunction around the silicon conduction band edge. Such
workfunction setting metal layers may include, for example,
optional layers of about 10 .ANG. to about 30 .ANG. thick titanium
nitride and about 10 .ANG. to about 30 .ANG. thick tantalum
nitride, followed by a non-optional about 10 .ANG. to about 40
.ANG. thick layer of titanium aluminum, which together make up a
workfunction setting metal layer portion of the metal gate layer
106. Alternatively, titanium aluminum nitride, tantalum aluminum,
tantalum aluminum nitride, hafnium silicon alloy, hafnium nitride,
or tantalum carbide may be used in the workfunction setting metal
layer portion in lieu of the titanium aluminum.
[0033] In one specific embodiment of a PFET device, the metal gate
layer 124 may include workfunction setting metal layers selected to
set the workfunction around the silicon valence band edge. Here,
such workfunction setting metal layers may include, for example,
optional layers of about 10 .ANG. to about 30 .ANG. thick titanium
nitride and about 10 .ANG. to about 30 .ANG. thick tantalum
nitride, followed by non-optional layers of about 30 .ANG. to about
70 .ANG. thick titanium nitride and about 10 .ANG. to about 40
.ANG. thick layer of titanium aluminum, which together make up a
workfunction setting metal layer portion of the metal gate layer
124. Alternatively, tungsten, tantalum nitride, ruthenium,
platinum, rhenium, iridium, or palladium may be used in the
workfunction setting metal layer portion in lieu of the titanium
nitride and titanium aluminum nitride, tantalum aluminum, tantalum
aluminum nitride, hafnium silicon alloy, hafnium nitride, or
tantalum carbide may be deposited instead of the titanium aluminum.
Regardless of the specific workfunction setting metal layers used
in either an NFET or a PFET device, a remainder of the metal gate
layer 106 may include a fill metal such as aluminum, titanium-doped
aluminum, tungsten or copper.
[0034] Finally, FIG. 8 illustrates an exemplary processor 800 for
performing GCIB processing as described above. The processor 800 is
enclosed in a vacuum vessel 802 having a source chamber 804 and a
processing chamber 806. Although not required, it may sometimes be
desirable to also employ a differential vacuum pumping chamber 808
to help isolate the downstream regions from the higher pressure
upstream regions. The interior of the vacuum vessel 802 is
maintained at a vacuum reduced pressure by one or more vacuum pumps
810. A source gas 812 is introduced through a gas feed tube 814.
Gas clusters 816 are formed by creating a supersonic jet of source
gas through a properly shaped nozzle 818 into the source chamber
43, which is at a substantially reduced pressure.
[0035] Cooling resulting from the expansion causes the gas to
condense into clusters of, for example, from several to several
thousand atoms or molecules. A gas skimmer aperture 820 is used to
separate the gas products that have not been converted into a
cluster jet from the cluster jet so as to minimize pressure in the
downstream regions where such higher pressures would be detrimental
(e.g., ionizer 822, accelerator high voltage electrodes 824, and
processing chamber 806). Suitable source gases 812 include, for
example, argon, other inert gases, oxygen, nitrogen, oxygen bearing
gases such as carbon dioxide, and silicon bearing gases. After the
cluster jet has been formed, the clusters 816 are ionized in an
ionizer 822. The ionizer 322 may be an electron impact ionizer that
produces thermoelectrons from one or more incandescent filaments
and accelerates and directs the electrons causing them to collide
with the gas clusters 816 in the gas cluster jet where it passes
through the ionizer 822. The electron impact ejects electrons from
the clusters, causing the clusters to become positively
ionized.
[0036] A set of suitably biased high voltage lens electrodes 826
extracts the cluster ions from the ionizer and focuses them to form
a gas cluster ion beam. Another set of high voltage accelerator
electrodes 824 accelerates the beam to a desired energy, for
example, from 1 keV to several tens of keV. The accelerated beam is
directed at a substrate 828 for GCIB processing. Although not
specifically illustrated in FIG. 8, is a mass selector may be
utilized for selecting clusters of a certain mass or within a
certain range of masses. Such a mass selector can be, for example,
a weak transverse magnetic field for deflecting monomer ions and
other light ions (e.g., those cluster ions often or fewer atoms or
molecules) out of the beam and passing more massive cluster
ions.
[0037] Since the silicon rich layer infusion application
contemplates processing of large diameter wafers with spatially
uniform results, a scanning system 830 is may be used in order to
uniformly scan the GCIB across large areas to produce spatially
homogeneous results. In this regard, two pairs of orthogonally
oriented electrostatic scan plates 832 and 834 make up scanning
system 830, and having suitable beam scanning voltage waveforms
imposed can be utilized to produce a raster or other scanning
pattern across the desired area.
[0038] While the invention has been described with reference to a
preferred embodiment or embodiments, it will be understood by those
skilled in the art that various changes may be made and equivalents
may be substituted for elements thereof without departing from the
scope of the invention. In addition, many modifications may be made
to adapt a particular situation or material to the teachings of the
invention without departing from the essential scope thereof.
Therefore, it is intended that the invention not be limited to the
particular embodiment disclosed as the best mode contemplated for
carrying out this invention, but that the invention will include
all embodiments falling within the scope of the appended
claims.
* * * * *