U.S. patent application number 13/348766 was filed with the patent office on 2013-07-18 for step-like spacer profile.
This patent application is currently assigned to GLOBAL FOUNDRIES Singapore Pte. Ltd.. The applicant listed for this patent is Hai Cong, Lup San Leong, Huang Liu, Xuesong Rao, Alex See, Chim Seng Seet, Yun Ling Tan, Wen Zhan Zhou, Zheng Zou. Invention is credited to Hai Cong, Lup San Leong, Huang Liu, Xuesong Rao, Alex See, Chim Seng Seet, Yun Ling Tan, Wen Zhan Zhou, Zheng Zou.
Application Number | 20130181259 13/348766 |
Document ID | / |
Family ID | 48779379 |
Filed Date | 2013-07-18 |
United States Patent
Application |
20130181259 |
Kind Code |
A1 |
Rao; Xuesong ; et
al. |
July 18, 2013 |
STEP-LIKE SPACER PROFILE
Abstract
Interlayer dielectric gap fill processes are enhanced by forming
gate spacers with a step-like or tapered profile. Embodiments
include forming a gate electrode on a substrate, depositing a
spacer material over the gate electrode, etching the spacer
material to form a first spacer on each side of the gate electrode,
and pulling back the first spacers to form second spacers which
have a step-like profile. Embodiments further include depositing a
second spacer material over the gate electrode and the second
spacers, and etching the second spacer material to form a third
spacer on each second spacer, the second and third spacers forming
an outwardly tapered composite spacer.
Inventors: |
Rao; Xuesong; (Singapore,
SG) ; Seet; Chim Seng; (Singapore, SG) ; Cong;
Hai; (Singapore, SG) ; Zou; Zheng; (Singapore,
SG) ; See; Alex; (Singapore, SG) ; Tan; Yun
Ling; (Singapore, SG) ; Zhou; Wen Zhan;
(Singapore, SG) ; Leong; Lup San; (Singapore,
SG) ; Liu; Huang; (Singapore, SG) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Rao; Xuesong
Seet; Chim Seng
Cong; Hai
Zou; Zheng
See; Alex
Tan; Yun Ling
Zhou; Wen Zhan
Leong; Lup San
Liu; Huang |
Singapore
Singapore
Singapore
Singapore
Singapore
Singapore
Singapore
Singapore
Singapore |
|
SG
SG
SG
SG
SG
SG
SG
SG
SG |
|
|
Assignee: |
GLOBAL FOUNDRIES Singapore Pte.
Ltd.
|
Family ID: |
48779379 |
Appl. No.: |
13/348766 |
Filed: |
January 12, 2012 |
Current U.S.
Class: |
257/288 ;
257/E21.158; 257/E29.255; 438/585 |
Current CPC
Class: |
H01L 29/78 20130101;
H01L 29/6656 20130101 |
Class at
Publication: |
257/288 ;
438/585; 257/E29.255; 257/E21.158 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 21/28 20060101 H01L021/28 |
Claims
1. A method comprising: forming a gate electrode on a substrate;
depositing a low temperature oxide (LTO) spacer material over the
gate electrode; etching the LTO spacer material to form a first
spacer on each side of the gate electrode; and pulling back the
first spacers to form second spacers.
2. The method according to claim 1, further comprising: depositing
a second spacer material over the gate electrode and the second
spacers; and etching the second spacer material to form a third
spacer on each second spacer, the second and third spacers forming
an outwardly tapered composite spacer.
3. The method according to claim 2, comprising depositing low
temperature LTO for the second spacer material.
4. The method according to claim 3, comprising pulling back the
first spacers by wet cleaning.
5. The method according to claim 4, comprising wet cleaning by
applying a dilute hydrogen fluoride (dHF).
6. The method according to claim 5, comprising etching the second
spacer material by reactive ion etching (RIE).
7. The method according to claim 6, further comprising: a second
wet cleaning; depositing a third spacer material over the gate
electrodes, second spacers, and third spacers; and etching the
third spacer material to form a fourth spacer on each third spacer,
the second, third, and fourth spacers forming an outwardly tapered
composite spacer.
8. The method according to claim 1, further comprising: depositing
a resist on the gate electrode and first spacers; and etching away
a portion of the resist prior to pulling back the first
spacers.
9. The method according to claim 8, comprising pulling back the
first spacers by wet etching and stripping the resist.
10. The method according to claim 9, wherein the resist comprises a
spin-on resist.
11. The method according to claim 8, comprising pulling back the
first spacers to a height of 40 nm to 120 nm and having a vertical
portion having a height of 30 nm to 110 nm.
12. A device comprising: a substrate; a gate electrode on the
substrate; and a spacer comprising a low temperature oxide (LTO) on
each side of the gate electrode, wherein each spacer has a tapered
or step-like profile.
13. The device according to claim 12, wherein each spacer has a
height less than a height of the gate electrode.
14. The device according to claim 12, wherein each spacer
comprises: a first spacer having a height less than a height of the
gate electrode; and a second spacer, on the first spacer.
15. The device according to claim 14, wherein the second spacers
each comprise a LTO.
16. The device according to claim 15, wherein the first and second
spacers each have a width of 50 .ANG. to 250 .ANG..
17. The device according to claim 12, wherein each spacer comprises
a composite spacer of three to five spacers, the spacer closest to
the gate electrode having a height less than a height of the gate
electrode, and the composite spacer having substantially no
vertical portion.
18. A method comprising: forming at least two gate electrodes on a
substrate; depositing a low temperature oxide (LTO) over the gate
electrodes; etching the LTO to form a first spacer on each side of
each gate electrode; pulling back the first spacers to form second
spacers, wherein a profile of the second spacers is more angled
than a profile of the first spacers; and depositing an interlayer
dielectric (ILD) on and between the at least two gate
electrodes.
19. The method according to claim 18, comprising pulling back the
first spacers by: depositing a spin-on resist on the gate
electrodes and first spacers; etching away a portion of the spin-on
resist; wet etching; and stripping the spin-on resist.
20. The method according to claim 18, wherein the first spacers are
pulled back by wet cleaning by applying a dilute hydrogen fluoride
(dHF), the method further comprising: depositing a second LTO over
the gate electrode and the second spacers; and reactive ion etching
(RIE) the second LTO to form a third spacer on each second spacer,
the second and third spacers forming an outwardly tapered composite
spacer.
Description
TECHNICAL FIELD
[0001] The present disclosure relates to methods for forming
semiconductor gate spacers having a tapered or step-like profile.
The present disclosure is particularly applicable to 40 nanometer
(nm) technology nodes and beyond.
BACKGROUND
[0002] As the dimensions of semiconductor devices continue to
shrink, the spacing between adjacent polysilicon gates decreases,
the aspect ratio of the gaps between the gates increases, and
filling of the gaps with a dielectric material becomes very
challenging. As the gaps are actually formed between spacers of
adjacent gates, the spacer profile is a key factor in a
high-quality gap fill. Conventional spacers generally result in a
substantially uniform gap width, leading to voids in the filled
dielectric material. Voids in the interlayer dielectric (ILD) may
cause shorts between drain contacts or between source contacts,
thereby degrading device performance.
[0003] Achieving a void-free gap fill of dielectric material is
particularly difficult between double-poly gates, for example
having a height about 200 nanometers (nm), with tight spacing, e.g.
having a minimum spacing of 108 nm, in a typical embedded
non-volatile memory (eNVM) process flow. Adverting to FIG. 1A, each
gate 101 includes a sidewall spacer 103 having an upper portion 105
and a lower portion 107. The lower portion may be characterized by
sidewall angle 109, space 111, and height 113. As illustrated in
FIG. 1B, when an ILD 115 is deposited over and between two adjacent
gates 101, a void 117 is formed. Current process flows, such as
deposition of a low temperature oxide (LTO) 201 to a thickness of
500 angstroms (.ANG.) over gate 203 (as illustrated in FIG. 2A)
followed by etching, produce a sidewall spacer profile 205 (as
illustrated in FIG. 2B) with a large, substantially vertical, lower
portion 207, for example having a height of 120 nm to 180 nm. The
significant vertical portion is not favored by current ILD gap fill
processes, such as a high aspect ratio process (HARP), causing
formation of voids 117 during ILD gap fill.
[0004] A need therefore exists for methodology enabling formation
of gate spacers having a tapered or step-like profile, and the
resulting device.
SUMMARY
[0005] An aspect of the present disclosure is a method of forming a
semiconductor device having gate spacers with a step-like or
tapered profile.
[0006] Another aspect of the present disclosure is semiconductor
device having gate spacers with a step-like or tapered profile.
[0007] Additional aspects and other features of the present
disclosure will be set forth in the description which follows and
in part will be apparent to those having ordinary skill in the art
upon examination of the following or may be learned from the
practice of the present disclosure. The advantages of the present
disclosure may be realized and obtained as particularly pointed out
in the appended claims.
[0008] According to the present disclosure, some technical effects
may be achieved in part by a method including: forming a gate
electrode on a substrate; depositing a spacer material over the
gate electrode; etching the spacer material to form a first spacer
on each side of the gate electrode; and pulling back the first
spacers to form second spacers.
[0009] Aspects of the present disclosure include depositing a
second spacer material over the gate electrode and the second
spacers; and etching the second spacer material to form a third
spacer on each second spacer, the second and third spacers forming
an outwardly tapered composite spacer. Further aspects include
depositing low temperature oxides (LTO) for the first and second
spacer materials. Other aspects include pulling back the first
spacers by wet cleaning, such as by applying a dilute hydrogen
fluoride (dHF). Another aspect includes etching the second spacer
material by reactive ion etching (RIE). Additional aspects include
a second wet cleaning; depositing a third spacer material over the
gate electrodes, second spacers, and third spacers; and etching the
third spacer material to form a fourth spacer on each third spacer,
the second, third, and fourth spacers forming an outwardly tapered
composite spacer. Further aspects include depositing a resist, such
as a spin-on resist, on the gate electrode and first spacers; and
etching away a portion of the resist prior to pulling back the
first spacers. Other aspects include pulling back the first spacers
by wet etching and stripping the resist.
[0010] Another aspect of the present disclosure is a device
including: a substrate; a gate electrode on the substrate; and a
spacer on each side of the gate electrode, wherein each spacer has
a tapered or step-like profile.
[0011] Aspects include each spacer having a height less than a
height of the gate electrode. Further aspects include each spacer
including: a first spacer having a height less than a height of the
gate electrode; and a second spacer, on the first spacer. Another
aspect includes the first and second spacers each being formed of
an LTO. Other aspects include the first and second spacers each
having a width of 50 .ANG. to 250 .ANG.. Additional aspects include
each spacer being a composite spacer of three to five spacers, the
spacer closest to the gate electrode having a height less than a
height of the gate electrode, and the composite spacer having
substantially no vertical portion.
[0012] Another aspect of the present disclosure is a method
including: forming at least two gate electrodes on a substrate;
depositing a low temperature oxide (LTO) over the gate electrodes;
etching the LTO to form a first spacer on each side of each gate
electrode; pulling back the first spacers to form second spacers,
wherein a profile of the second spacers is more angled than a
profile of the first spacers; and depositing an interlayer
dielectric (ILD) on and between the at least two gate
electrodes.
[0013] Aspects include pulling back the first spacers by:
depositing a spin-on resist on the gate electrodes and first
spacers; etching away a portion of the spin-on resist; wet etching;
and stripping the spin-on resist. Other aspects include the first
spacers being pulled back by wet cleaning by applying a dilute
hydrogen fluoride (dHF), the method further including: depositing a
second LTO over the gate electrode and the second spacers; and
reactive ion etching (RIE) the second LTO to form a third spacer on
each second spacer, the second and third spacers forming an
outwardly tapered composite spacer.
[0014] Additional aspects and technical effects of the present
disclosure will become readily apparent to those skilled in the art
from the following detailed description wherein embodiments of the
present disclosure are described simply by way of illustration of
the best mode contemplated to carry out the present disclosure. As
will be realized, the present disclosure is capable of other and
different embodiments, and its several details are capable of
modifications in various obvious respects, all without departing
from the present disclosure. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The present disclosure is illustrated by way of example, and
not by way of limitation, in the figures of the accompanying
drawing and in which like reference numerals refer to similar
elements and in which:
[0016] FIGS. 1A and 1B schematically illustrate a model for current
ILD gap fill;
[0017] FIGS. 2A and 2B schematically illustrate a current process
flow for forming gate spacers;
[0018] FIGS. 3 through 5 schematically illustrate a process flow
for fabricating a semiconductor device having gate spacers with a
tapered profile, in accordance with an exemplary embodiment;
and
[0019] FIGS. 6 through 11 schematically illustrate a process flow
for fabricating a semiconductor device having gate spacers with a
step-like profile, in accordance with another exemplary
embodiment.
DETAILED DESCRIPTION
[0020] In the following description, for the purposes of
explanation, numerous specific details are set forth in order to
provide a thorough understanding of exemplary embodiments. It
should be apparent, however, that exemplary embodiments may be
practiced without these specific details or with an equivalent
arrangement. In other instances, well-known structures and devices
are shown in block diagram form in order to avoid unnecessarily
obscuring exemplary embodiments. In addition, unless otherwise
indicated, all numbers expressing quantities, ratios, and numerical
properties of ingredients, reaction conditions, and so forth used
in the specification and claims are to be understood as being
modified in all instances by the term "about."
[0021] The present disclosure addresses and solves the current
problem of void formation attendant upon current gap fill processes
between adjacent semiconductor gates. In accordance with
embodiments of the present disclosure, gate spacers are formed with
a tapered profile or with a step-like profile to minimize the
vertical portion therebetween. The resulting gap has a large
opening in the upper portion and a narrow gap in the lower portion,
thereby reducing void formation during gap filling.
[0022] Methodology in accordance with embodiments of the present
disclosure includes forming a gate electrode on a substrate,
depositing a spacer material over the gate electrode, etching the
spacer material to form a first spacer on each side of the gate
electrode, and pulling back the first spacers to form second
spacers.
[0023] Still other aspects, features, and technical effects will be
readily apparent to those skilled in this art from the following
detailed description, wherein preferred embodiments are shown and
described, simply by way of illustration of the best mode
contemplated. The disclosure is capable of other and different
embodiments, and its several details are capable of modifications
in various obvious respects. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
as restrictive.
[0024] The initial process flow in accordance with an exemplary
embodiment is the same as that illustrated in FIGS. 2A and 2B.
Specifically, an LTO layer 201 is deposited over gate 203 to a
thickness of 100 .ANG. to 500 .ANG. followed by a reactive ion etch
(RIE) to form spacers 205. Gate 203 may, for example, be part of a
high voltage (HV) transistor or may be part of an eNVM formed on
the same chip. Spacers 205 have a width of 100 .ANG. to 500 .ANG.
and a substantially vertical lower portion having a height of 120
nm to 180 nm, in which a larger spacer width corresponds to a
shorter lower portion and a more tapered profile.
[0025] Adverting to FIG. 3, the spacers are then pulled back, for
example by etching, to about half the spacer width, for example to
a width of 50 .ANG. to 250 .ANG., to form spacers 301. The etching
may be performed with a wet clean step, for example using diluted
hydrofluoric acid (dHF). The wet clean not only reduces the spacer
width, but also reduces the spacer height. For example, 200 .ANG.
of dHF will correspondingly reduce the spacer height by 200
.ANG..
[0026] As illustrated in FIG. 4, a second LTO layer 401 is
deposited over spacers 301 and gate 203. LTO layer 401 may be
deposited to a thickness of 50 .ANG. to 250 .ANG., for example 250
.ANG..
[0027] A second spacer RIE is then performed, forming spacers 501,
as illustrated in FIG. 5. The resulting spacers have a lower
portion 503 having a height of 60 nm to 120 nm, which is less than
current spacers, and a sidewall angle between 60.degree. and
90.degree., which is more tapered and gap-fill friendly than
current spacers. The minimum space between adjacent spacers may be
less than 10 nm. A stress proximity technique (SPT) may also be
applied after formation of the spacers. The longer the SPT, the
larger the spacing and the better the profile for the lower part of
the gap for a subsequent ILD deposition. In other words, a longer
SPT improves the ILD gap fill. The steps illustrated in FIGS. 3
through 5 may be repeated multiple times, for example one to three
times, to further reduce the vertical portion of the spacers.
[0028] Adverting to FIGS. 6 through 11, a process flow for forming
spacers with a shorter lower portion in accordance with another
exemplary embodiment is illustrated. FIGS. 6 through 8 illustrate a
conventional process flow, and FIGS. 9 through 11 show the
additional steps in accordance with the exemplary embodiment. As
shown in FIG. 6, double poly gates 601 are each formed with a top
control gate (CG), a bottom floating gate (FG), and an
oxide-nitride-oxide (ONO) layer therebetween.
[0029] As illustrated in FIG. 7, a thin etch stop layer 701, is
formed over gates 601 to a thickness of, for example, 300 .ANG..
Over etch stop layer 701, a layer of spacer material 703 may be
deposited, to a thickness of 5 nm to 15 nm. Spacer material layer
703 may, for example, be formed of an LTO. The LTO is then etched,
for example by RIE, as illustrated in FIG. 8, forming spacers 801.
As shown, conventional spacers 801 have a large vertical portion,
for example 120 nm to 180 nm.
[0030] Adverting to FIG. 9, the gates 601 are covered with a
spin-on resist 901. Resist 901 may then be etched back to a height
of 40 nm to 120 nm forming resist portions 1001. A wet etch, for
example by application of dHF, is performed, and the spin-on resist
is stripped, forming spacers 1101 having a height of 40 nm to 120
nm, with a vertical portion of 30 nm to 110 nm. As a result,
spacers 1101 have a more tapered profile than conventional spacers
801, making them more favorable for the subsequent ILD gap fill
process.
[0031] The embodiments of the present disclosure can achieve
several technical effects, including reducing the vertical portion
of gate spacers, thereby facilitating ILD gap fill and reducing ILD
voids. Devices formed in accordance with embodiments of the present
disclosure enjoy utility in various industrial applications, e.g.,
microprocessors, smart phones, mobile phones, cellular handsets,
set-top boxes, DVD recorders and players, automotive navigation,
printers and peripherals, networking and telecom equipment, gaming
systems, and digital cameras. The present disclosure therefore
enjoys industrial applicability in any of various types of highly
integrated semiconductor devices.
[0032] In the preceding description, the present disclosure is
described with reference to specifically exemplary embodiments
thereof. It will, however, be evident that various modifications
and changes may be made thereto without departing from the broader
spirit and scope of the present disclosure, as set forth in the
claims. The specification and drawings are, accordingly, to be
regarded as illustrative and not as restrictive. It is understood
that the present disclosure is capable of using various other
combinations and embodiments and is capable of any changes or
modifications within the scope of the inventive concept as
expressed herein.
* * * * *