See; Alex

Patent Applications and Registrations

Patent applications and USPTO patent grants for See; Alex.The latest application filed is for "integrated two-terminal device with logic device for embedded application".

Company Profile

5.77.64

See; Alex - Singapore SG
See; Alex - Woodlands SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated two-terminal device with logic device for embedded application Grant 10,608,046 - Yi , et al.	2020-03-31
Integrated Two-terminal Device With Logic Device For Embedded Application App 20190326352 - YI; Wanbing ; et al.	2019-10-24
Integrated two-terminal device with logic device for embedded application Grant 10,446,607 - Yi , et al. Oc	2019-10-15
Method and device for reducing contamination for reliable bond pads Grant 10,410,854 - Mou , et al. Sept	2019-09-10
Method And Device For Reducing Contamination For Reliable Bond Pads App 20190206676 - MOU; Honghui ; et al.	2019-07-04
Methods for removal of hard mask Grant 10,115,625 - Li , et al. October 30, 2	2018-10-30
CD control Grant 10,103,097 - Zou , et al. October 16, 2	2018-10-16
Methods For Removal Of Hard Mask App 20180190537 - LI; Liang ; et al.	2018-07-05
Integrated Two-terminal Device With Logic Device For Embedded Application App 20180182810 - YI; Wanbing ; et al.	2018-06-28
Integrated circuits with overlay marks and methods of manufacturing the same Grant 9,646,934 - Wang , et al. May 9, 2	2017-05-09
CMP wafer edge control of dielectric Grant 9,627,219 - Wang , et al. April 18, 2	2017-04-18
Methods for fabricating integrated circuits with improved active regions Grant 9,620,418 - Li , et al. April 11, 2	2017-04-11
Integrated circuits having nickel silicide contacts and methods for fabricating the same Grant 9,548,371 - Huang , et al. January 17, 2	2017-01-17
Small pitch and high density contact array Grant 9,543,502 - Zou , et al. January 10, 2	2017-01-10
Integrated circuits with memory cells and methods of manufacturing the same Grant 9,537,092 - Zou , et al. January 3, 2	2017-01-03
Planar passivation for pads Grant 9,520,371 - Lin , et al. December 13, 2	2016-12-13
CMP head structure with retaining ring Grant 9,511,470 - Lin , et al. December 6, 2	2016-12-06
CMP head structure with retaining ring Grant 9,511,474 - Lin , et al. December 6, 2	2016-12-06
Integrated Circuits With Overlay Marks And Methods Of Manufacturing The Same App 20160351507 - Wang; Shijie ; et al.	2016-12-01
Small Pitch And High Density Contact Array App 20160351791 - ZOU; Zheng ; et al.	2016-12-01
Integrated Circuits With Memory Cells And Methods Of Manufacturing The Same App 20160284991 - Zou; Zheng ; et al.	2016-09-29
Through silicon vias Grant 9,437,547 - Lin , et al. September 6, 2	2016-09-06
Slot Designs In Wide Metal Lines App 20160233157 - LIM; Yeow Kheng ; et al.	2016-08-11
Through Silicon Vias App 20160190066 - LIN; Benfu ; et al.	2016-06-30
Isolation for embedded devices Grant 9,349,654 - Li , et al. May 24, 2	2016-05-24
Cmp Head Structure App 20160136774 - LIN; Benfu ; et al.	2016-05-19
Cmp Head Structure App 20160136781 - Lin; Benfu ; et al.	2016-05-19
Methods For Fabricating Integrated Circuits With Improved Active Regions App 20160133524 - Li; Liang ; et al.	2016-05-12
Uniform Polishing With Fixed Abrasive Pad App 20160114457 - LEONG; Lup San ; et al.	2016-04-28
Planar Passivation For Pads App 20160118355 - LIN; Benfu ; et al.	2016-04-28
Slot designs in wide metal lines Grant 9,318,378 - Lim , et al. April 19, 2	2016-04-19
Through silicon vias Grant 9,287,197 - Lin , et al. March 15, 2	2016-03-15
CMP head structure Grant 9,242,341 - Lin , et al. January 26, 2	2016-01-26
Integrated circuits with memory cells and methods of manufacturing the same Grant 9,209,275 - Zou , et al. December 8, 2	2015-12-08
Integrated circuits with improved gap fill dielectric and methods for fabricating same Grant 9,202,746 - Wang , et al. December 1, 2	2015-12-01
Integrated Circuits Having Nickel Silicide Contacts And Methods For Fabricating The Same App 20150311221 - Huang; Jingyan ; et al.	2015-10-29
Cmp Wafer Edge Control Of Dielectric App 20150303068 - WANG; Lei ; et al.	2015-10-22
Isolation For Embedded Devices App 20150279743 - LI; Liang ; et al.	2015-10-01
Integrated Circuits With Improved Gap Fill Dielectric And Methods For Fabricating Same App 20150187641 - Wang; Lei ; et al.	2015-07-02
Filament free silicide formation Grant 9,023,725 - Yeo , et al. May 5, 2	2015-05-05
Cmp Head Structure App 20150111467 - LIN; Benfu ; et al.	2015-04-23
Cmp Head Structure App 20150111469 - LIN; Benfu ; et al.	2015-04-23
Cd Control App 20140374920 - ZOU; Zheng ; et al.	2014-12-25
STI CMP under polish monitoring Grant 8,852,968 - Li , et al. October 7, 2	2014-10-07
Through Silicon Vias App 20140264911 - LIN; Benfu ; et al.	2014-09-18
CD control Grant 8,836,139 - Zou , et al. September 16, 2	2014-09-16
Spacer profile engineering using films with continuously increased etch rate from inner to outer surface Grant 8,828,858 - Rao , et al. September 9, 2	2014-09-09
Sti Cmp Under Polish Monitoring App 20140234993 - LI; Liang ; et al.	2014-08-21
Integrated circuit with self-aligned line and via Grant 8,766,454 - Lim , et al. July 1, 2	2014-07-01
Filament Free Silicide Formation App 20140167121 - YEO; Kwee Liang ; et al.	2014-06-19
Copper Hillock Prevention With Hydrogen Plasma Treatment In A Dedicated Chamber App 20140117545 - LIU; Huang ; et al.	2014-05-01
Cd Control App 20140110855 - ZOU; Zheng ; et al.	2014-04-24
Methods of protecting elevated polysilicon structures during etching processes Grant 8,569,173 - Li , et al. October 29, 2	2013-10-29
Spacer Profile Engineering Using Films With Continuously Increased Etch Rate From Inner To Outer Surface App 20130187202 - Rao; Xuesong ; et al.	2013-07-25
Step-like spacer profile Grant 8,492,236 - Rao , et al. July 23, 2	2013-07-23
Step-like Spacer Profile App 20130181259 - Rao; Xuesong ; et al.	2013-07-18
Methods of Protecting Elevated Polysilicon Structures During Etching Processes App 20130149851 - Li; Liang ; et al.	2013-06-13
Through Silicon Via For Stacked Wafer Connections App 20130119543 - YU; Hong ; et al.	2013-05-16
Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing Grant 8,324,011 - Poon , et al. December 4, 2	2012-12-04
Grain boundary blocking for stress migration and electromigration improvement in CU interconnects Grant 7,989,338 - Zhang , et al. August 2, 2	2011-08-02
Combined copper plating method to improve gap fill Grant 7,585,768 - Bu , et al. September 8, 2	2009-09-08
Implementation Of Temperature-dependent Phase Switch Layer For Improved Temperature Uniformity During Annealing App 20090068825 - POON; CHYIU HYIA ; et al.	2009-03-12
Combined copper plating method to improve gap fill App 20070293039 - Bu; Xiaomei ; et al.	2007-12-20
Integrated Circuit With Self-aligned Line And Via App 20070075371 - Lim; Yeow Kheng ; et al.	2007-04-05
Grain boundary blocking for stress migration and electromigration improvement in CU interconnects App 20060286797 - Zhang; Fan ; et al.	2006-12-21
Integrated circuit with self-aligned line and via and manufacturing method therefor Grant 7,119,010 - Lim , et al. October 10, 2	2006-10-10
Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal Grant 7,112,499 - Poon , et al. September 26, 2	2006-09-26
Structure and method of liner air gap formation Grant 7,094,669 - Bu , et al. August 22, 2	2006-08-22
Process flow for a performance enhanced MOSFET with self-aligned, recessed channel Grant 7,091,092 - Sneelal , et al. August 15, 2	2006-08-15
Method and apparatus for performing nickel salicidation Grant 7,030,451 - Lee , et al. April 18, 2	2006-04-18
Slot designs in wide metal lines App 20060040491 - Lim; Yeow Kheng ; et al.	2006-02-23
Structure and method of liner air gap formation App 20060030128 - Bu; Xiaomei ; et al.	2006-02-09
Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal App 20050158956 - Poon, Chyiu Hyia ; et al.	2005-07-21
Method and apparatus for performing nickel salicidation App 20050156269 - Lee, Pooi See ; et al.	2005-07-21
Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer Grant 6,905,964 - Lim , et al. June 14, 2	2005-06-14
Method for forming a region of low dielectric constant nanoporous material using a microemulsion technique Grant 6,899,857 - Pheng , et al. May 31, 2	2005-05-31
Method of multiple pulse laser annealing to activate ultra-shallow junctions Grant 6,897,118 - Poon , et al. May 24, 2	2005-05-24
Method and apparatus for performing nickel salicidation Grant 6,890,854 - Lee , et al. May 10, 2	2005-05-10
Technique to achieve thick silicide film for ultra-shallow junctions Grant 6,878,623 - Tan , et al. April 12, 2	2005-04-12
Dual silicon-on-insulator device wafer die Grant 6,849,928 - Cha , et al. February 1, 2	2005-02-01
Method to form C54 TiSi2 for IC device fabrication Grant 6,777,329 - Chen , et al. August 17, 2	2004-08-17
Method of forming a high K metallic dielectric layer Grant 6,764,914 - See , et al. July 20, 2	2004-07-20
Replacement of silicon nitride copper barrier with a self-aligning metal barrier App 20040137721 - Lim, Boon Kiat ; et al.	2004-07-15
Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure Grant 6,734,072 - Chong , et al. May 11, 2	2004-05-11
Method to fabricate elevated source/drain structures in MOS transistors Grant 6,727,151 - Chong , et al. April 27, 2	2004-04-27
Method To Fabricate Elevated Source/drain Structures In Mos Transistors App 20040029320 - Chong, Yung Fu ; et al.	2004-02-12
Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant Grant 6,680,239 - Cha , et al. January 20, 2	2004-01-20
Parallel spiral stacked inductor on semiconductor material Grant 6,650,220 - Sia , et al. November 18, 2	2003-11-18
Novel technique to achieve thick silicide film for ultra-shallow junctions App 20030207565 - Tan, Cheng Cheh ; et al.	2003-11-06
Method for obtaining clean silicon surfaces for semiconductor manufacturing Grant 6,638,365 - Ye , et al. October 28, 2	2003-10-28
Integrated circuit with self-aligned line and via and manufacturing method therefor App 20030197279 - Lim, Yeow Kheng ; et al.	2003-10-23
Parallel Spiral Stacked Inductor On Semiconductor Material App 20030197586 - Sia, Choon-Beng ; et al.	2003-10-23
Method of gate patterning for sub-0.1 .mu.m technology Grant 6,630,405 - Hong , et al. October 7, 2	2003-10-07
Formation of silicided shallow junctions using implant through metal technology and laser annealing process Grant 6,624,489 - Chong , et al. September 23, 2	2003-09-23
Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance Grant 6,613,652 - Lim , et al. September 2, 2	2003-09-02
Method for buffer STI scheme with a hard mask layer as an oxidation barrier Grant 6,613,649 - Lim , et al. September 2, 2	2003-09-02
Method for forming a region of low dielectric constant nanoporous material Grant 6,602,801 - Kong , et al. August 5, 2	2003-08-05
Dual silicon-on-insulator device wafer die App 20030107083 - Cha, Randall Cher Liang ; et al.	2003-06-12
Method for buffer STI scheme with a hard mask layer as an oxidation barrier App 20030104675 - Lim, Seng-Keong Victor ; et al.	2003-06-05
Method of forming a high K metallic dielectric layer App 20030104673 - See, Alex ; et al.	2003-06-05
Method For Forming A Region Of Low Dielectric Constant Nanoporous Material App 20030092240 - Kong, Siew Yong ; et al.	2003-05-15
Method for forming a region of low dielectric constant nanoporous material using a microemulsion technique App 20030092251 - Pheng, Soo Choi ; et al.	2003-05-15
Dual silicon-on-insulator device wafer die Grant 6,558,994 - Cha , et al. May 6, 2	2003-05-06
Method for obtaining clean silicon surfaces for semiconductor manufacturing App 20030069151 - Ye, Jianhui ; et al.	2003-04-10
Method of forming of high K metallic dielectric layer Grant 6,492,242 - See , et al. December 10, 2	2002-12-10
Novel method to form C54 TiSi2 for IC device fabrication App 20020155703 - Chen, Shaoyin ; et al.	2002-10-24
Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance App 20020132448 - Lim, Yeow Kheng ; et al.	2002-09-19
Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application App 20020127834 - Lim, Yeow Kheng ; et al.	2002-09-12
Dual silicon-on-insulator device wafer die App 20020127816 - Cha, Randall Cher Liang ; et al.	2002-09-12
Method for pre-STI-CMP planarization using poly-si thermal oxidation Grant 6,436,833 - Pang , et al. August 20, 2	2002-08-20
Novel technique to achieve thick silicide film for ultra-shallow junctions App 20020102802 - Tan, Cheng Cheh ; et al.	2002-08-01
Formation of silicided shallow junctions using implant through metal technology and laser annealing process App 20020098689 - Chong, Yung Fu ; et al.	2002-07-25
Simplified Method To Reduce Or Eliminate Sti Oxide Divots App 20020098661 - Cha, Randall Cher Liang ; et al.	2002-07-25
Process flow for a performance enhanced MOSFET with self-aligned, recessed channel App 20020094622 - Sneelal, Sneedharan Pillai ; et al.	2002-07-18
Method for fabricating an air gap shallow trench isolation (STI) structure Grant 6,406,975 - Lim , et al. June 18, 2	2002-06-18
Method and apparatus for performing nickel salicidation App 20020064918 - Lee, Pooi See ; et al.	2002-05-30
Activating source and drain junctions and extensions using a single laser anneal Grant 6,391,731 - Chong , et al. May 21, 2	2002-05-21
Method to fabricate RF inductors with minimum area Grant 6,387,747 - Cha , et al. May 14, 2	2002-05-14
Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures Grant 6,380,106 - Lim , et al. April 30, 2	2002-04-30
Method to form high performance copper damascene interconnects by de-coupling via and metal line filling Grant 6,380,084 - Lim , et al. April 30, 2	2002-04-30
Methods for eliminating metal corrosion by FSG Grant 6,380,066 - See , et al. April 30, 2	2002-04-30
Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process Grant 6,365,446 - Chong , et al. April 2, 2	2002-04-02
Versatile copper-wiring layout design with low-k dielectric integration Grant 6,355,563 - Cha , et al. March 12, 2	2002-03-12
Method to form MOS transistors with shallow junctions using laser annealing Grant 6,335,253 - Chong , et al. January 1, 2	2002-01-01
Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique Grant 6,319,767 - Cha , et al. November 20, 2	2001-11-20
Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer Grant 6,303,418 - Cha , et al. October 16, 2	2001-10-16
Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill Grant 6,281,082 - Chen , et al. August 28, 2	2001-08-28
Method of forming contact to polysilicon gate for MOS devices Grant 6,261,935 - See , et al. July 17, 2	2001-07-17
Method to form transistors and local interconnects using a silicon nitride dummy gate technique Grant 6,204,137 - Teo , et al. March 20, 2	2001-03-20

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