U.S. patent application number 13/251987 was filed with the patent office on 2013-04-04 for interposer for esd, emi, and emc.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is WILLIAM E. BERNIER, BING DANG, MARIO J. INTERRANTE, JOHN U. KNICKERBOCKER, SON K. TRAN. Invention is credited to WILLIAM E. BERNIER, BING DANG, MARIO J. INTERRANTE, JOHN U. KNICKERBOCKER, SON K. TRAN.
Application Number | 20130082365 13/251987 |
Document ID | / |
Family ID | 47991790 |
Filed Date | 2013-04-04 |
United States Patent
Application |
20130082365 |
Kind Code |
A1 |
BERNIER; WILLIAM E. ; et
al. |
April 4, 2013 |
Interposer for ESD, EMI, and EMC
Abstract
A interposer sandwich structure comprises a top interposer and a
bottom interposer enclosing an integrated circuit electronic device
that includes means for attaching the device to the bottom
interposer, and an interconnection structure connecting the top
interposer to the bottom interposer. The top interposer may also be
directly connected to a chip carrier in addition to the bottom
interposer. The structure provides shielding and protection of the
device against Electrostatic Discharge (ESD), Electromagnetic
Interference (EMI), and Electromagnetic Conductivity (EMC) in
miniaturized 3D packaging.
Inventors: |
BERNIER; WILLIAM E.;
(Armonk, NY) ; DANG; BING; (Armonk, NY) ;
INTERRANTE; MARIO J.; (Armonk, NY) ; KNICKERBOCKER;
JOHN U.; (Armonk, NY) ; TRAN; SON K.; (Armonk,
NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
BERNIER; WILLIAM E.
DANG; BING
INTERRANTE; MARIO J.
KNICKERBOCKER; JOHN U.
TRAN; SON K. |
Armonk
Armonk
Armonk
Armonk
Armonk |
NY
NY
NY
NY
NY |
US
US
US
US
US |
|
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
47991790 |
Appl. No.: |
13/251987 |
Filed: |
October 3, 2011 |
Current U.S.
Class: |
257/659 ;
257/E23.114 |
Current CPC
Class: |
H01L 23/49833 20130101;
H01L 2924/01029 20130101; H01L 2924/14 20130101; H01L 2924/15787
20130101; H01L 2924/1579 20130101; H01L 23/60 20130101; H01L
2924/19105 20130101; H01L 2924/01014 20130101; H01L 23/49816
20130101; H01L 2924/15331 20130101; H01L 23/49827 20130101; H01L
2924/15738 20130101; H01L 24/81 20130101; H01L 2224/81192 20130101;
H01L 2924/00 20130101; H01L 2924/1461 20130101; H01L 25/0655
20130101; H01L 2924/15192 20130101; H01L 23/552 20130101; H01L
23/367 20130101; H01L 2924/01082 20130101; H01L 2924/0105 20130101;
H01L 2924/01047 20130101; H01L 2924/15311 20130101; H01L 2924/014
20130101; H01L 2924/01028 20130101; H01L 24/09 20130101; H01L
2924/1461 20130101; H01L 2924/1433 20130101; H01L 2224/16225
20130101; H01L 2224/08238 20130101 |
Class at
Publication: |
257/659 ;
257/E23.114 |
International
Class: |
H01L 23/552 20060101
H01L023/552 |
Claims
1. An interposer sandwich structure article of manufacture
comprising a top interposer and a bottom interposer enclosing an
integrated circuit electronic device, an attaching structure for
attaching said device to said bottom interposer, and an
interconnection structure connecting said top interposer to said
bottom interposer.
2. The article of manufacture of claim 1 wherein said attaching
structure for attaching said device to said bottom interposer
comprise small metal bumps and said interconnection structure
comprises large metal bumps extending from said top interposer and
fused with small metal bumps extending from said bottom
interposer.
3. The article of manufacture of claim 1 wherein said attaching
structure for attaching said device to said bottom interposer
comprise small solder bumps and said interconnection structure
comprises large solder bumps extending from said top interposer an
fused with small solder bumps extending from said bottom
interposer.
4. The article of manufacture of claim 1 wherein said attaching
structure for attaching said device to said bottom interposer
comprise small solder bumps and said interconnection structure
comprises large copper bumps extending from said top interposer and
fused with small solder bumps extending from said bottom
interposer.
5. The article of manufacture of claim 1 wherein said interposers
are selected from silicon interposers, ceramic interposers and
polymeric interposers and combinations thereof.
6. The article of manufacture of claim 1 wherein said interposers
comprise silicon interposers.
7. The article of manufacture of claim 1 wherein said top
interposer is also directly connected to a chip carrier.
8. The article of manufacture of claim 1 wherein said top
interposer includes a blanket metal coating on at least one of the
bottom or top surfaces of said top interposer.
9. The article of manufacture of claim 1 wherein said attaching
structure for attaching said device to said bottom interposer
comprises electrical connections to an electrical ground or
bias.
10. The article of manufacture of claim 1 wherein said top
interposer comprises connections to a chip carrier.
11. The article of manufacture of claim 10 wherein said connections
to said chip carrier comprises connections to an electrical ground
or bias.
12. The article of manufacture of claim 1 comprising a plurality of
said devices connected to said bottom interposer wherein said top
interposer is operatively associated with less than all of said
devices to provide selective functional isolation of said devices
for shielding for maximum miniaturization.
13. The article of manufacture of claim 1 comprising a thermal
interface material operatively associated with said device to
provide rapid heat dissipation from said device.
13. The article of manufacture of claim 12 comprising a thermal
interface material operatively associated with said devices to
provide rapid heat dissipation from said devices.
Description
FIELD OF THE INVENTION
[0001] The field of the invention comprises miniaturization of
electronics through 3D packaging structures incorporating
integrated circuit devices protected against Electrostatic
Discharge (ESD), Electromagnetic Interference (EMI), and
Electromagnetic Conductivity (EMC)
BACKGROUND OF THE INVENTION
[0002] Miniaturization of electronics is a continuously evolving
process in devices generated today. One way of achieving this is
with 3D packaging using interposers incorporating Through Silicon
Vias (TSV's). The TSV's allow a variety of additional function such
as capacitance, resistance, inductance, and simple circuitry to be
placed close to integrated circuits. These circuits are
interconnected electrically and supported structurally while
allowing efficient dissipation of heat. Such 3D packaging
structures incorporating integrated circuit devices need to be
protected from ESD which may damage or destroy circuitry, EMI from
emission sources in the nearby environment, and EMC resulting in
emission from the device requiring control so as to not interfere
with other devices.
[0003] As 3D packaging continues to advance in complexity, multiple
integrated circuit devices present on the same interposer silicon
carrier will require simple modes of separation and isolation from
ESD, EMI and EMC factors. Currently available technology can
achieve the necessary isolation and protection of integrated
circuit function but only at the cost of loss of the desired
miniaturization. Individual devices must be placed on isolated
interposers and large structures must be designed to shield and
protect the integrated circuit device function. These would be
constructed with base plates, lids, gaskets, and device separation
common in the industry for shielding and protection but this
defeats the enhancement of functional proximity otherwise afforded
by the interposer TSV 3D packaging.
RELATED ART
[0004] The following patents, published applications, and
literature exemplify the state of the art in the field of 3D
packaging: [0005] Barth, et al., United States Published Patent
Application No.2010/0078779; [0006] Morrison, et al., U.S. Pat. No.
7,709,915; [0007] DiBiene, et al., U.S. Pat. No. 7,245,507; [0008]
Lim, et al., IP.COM Technical Disclosure, IPCOM000169379D,
"Shielding and Interconnection Interposer Substrate", Apr. 24,
2008; [0009] Pelley, et al., U.S. Pat. No. 7,777,330; [0010] Lin,
et al., United States Published Patent Application No.
2010/0237386; [0011] Anthony, et al., U.S. Pat. No. 7,733,621;
[0012] England, et al., U.S. Pat. No. 7,622,786; [0013]
Hollingsworth, et al., U.S. Pat. No. 7,002,217; [0014] Neidich, et
al., U.S. Pat. No. 6,780,056.
SUMMARY OF THE INVENTION
[0015] The present invention comprises structures, articles of
manufacture, processes and products produced by the processes that
address the foregoing needs, and provides ESD, EMI and EMC
shielding and protection of integrated circuit devices in 3D
packaging. Examples of these devices comprise electronic devices
such as semiconductor chips, semiconductor arrays, or wafers, or IC
electronic components (integrated circuits, i.e., "IC chips") and
other components such as but not limited to
micro-electro-mechanical (MEMS) components, passive filters,
detector arrays, photovoltaic displays, organic light-emitting
diodes (OLEDs) and the like or SiGe, a III-V electronic device, or
opto-electronics.
[0016] In one embodiment, this innovative idea provides for ESD,
EMI and EMC shielding and protection of integrated circuit devices
in 3D packaging by creating a sandwich of interposers around the
integrated circuit device in which metallized shielding and diode
protective devices may be incorporated into both the top and bottom
interposers. TSV's would allow interconnection of the metallized
shielding to ground or voltage as required electrically, and the
bottom interposer in the sandwich connecting by TSV's and solder
connection to the chip carrier package, and the top interposer
connecting peripherally by TSV's beyond the outline of the
integrated circuit device to the bottom interposer which would then
connect electrically to the chip carrier. This would provide a
miniature localized cage around the device and preserve the scale
of integration and miniaturization desired with this
technology.
[0017] In addition, multiple integrated circuit devices, which
normally would need to be isolated in much larger or even separate
packages, now may be placed adjacent to one another on the same
interposer with TSV's by providing one or more top interposers to
isolate the sensitive devices from one another in close proximity
in the miniaturized sandwich package structure.
[0018] In one embodiment, the interposer sandwich structure as
shown in FIG. 1 comprises two interposers enclosing a device
requiring shielding or protection. A solder bump size hierarchy may
be used with smaller solder bumps attaching the integrated circuit
device to the interposer on the bottom, and larger solder bumps or
other interconnection structure connecting the top interposer with
the bottom interposer or directly with the chip carrier. The other
interconnection structure may comprise copper post bumps or
equivalent metal post bumps known in the art. In another
embodiment, these metal post bumps (e.g., copper) extends from
either the top or the bottom interposer toward a solder bump on the
bottom interposer for connecting the two by soldering. The height
of the structure is substantially the same whether employing solder
bumps or metal post bumps (e.g., copper). The combined height of
the bumps is about 50 um (microns), and the ratio of the heights of
the larger bumps to the smaller bumps is about 3:1.
[0019] The top interposer has a blanket metal coating on the bottom
or top surface and the connections to the bottom interposer or the
chip carrier would be to electrical ground or bias depending on the
function required. As shown in FIG. 2, one or more devices
connected to the bottom interposer may be shielded with a top
interposer selectively to provide the functional isolation for
shielding or protection desired, for maximum miniaturization.
Thermal interface material can be dispensed on the back of the
integrated circuit device prior to joining the top interposer in
order to provide for rapid heat dissipation from the integrated
circuit device if required.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings are not necessarily drawn to scale
but nonetheless set out the invention, and are included to
illustrate various embodiments of the invention, and together with
this specification also serve to explain the principles of the
invention. These drawings comprise various Figures that illustrate
ESD, EMI and EMC shielding and protection of integrated circuit
devices in 3D packaging.
[0021] FIGS. 1-2 comprise side elevations in cross-section
illustrating structures for ESD, EMI and EMC shielding and
protection of integrated circuit devices in 3D packaging.
DETAILED DESCRIPTION OF THE INVENTION
[0022] To achieve the foregoing and other advantages, and in
accordance with the purpose of this invention as embodied and
broadly described herein, the following detailed description
comprises disclosed examples of the invention that can be embodied
in various forms.
[0023] The specific processes, compounds, compositions, and
structural details set out herein not only comprise a basis for the
claims and a basis for teaching one skilled in the art to employ
the present invention in any novel and useful way, but also provide
a description of how to make and use this invention. The written
description, claims, abstract of the disclosure, and the drawings
that follow set forth various features, objectives, and advantages
of the invention and how they may be realized and obtained. These
features, objectives, and advantages will also become apparent by
practicing the invention.
[0024] As noted before, the interposer sandwich structure as shown
in FIG. 1 comprises two interposers enclosing a device requiring
shielding or protection. A solder or metal post bump size hierarchy
may be used with smaller solder bumps attaching the integrated
circuit device to the interposer on the bottom, and larger solder
or metal post bumps or other interconnection structure connecting
the top interposer with the bottom interposer or directly with the
chip carrier. The top interposer has a blanket metal coating on the
bottom or top surface, and the connections to the bottom interposer
or the chip carrier would be to electrical ground or bias,
depending on the function required. As shown in FIG. 2 one or more
devices connected to the bottom interposer may be shielded with a
top interposer selectively to provide the functional isolation for
shielding or protection desired for maximum miniaturization.
Thermal interface material can be dispensed on the back of the
integrated circuit device prior to joining the top interposer in
order to provide for rapid heat dissipation from the integrated
circuit device if required.
[0025] FIG. 1, illustrates a interposer sandwich structure for ESD,
EMI, and EMC shielding and protection having a top interposer 110,
and interconnectors 112 and 114 comprising joined solder bumps, as
described herein or metal posts capped with solder alloy. An
Application Specific Integrated Circuit (ASIC) 116 is position
under top interposer 110 that is operatively associated with chip
ground I/O interconnection 118.
[0026] A first metal layer 120 is positioned on BEOL dielectric
layer 132 and a second metal layer 122 on the bottom interposer
134. We also form a chip signal I/O interconnection 124 and a chip
signal I/O interconnection 126 (substantially the same as 124) both
positioned on the device as shown. A second metal layer 128
contacts the bottom interposer 134. A through-Si-Via
interconnection 130 forms an electrical connection to chip carrier
138 through connector 135. We position BEOL dielectric layer 132 on
bottom interposer 134 which is operatively associated with second
level ground I/O interconnection 136 and Chip carrier 138.
[0027] FIG. 2 illustrates top Interposer 210 with interconnectors
212 and 214 constructed of solder bumps or metal posts (Cu or Ni,
or the art-known equivalents thereof) positioned above chips 216
and 220. Chip 224 and chip 228 are positioned away from the
interposer to illustrate that the invention may be used in limited
areas on a device or devices mounted on a chip carrier such as chip
carrier 232. These chips 216, 220, 224, and 228 are operatively
associated with structure 230 that comprises capacitors and wiring
input/output (I/O) that is mounted on chip carrier 232.
[0028] Interconnectors 112, 114, 212, and 214 as noted comprise
solder (SnPb, SnAg, SnAgCu, or the art-known equivalents thereof)
bumps or metal (Cu or Ni or the art-known equivalents thereof.)
posts capped with solder alloy. In those instances we employ
shorter interconnectors between the chip and the lower interposer
before assembly of upper interposer to the lower interposer with
taller interconnectors. The shorter interconnectors are about
one-third the height of the taller interconnects between the upper
interposer and the lower interposer.
[0029] The interposers comprise a structure made of Si or other
materials such as ceramics used in microcircuit technology (e.g.,
SiC) and the art-know equivalents thereof, or polymers, such as
polyimides, phenolics or epoxies and the art-know equivalents
thereof.
[0030] Throughout this specification, and abstract of the
disclosure, the inventors have set out equivalents, of various
materials as well as combinations of elements, materials,
compounds, compositions, conditions, processes, structures and the
like, and even though set out individually, also include
combinations of these equivalents such as the two component, three
component, or four component combinations, or more as well as
combinations of such equivalent elements, materials, compositions
conditions, processes, structures and the like in any ratios or in
any manner.
[0031] Additionally, the various numerical ranges describing the
invention as set forth throughout the specification also includes
any combination of the lower ends of the ranges with the higher
ends of the ranges, and any single numerical value, or any single
numerical value that will reduce the scope of the lower limits of
the range or the scope of the higher limits of the range, and also
includes ranges falling within any of these ranges.
[0032] The terms "about," "substantial," or "substantially" as
applied to any claim or any parameters herein, such as a numerical
value, including values used to describe numerical ranges, means
slight variations in the parameter or the meaning ordinarily
ascribed to these terms by a person with ordinary skill in the art.
In another embodiment, the terms "about," "substantial," or
"substantially," when employed to define numerical parameter
include, e.g., a variation up to five per-cent, ten per-cent, or 15
per-cent, or somewhat higher.
[0033] The term "operatively associated" as used in this
specification means at least two structures and/or materials or
compounds or compositions connected to or aligned with one another
to perform a function, such as electrical conductance, electrical
shielding, electrical insulation, or heat shielding, or in some way
to enhance the performance of one or the other or both.
[0034] All scientific journal articles and other articles,
including Internet sites, as well as issued and pending patents
that this written description or applicants' Invention Disclosure
Statements mention, including the references cited in such
scientific journal articles and other articles, including internet
sites, and such patents, are incorporated herein by reference in
their entirety and for the purpose cited in this written
description and for all other disclosures contained in such
scientific journal articles and other articles, including Internet
sites as well as patents and the references cited therein, as all
or any one may bear on or apply in whole or in part, not only to
the foregoing written description, but also the following claims,
and abstract of the disclosure.
[0035] Although the inventors have described their invention by
reference to some embodiments, other embodiments defined by the
doctrine of equivalents are intended to be included as falling
within the broad scope and spirit of the foregoing written
description, and the following claims, and abstract of the
disclosure.
* * * * *