U.S. patent application number 12/763378 was filed with the patent office on 2012-08-23 for semiconductor device and method of protecting passivation layer in a solder bump process.
This patent application is currently assigned to STATS CHIPPAC, LTD.. Invention is credited to Haijing Cao, Yaojian Lin, Qing Zhang.
Application Number | 20120211881 12/763378 |
Document ID | / |
Family ID | 39541682 |
Filed Date | 2012-08-23 |
United States Patent
Application |
20120211881 |
Kind Code |
A9 |
Lin; Yaojian ; et
al. |
August 23, 2012 |
Semiconductor Device and Method of Protecting Passivation Layer in
a Solder Bump Process
Abstract
A flip chip semiconductor device has a substrate with a
plurality of active devices formed thereon. A contact pad is formed
on the substrate in electrical contact with the plurality of active
devices. A passivation layer is formed over the substrate and
intermediate conduction layer. An adhesive layer is formed over the
passivation layer. A barrier layer is formed over the adhesive
layer. A wetting layer is formed over the barrier layer. The
barrier layer and wetting layer in a first region are removed,
while the barrier layer, wetting layer, and adhesive layer in a
second region are maintained. The adhesive layer over the
passivation layer in the first region are maintained until the
solder bumps are formed. By keeping the adhesive layer over the
passivation layer until after formation of the solder bumps, less
cracking occurs in the passivation layer.
Inventors: |
Lin; Yaojian; (Singapore,
SG) ; Cao; Haijing; (Singapore, SG) ; Zhang;
Qing; (Singapore, SG) |
Assignee: |
STATS CHIPPAC, LTD.
Singapore
SG
|
Prior
Publication: |
|
Document Identifier |
Publication Date |
|
US 20100200985 A1 |
August 12, 2010 |
|
|
Family ID: |
39541682 |
Appl. No.: |
12/763378 |
Filed: |
April 20, 2010 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11934009 |
Nov 1, 2007 |
7727876 |
|
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12763378 |
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|
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60871410 |
Dec 21, 2006 |
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Current U.S.
Class: |
257/737 ;
257/E23.175 |
Current CPC
Class: |
H01L 2224/05155
20130101; H01L 2924/01013 20130101; H01L 2924/01074 20130101; H01L
2924/01079 20130101; H01L 2224/131 20130101; H01L 2224/05166
20130101; H01L 2224/05169 20130101; H01L 2924/14 20130101; H01L
2924/01029 20130101; H01L 2224/05027 20130101; H01L 24/03 20130101;
H01L 24/05 20130101; H01L 24/10 20130101; H01L 2224/05008 20130101;
H01L 2224/05024 20130101; H01L 24/13 20130101; H01L 2224/13099
20130101; H01L 2224/05572 20130101; H01L 2224/05647 20130101; H01L
2224/0401 20130101; H01L 2924/01024 20130101; H01L 2924/0002
20130101; H01L 2224/02377 20130101; H01L 2924/01022 20130101; H01L
2924/30105 20130101; H01L 2224/13024 20130101; H01L 2924/01082
20130101; H01L 2224/05624 20130101; H01L 24/02 20130101; H01L
2924/01047 20130101; H01L 2224/13 20130101; H01L 2224/05171
20130101; H01L 2924/01006 20130101; H01L 2924/01078 20130101; H01L
24/11 20130101; H01L 2924/01033 20130101; H01L 2924/01046 20130101;
H01L 2224/05147 20130101; H01L 2224/16 20130101; H01L 2924/0001
20130101; H01L 2224/05124 20130101; H01L 2224/05164 20130101; H01L
2924/014 20130101; H01L 2224/05644 20130101; H01L 2224/05572
20130101; H01L 2924/00014 20130101; H01L 2224/05027 20130101; H01L
2924/00014 20130101; H01L 2224/13 20130101; H01L 2924/00 20130101;
H01L 2924/0002 20130101; H01L 2224/05552 20130101; H01L 2224/05624
20130101; H01L 2924/00014 20130101; H01L 2224/05644 20130101; H01L
2924/00014 20130101; H01L 2224/05647 20130101; H01L 2924/00014
20130101; H01L 2224/05124 20130101; H01L 2924/00014 20130101; H01L
2224/05147 20130101; H01L 2924/00014 20130101; H01L 2224/05155
20130101; H01L 2924/00014 20130101; H01L 2224/05164 20130101; H01L
2924/00014 20130101; H01L 2224/05166 20130101; H01L 2924/00014
20130101; H01L 2224/05169 20130101; H01L 2924/00014 20130101; H01L
2224/05171 20130101; H01L 2924/00014 20130101; H01L 2224/05147
20130101; H01L 2924/013 20130101; H01L 2924/00014 20130101; H01L
2224/05124 20130101; H01L 2924/01029 20130101; H01L 2924/013
20130101; H01L 2224/05166 20130101; H01L 2924/01074 20130101; H01L
2924/013 20130101; H01L 2224/05171 20130101; H01L 2924/01029
20130101; H01L 2924/013 20130101; H01L 2224/05155 20130101; H01L
2924/013 20130101; H01L 2924/00014 20130101; H01L 2224/05147
20130101; H01L 2924/01013 20130101; H01L 2924/013 20130101; H01L
2924/0001 20130101; H01L 2224/02 20130101; H01L 2224/131 20130101;
H01L 2924/014 20130101 |
Class at
Publication: |
257/737 ;
257/E23.175 |
International
Class: |
H01L 23/538 20060101
H01L023/538 |
Claims
1. A semiconductor device, comprising: a substrate having a
plurality of semiconductor devices formed on a surface of the
substrate; a contact pad formed over the substrate in electrical
contact with the semiconductor devices; a redistribution layer
(RDL) formed over the substrate in electrical contact with the
contact pad; a passivation layer formed over the substrate and RDL,
wherein a portion of the passivation layer is removed to expose the
RDL; an adhesive layer formed over the passivation layer and the
exposed RDL; a barrier layer formed over a first portion of the
adhesive layer which is over the exposed RDL, the barrier layer not
being formed over a second portion of the adhesive layer; a wetting
layer formed over the barrier layer which is over the first portion
of the adhesive layer, the wetting layer not being formed over the
second portion of the adhesive layer; and a bump formed over the
wetting layer and barrier layer.
2. The semiconductor device of claim 1, wherein the first portion
of the adhesive layer is removed after the bump is formed.
3. The semiconductor device of claim 1, wherein the wetting layer,
barrier layer and adhesive layer constitute an under bump
metallization structure.
4. The semiconductor device of claim 1, wherein the adhesive layer
follows a contour of the passivation layer.
5. A semiconductor device, comprising: a substrate; a passivation
layer formed over the substrate; an adhesive layer formed over the
passivation layer; a barrier layer formed over a first portion of
the adhesive layer, the barrier layer not being formed over a
second portion of the adhesive layer; a wetting layer formed over
the barrier layer over the first portion of the adhesive layer, the
wetting layer not being formed over the second portion of the
adhesive layer; and an electrical interconnect formed over the
wetting layer and barrier layer.
6. The semiconductor device of claim 5, further including a
plurality of semiconductor devices formed on a surface of the
substrate.
7. The semiconductor device of claim 5, further including: a
contact pad formed over the substrate; and a redistribution layer
(RDL) formed over the substrate in electrical contact with the
contact pad.
8. The semiconductor device of claim 7, wherein the passivation
layer is formed over the RDL and a portion of the passivation layer
is removed to expose the RDL.
9. The semiconductor device of claim 8, wherein the barrier layer
is formed over the first portion of the adhesive layer which is
over the exposed RDL.
10. The semiconductor device of claim 5, wherein the first portion
of adhesive layer is removed after the bump is formed.
11. The semiconductor device of claim 5, wherein the wetting layer,
barrier layer and adhesive layer constitute an under bump
metallization structure.
12. The semiconductor device of claim 5, wherein the adhesive layer
follows a contour of the passivation layer.
13. The semiconductor device of claim 5, wherein the electrical
interconnect includes a bump.
14. A semiconductor device, comprising: a substrate; a passivation
layer formed over the substrate; an adhesive layer formed over the
passivation layer; a wetting layer formed over a first portion of
the adhesive layer, the wetting layer not being formed over a
second portion of the adhesive layer; and an electrical
interconnect formed over the wetting layer.
15. The semiconductor device of claim 14, further including a
barrier layer formed between the adhesive layer and the wetting
layer.
16. The semiconductor device of claim 15, wherein the wetting
layer, barrier layer and adhesive layer constitute an under bump
metallization structure.
17. The semiconductor device of claim 14, further including: a
contact pad formed over the substrate; and a redistribution layer
formed over the substrate in electrical contact with the contact
pad.
18. The semiconductor device of claim 14, wherein the first portion
of adhesive layer is removed after the bump is formed.
19. The semiconductor device of claim 14, wherein the electrical
interconnect includes a bump.
20. A semiconductor device, comprising: a substrate; a passivation
layer formed over the substrate; an adhesive layer formed over the
passivation layer; a barrier layer formed over a first portion of
the adhesive layer, the barrier layer not being formed over a
second portion of the adhesive layer; and an electrical
interconnect formed over the barrier layer.
21. The semiconductor device of claim 20, further including a
wetting layer formed over the barrier layer which is over the first
portion of the adhesive layer, the wetting layer not being formed
over the second portion of the adhesive layer.
22. The semiconductor device of claim 21, wherein the wetting
layer, barrier layer and adhesive layer constitute an under bump
metallization structure.
23. The semiconductor device of claim 20, further including: a
contact pad formed over the substrate; and a redistribution layer
formed over the substrate in electrical contact with the contact
pad.
24. The semiconductor device of claim 20, wherein the first portion
of adhesive layer is removed after the bump is formed.
25. The semiconductor device of claim 20, wherein the electrical
interconnect includes a bump.
Description
CLAIM TO DOMESTIC PRIORITY
[0001] The present application is a division of U.S. patent
application Ser. No. 11/934,009, filed Nov. 1, 2007, and claims
priority to the foregoing parent application pursuant to 35 U.S.C.
.sctn.120.
FIELD OF THE INVENTION
[0002] The present invention relates in general to semiconductor
devices and, more particularly, to formation of solder bump
structures on semiconductor devices.
BACKGROUND OF THE INVENTION
[0003] Semiconductor devices are found in many products used in
modern society. Semiconductors find applications in consumer items
such as entertainment, communications, networks, computers, and
household items markets. In the industrial or commercial market,
semiconductors are found in military, aviation, automotive,
industrial controllers, and office equipment.
[0004] The manufacture of semiconductor devices involves formation
of a wafer having a plurality of die. Each die contains hundreds or
thousands of transistors and other active and passive devices
performing a variety of electrical functions. For a given wafer,
each die from the wafer typically performs the same electrical
function. Front-end manufacturing generally refers to formation of
the semiconductor devices on the wafer. The finished wafer has an
active side containing the transistors and other active and passive
components. Back-end manufacturing refers to cutting or singulating
the finished wafer into the individual die and then packaging the
die for structural support and/or environmental isolation.
[0005] One goal of semiconductor manufacturing is to produce a
package suitable for faster, reliable, smaller, and higher-density
integrated circuits (IC) at lower cost. Flip chip packages or wafer
level packages (WLP) are ideally suited for ICs demanding high
speed, high density, and greater pin count. Flip chip style
packaging involves mounting the active side of the die facedown
toward a chip carrier substrate or printed circuit board (PCB). The
electrical and mechanical interconnect between the active devices
on the die and conduction tracks on the carrier substrate is
achieved through a solder bump structure comprising a large number
of conductive solder bumps or balls. The solder bumps are formed by
a reflow process applied to solder material deposited on contact
pads, which are disposed on the semiconductor substrate. The solder
bumps are then soldered to the carrier substrate. The flip chip
semiconductor package provides a short electrical conduction path
from the active devices on the die to the carrier substrate in
order to reduce signal propagation, lower capacitance, and achieve
overall better circuit performance.
[0006] The reliability and integrity of the interconnect structure
is important to testing, manufacturing yield, and longevity of the
product while in service. In some devices, a problem of cracking
has been detected in the passivation layer surrounding the solder
bump after solder reflow. The cracking has been attributed to
degradation of the passivation layer caused by the chemical
processes used during formation of the solder bumps. The cracking
problem is especially noted during formation and removal of dry
film used to create the solder bumps.
[0007] A need exists for a solder bump structure with enhanced
strength and reliability.
SUMMARY OF THE INVENTION
[0008] In one embodiment, the present invention is a semiconductor
device comprising a substrate having a plurality of semiconductor
devices formed on a surface of the substrate. A contact pad is
formed over the substrate in electrical contact with the
semiconductor devices. An RDL is formed over the substrate in
electrical contact with the contact pad. A passivation layer is
formed over the substrate and RDL. A portion of the passivation
layer is removed to expose the RDL. An adhesive layer is formed
over the passivation layer and the exposed RDL. A barrier layer is
formed over a first portion of the adhesive layer which is over the
exposed RDL. The barrier layer is not formed over a second portion
of the adhesive layer. A wetting layer is formed over the barrier
layer which is over the first portion of the adhesive layer. The
wetting layer is not formed over the second portion of the adhesive
layer. A bump is formed over the wetting layer and barrier
layer.
[0009] In another embodiment, the present invention is a
semiconductor device comprising a substrate and passivation layer
formed over the substrate. An adhesive layer is formed over the
passivation layer. A barrier layer is formed over a first portion
of the adhesive layer. The barrier layer not being formed over a
second portion of the adhesive layer. A wetting layer is formed
over the barrier layer over the first portion of the adhesive
layer. The wetting layer not being formed over the second portion
of the adhesive layer. An electrical interconnect is formed over
the wetting layer and barrier layer.
[0010] In another embodiment, the present invention is a
semiconductor device comprising substrate and passivation layer
formed over the substrate. An adhesive layer is formed over the
passivation layer. A wetting layer is formed over a first portion
of the adhesive layer. The wetting layer not being formed over a
second portion of the adhesive layer. An electrical interconnect is
formed over the wetting layer.
[0011] In another embodiment, the present invention is a
semiconductor device comprising a substrate and passivation layer
formed over the substrate. An adhesive layer is formed over the
passivation layer. A barrier layer is formed over a first portion
of the adhesive layer. The barrier layer not being formed over a
second portion of the adhesive layer. An electrical interconnect is
formed over the barrier layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a flip chip semiconductor device with solder bumps
providing electrical interconnect between an active area of the die
and a chip carrier substrate;
[0013] FIG. 2 illustrates formation of an adhesive layer over the
second passivation layer;
[0014] FIG. 3 illustrates formation of a barrier layer and wetting
layer over the adhesive layer;
[0015] FIG. 4 illustrates patterning the UBM structure prior to
etching portions of the barrier layer and wetting layer;
[0016] FIG. 5 illustrates removing portions of the barrier layer
and wetting layer in a region outside the UBM structure while
leaving the adhesive layer intact over the passivation layer;
[0017] FIG. 6 illustrates formation of dry film layer over the
adhesive layer, which protects the passivation layer and the
deposition of solder material;
[0018] FIG. 7 illustrates reflow of the solder material to form
solder bumps and removal of dry film layer; and
[0019] FIG. 8 illustrates removal of the adhesive layer from the
region outside the UBM structure.
DETAILED DESCRIPTION OF THE DRAWINGS
[0020] The present invention is described in one or more
embodiments in the following description with reference to the
Figures, in which like numerals represent the same or similar
elements. While the invention is described in terms of the best
mode for achieving the invention's objectives, it will be
appreciated by those skilled in the art that it is intended to
cover alternatives, modifications, and equivalents as may be
included within the spirit and scope of the invention as defined by
the appended claims and their equivalents as supported by the
following disclosure and drawings.
[0021] The manufacture of semiconductor devices involves formation
of a wafer having a plurality of die. Each die contains hundreds or
thousands of transistors and other active and passive devices
performing one or more electrical functions. For a given wafer,
each die from the wafer typically performs the same electrical
function. Front-end manufacturing generally refers to formation of
the semiconductor devices on the wafer. The finished wafer has an
active side containing the transistors and other active and passive
components. Back-end manufacturing refers to cutting or singulating
the finished wafer into the individual die and then packaging the
die for structural support and/or environmental isolation.
[0022] A semiconductor wafer generally includes an active front
side surface having semiconductor devices disposed thereon, and a
backside surface formed with bulk semiconductor material, e.g.,
silicon. The active front side surface contains a plurality of
semiconductor die. The active surface is formed by a variety of
semiconductor processes, including layering, patterning, doping,
and heat treatment. In the layering process, semiconductor
materials are grown or deposited on the substrate by techniques
involving thermal oxidation, nitridation, chemical vapor
deposition, evaporation, and sputtering. Patterning involves use of
photolithography to mask areas of the surface and etch away
undesired material to form specific structures. The doping process
injects concentrations of dopant material by thermal diffusion or
ion implantation. The active surface is substantially planar and
uniform with electrical interconnects, such as bond pads.
[0023] Flip chip semiconductor packages and wafer level packages
(WLP) are commonly used with integrated circuits (ICs) demanding
high speed, high density, and greater pin count. Flip chip style
semiconductor device 10 involves mounting an active area 12 of die
14 facedown toward a chip carrier substrate or printed circuit
board (PCB) 16, as shown in FIG. 1. Active area 12 contains active
and passive devices, conductive layers, and dielectric layers
according to the electrical design of the die. The electrical and
mechanical interconnect is achieved through a solder bump structure
20 comprising a large number of individual conductive solder bumps
or balls 22. The solder bumps are formed on bump pads 24, which are
disposed on active area 12. The bump pads 24 connect to the active
circuits by conduction tracks in active area 12. The solder bumps
22 are electrically and mechanically connected to contact pads 26
on carrier substrate 16 by a solder reflow process. The flip chip
semiconductor device provides a short electrical conduction path
from the active devices on die 14 to conduction tracks on carrier
substrate 16 in order to reduce signal propagation, lower
capacitance, and achieve overall better circuit performance.
[0024] FIG. 2 illustrates a cross-sectional view of the formation
of a support structure for a solder bump. Note that for FIGS. 2-8
the semiconductor device is oriented with its active surface facing
up. In FIG. 2, metal contact pad 32 is formed on silicon substrate
34. Contact pad 32 is made of aluminum (Al), copper (Cu), or
aluminum/copper alloys. Contact pad 32 is electrically connected to
active and passive devices through conduction tracks or layers
formed on substrate 34. A solder bump will later be formed to
connect through an RDL to the metal contact pad. A first
passivation layer 36 is formed over substrate 34 with an opening to
expose metal contact pad 32. The opening is realized by removing a
portion of passivation layer 36 through a photoresist mask defined
etching process. The first passivation layer 36 can be made with
silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride
(SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole
(PBO), or other insulating material.
[0025] A first redistribution layer (RDL) 40 is formed over first
passivation layer 36, as shown in FIG. 2. RDL 40 provides
electrical contact between pad 32 and solder bump area 48 which is
provided for the first solder bump. A second RDL 42 is also is
formed over first passivation layer 36. RDL 42 provides electrical
contact between other conduction tracks on substrate 34 and solder
bump area 50 which is provided for the second solder bump. The
first and second RDLs can be made with Aluminum (Al), Aluminum
Copper alloy (AlCu), Cu, or Cu alloy. RDLs 40 and 42 operate as an
intermediate conduction layer to route electrical signals to
various areas of the die, including active and passive circuits,
and provides various electrical interconnect options during package
integration.
[0026] A second passivation layer 44 is formed over first
passivation layer 36 and RDLs 40 and 42. The second passivation
layer is thicker than RDLs 40 and 42. In one embodiment,
passivation layer 44 is about 5-15 .mu.m in thickness and RDL 40 is
about 1-3 .mu.m in thickness. Passivation layer 44 can be made
using similar material as described for passivation layer 36. In
another embodiment, passivation layers 36 and 44 are formed by
repassivation. A portion of second passivation layer 44 is removed
by a photoresist mask defined etching process for the first and
second solder bumps in areas 48 and 50 or the second passivation
layer is photosensitive and can be patterned directly.
[0027] An adhesive layer 46 is formed on passivation layer 44 and
RDLs 40 and 42. In one embodiment, adhesive layer 46 is about
200-2000 angstroms in thickness. Adhesive layer 46 can be titanium
(Ti), Al, titanium tungsten (TiW), and chromium (Cr). Adhesive
layer 46 is patterned to follow the contour of passivation layer 44
and RDLs 40 and 42. Accordingly, the formation of adhesive layer 46
is depressed in solder bump areas 48 and 50 and covers
substantially the entire surface of passivation layer 44,
particularly in and around areas 48 and 50, as seen in FIG. 2.
[0028] FIG. 3 illustrates a barrier layer 52 formed over adhesive
layer 46, and wetting layer 54 formed over barrier layer 52.
Barrier layer 52 and wetting layer 54, in combination with adhesive
layer 46, forms an under bump metallization (UBM) in areas 48 and
50 for the first and second solder bumps. The adhesion layer 46
bonds to barrier layer 52. Barrier layer 42 inhibits the diffusion
of materials destructive to silicon such as Cu into the active area
of the die. Barrier layer 52 is optional depending on the materials
used and the application. Wetting layer 52 electrically connects to
contact pad 32 via RDL 40. In one embodiment, barrier layer 52 is
about 3000-4000 angstroms in thickness, and wetting layer 54 is
about 5000-10000 angstroms in thickness. Barrier layer 52 can be
made of nickel (Ni), Ni-alloy, platinum (Pt), palladium (Pd), TiW,
and chromium copper (CrCu). Wetting layer 54 can be made with Cu,
gold (Au), or Al. Barrier layer 52 is patterned to follow the
contour of adhesive layer 46. Likewise, wetting layer 54 is
patterned to follow the contour of barrier layer 52 and acts as an
intermediate conduction layer formed between the first solder bump
and RDL 40. The patterning barrier layer 52 and wetting layer 54
and adhesive layer 46, as described above, define the solder bump
areas 48 and 50 for forming solder bumps. The barrier layer 52 and
wetting layer 54 and adhesive layer 46 enhance reliability of the
bump support structure.
[0029] In FIG. 4, a photoresist layer is deposited over wetting
layer 54. The photoresist layer is patterned to provide photoresist
layers 56 and 58 over solder bump areas 48 and 50, respectively. In
FIG. 5, the portions of barrier layer 52 and wetting layer 54,
which are not protected by photoresist layers 56 and 58, are
removed using a wet etch process. That is, only the portions of
wetting layer 54 and barrier layer 52 in the region outside the UBM
structure are etched away. The adhesive layer 46 in the region
outside the UMB structure remains in place at this stage of the
process. As will be shown, the portion of adhesive layer 46 in the
region outside solder bump areas 48 and 50 protects passivation
layer 44 from chemical degradation during formation of the solder
bumps in later stages of the process. Photoresist layers 56 and 58
are then removed, leaving the UBM structure comprising adhesive
layer 46, barrier layer 52, and wetting layer 54 only in solder
bump areas 48 and 50.
[0030] In FIG. 6, a dry film layer 60 is deposited over adhesive
layer 46 and the UBM structure comprising adhesive layer 46,
barrier layer 52, and wetting layer 54. The dry film layer is
patterned, and the portion of the dry film over the UBM structure
is removed. Solder material 62 is deposited over the UBM structure
between the patterned dry film layer through a screen printing, or
electrolytic plating or electroless plating process. The solder
material can be any metal or electrically conductive material,
e.g., tin (Sn), lead (Pb), Ni, Au, silver (Ag), Cu, bismuthinite
(Bi) and alloys thereof, or mixtures of other electrically
conductive material. In one embodiment, the solder material is 63
percent weight of Sn and 37 percent weight of Pb.
[0031] In FIG. 7, the solder material is reflowed by heating the
conductive material above its melting point to form spherical balls
or bumps 64 and 66 over semiconductor substrate 34. In one
embodiment, solder bumps 64 and 66 are about 70.about.180 .mu.m in
height. In some applications, solder bumps 64 and 66 are reflowed a
second time to improve electrical contact to the UBM structure.
[0032] It is important to note that during the solder bump
formation process, the adhesive layer 46 in the region outside the
UBM structure remains in place. The previous step of removing the
portion of wetting layer 54 and barrier layer 52 in the region
outside the UBM structure did not involve adhesive layer 46. The
adhesive layer 46 in the region outside the UBM structure remains
in place and protects passivation layer 44 against chemical
degradation during the formation of the solder bumps, in particular
during deposition and remove of dry film layer 60. The adhesive
layer over the passivation layer reduces cracking of the
passivation layer 44 without incurring additional manufacturing
costs.
[0033] In FIG. 8, a wet etching process applied to remove any
portion of adhesion layer 46 in the region outside the region of
the solder bump structure using solder bumps as the etching mask.
Solder bump 64 electrically contacts metal contact pad 32 by way of
RDL 40. Likewise, solder bump 66 electrically contacts RDL 42.
[0034] In another embodiment, semiconductor device 10 can be made
with a direct contact between the solder bump and the contact pad,
i.e., without RDLs or other conductive routing structure. In this
case, contact pad 32 is formed directly under the UBM structure. A
similar process, as described in FIGS. 2-8, would be used for the
direct solder bump to contact pad embodiment. The adhesive layer in
the region outside the UBM structure protects the passivation layer
against chemical degradation during formation of the solder bumps,
particularly during deposition and removal of dry film layer.
Again, the adhesive layer over the passivation layer reduces
cracking of the passivation layer without incurring additional
manufacturing costs.
[0035] While one or more embodiments of the present invention have
been illustrated in detail, the skilled artisan will appreciate
that modifications and adaptations to those embodiments may be made
without departing from the scope of the present invention as set
forth in the following claims.
* * * * *