U.S. patent application number 12/654372 was filed with the patent office on 2011-03-17 for interposer and method for manufacturing the same.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO. LTD.. Invention is credited to Hyung Jin Jeon, Young Do Kweon, Seon Hee Moon, Seung Wook Park, Jong In Ryu, Seung Wan Shin.
Application Number | 20110061911 12/654372 |
Document ID | / |
Family ID | 43729371 |
Filed Date | 2011-03-17 |
United States Patent
Application |
20110061911 |
Kind Code |
A1 |
Jeon; Hyung Jin ; et
al. |
March 17, 2011 |
Interposer and method for manufacturing the same
Abstract
An interposer includes: an insulation plate where a via is
formed, the insulation plate including a resin or a ceramic; a
first upper redistribution layer electrically connected to the via
along a circuit pattern designed on the top surface of the
insulation plate; a first upper protection layer laminated to
expose a portion of the first upper redistribution layer and
protecting the first upper redistribution layer; a second upper
redistribution layer electrically connected to the first upper
redistribution layer and laminated along a designed circuit pattern
designed; a second upper protection layer laminated to expose a
portion of the second upper redistribution layer and protecting the
second upper redistribution layer; and an under bump metallization
(UBM) formed at the exposed portion of the second upper
redistribution layer.
Inventors: |
Jeon; Hyung Jin; (Gunpo,
KR) ; Ryu; Jong In; (Suwon, KR) ; Shin; Seung
Wan; (Hwaseong, KR) ; Moon; Seon Hee; (Seoul,
KR) ; Kweon; Young Do; (Seoul, KR) ; Park;
Seung Wook; (Suwon, KR) |
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.
LTD.
Suwon
KR
|
Family ID: |
43729371 |
Appl. No.: |
12/654372 |
Filed: |
December 17, 2009 |
Current U.S.
Class: |
174/258 ;
427/96.2 |
Current CPC
Class: |
H01L 23/49827 20130101;
H05K 3/4605 20130101; H01L 21/486 20130101; H05K 3/4644 20130101;
H05K 2201/0979 20130101; H01L 2225/06572 20130101; H05K 3/4602
20130101; H05K 2201/10378 20130101; H01L 23/49822 20130101; H01L
21/4857 20130101; H01L 2924/0002 20130101; H01L 2924/0002 20130101;
H01L 2924/00 20130101; H05K 3/244 20130101; H05K 3/427
20130101 |
Class at
Publication: |
174/258 ;
427/96.2 |
International
Class: |
H05K 1/03 20060101
H05K001/03; B05D 5/12 20060101 B05D005/12 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 14, 2009 |
KR |
10-2009-0086614 |
Claims
1. An interposer comprising: an insulation plate where a via is
formed, the insulation plate including a resin or a ceramic; a
first upper redistribution layer formed on the top surface of the
insulation plate to be electrically connected to the via along a
designed circuit pattern; a first upper protection layer laminated
to expose a portion of the first upper redistribution layer and
protecting the first upper redistribution layer; a second upper
redistribution layer electrically connected to the first upper
redistribution layer and laminated along a designed circuit
pattern; a second upper protection layer laminated to expose a
portion of the second upper redistribution layer and protecting the
second upper redistribution layer; and an under bump metallization
(UBM) formed at the exposed portion of the second upper
redistribution layer.
2. The interposer of claim 1, further comprising: a lower
redistribution layer formed on the bottom surface of the insulation
plate to be electrically connected to the via along a designed
circuit pattern; a lower protection layer laminated to expose a
portion of the lower redistribution layer and protecting the lower
redistribution layer; and an under bump metallization (UBM) formed
at the exposed portion of the lower redistribution layer.
3. A method for manufacturing an interposer, the method comprising:
forming a via hole in an insulation plate including a resin or a
ceramic; simultaneously forming resists for a first upper
redistribution layer on the top surface of the insulation plate,
and a resistor for a lower redistribution layer on the bottom
surface of the insulation plate; plating copper to fill the via
hole and simultaneously forming the first upper redistribution
layer and the lower redistribution layer along a designed circuit
pattern; and forming a first upper protection layer and a lower
protection layer to expose a portion of the first upper
redistribution layer and a portion of the lower redistribution
layer.
4. The method of claim 3, further comprising forming an under bump
metallization (UBM) on the first upper redistribution layer and the
lower redistribution layer exposed after the formation of the first
upper protection layer and the lower protection layer.
5. The method of claim 3, further comprising: forming a second
upper redistribution layer on the top surface of the insulation
plate along a designed circuit pattern; and forming a second upper
protection layer to expose a portion of the second upper
redistribution layer.
6. The method of claim 5, further comprising forming an under bump
metallization (UBM) on the second upper redistribution layer
exposed after the formation of the second upper protection
layer.
7. The method of claim 5, wherein the second upper redistribution
layer and the second upper protection layer are formed using a
semiconductor manufacturing process in order for implementation of
fine pitches.
8. The method of claim 3, wherein the forming of the via hole on
the insulation plate comprises forming a seed layer in a region
where the resin or ceramic inside the insulation plate is
exposed.
9. The method of claim 3, wherein the plating of the copper and the
forming of the first upper redistribution layer and the lower
redistribution layer comprise plating the copper on both sides of
the insulation plate and the via hole, and removing the
resists.
10. The method of claim 3, wherein the insulation plate is a copper
clad laminate (CCL).
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the priority of Korean Patent
Application No. 10-2009-0086614 filed on Sep. 14, 2009, in the
Korean Intellectual Property Office, the disclosure of which is
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to an interposer, and more
particularly, to an interposer which can be manufactured at low
costs by reducing material costs and manufacturing costs.
[0004] 2. Description of the Related Art
[0005] The trend within the electronics industry is to manufacture
lighter, smaller, faster, multi-functional, high-performance and
high-reliability products at low cost. One of most important
technologies within the industry is a package technology. In order
to implement smaller and slimmer packages, interposer technology
for realizing 3D structures and ensuring reliability is
required.
[0006] A typical interposer is manufactured using silicon through a
semiconductor manufacturing process. However, when the interposer
is manufactured using silicon, material costs and manufacturing
costs increase.
SUMMARY OF THE INVENTION
[0007] An aspect of the present invention provides an interposer
which can be manufactured at low costs by reducing material costs
and manufacturing cost.
[0008] According to an aspect of the present invention, there is
provided an interposer including: an insulation plate where a via
is formed, the insulation plate including a resin or a ceramic; a
first upper redistribution layer formed on the top surface of the
insulation plate to be electrically connected to the via along a
designed circuit pattern; a first upper protection layer laminated
to expose a portion of the first upper redistribution layer and
protecting the first upper redistribution layer; a second upper
redistribution layer electrically connected to the first upper
redistribution layer and laminated along a designed circuit
pattern; a second upper protection layer laminated to expose a
portion of the second upper redistribution layer and protecting the
second upper redistribution layer; and an under bump metallization
(UBM) formed at the exposed portion of the second upper
redistribution layer.
[0009] The interposer may further include: a lower redistribution
layer formed on the bottom surface of the insulation plate to be
electrically connected to the via along a designed circuit pattern;
a lower protection layer laminated to expose a portion of the lower
redistribution layer and protecting the lower redistribution layer;
and an under bump metallization (UBM) formed at the exposed portion
of the lower redistribution layer.
[0010] According to another aspect of the present invention, there
is provided a method for manufacturing an interposer, the method
including: forming a via hole in an insulation plate including a
resin or a ceramic; simultaneously forming a resists for a first
upper redistribution layer on the top surface of the insulation
plate, and a resistor for a lower redistribution layer on the
bottom surface of the insulation plate; plating copper to fill the
via hole and simultaneously forming the first upper redistribution
layer and the lower redistribution layer along a designed circuit
pattern; and forming a first upper protection layer and a lower
protection layer to expose a portion of the first upper
redistribution layer and a portion of the lower redistribution
layer.
[0011] The method may further include forming an under bump
metallization (UBM) on the first upper redistribution layer and the
lower redistribution layer exposed after the formation of the first
upper protection layer and the lower protection layer.
[0012] The method may further include: forming a second upper
redistribution layer on the top surface of the insulation plate
along a designed circuit pattern; and forming a second upper
protection layer to expose a portion of the second upper
redistribution layer.
[0013] The method may further include forming an under bump
metallization (UBM) on the second upper redistribution layer
exposed after the formation of the second upper protection
layer.
[0014] The second upper redistribution layer and the second upper
protection layer may be formed using a semiconductor manufacturing
process in order for implementation of fine pitches.
[0015] The forming of the via hole on the insulation plate may
include forming a seed layer in a region where the resin or ceramic
inside the insulation plate is exposed.
[0016] The plating of the copper and the forming of the first upper
redistribution layer and the lower redistribution layer may include
plating the copper on both sides of the insulation plate and the
via hole, and removing the resists.
[0017] The insulation plate may be a copper clad laminate
(CCL).
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The above and other aspects, features and other advantages
of the present invention will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0019] FIG. 1 is a cross-sectional view of an interposer according
to an embodiment of the present invention; and
[0020] FIGS. 2A to 2L illustrate a method for manufacturing an
interposer according to another embodiment of the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0021] Exemplary embodiments of the present invention will now be
described in detail with reference to the accompanying drawings.
The invention may, however, be embodied in many different forms and
should not be construed as being limited to the embodiments set
forth herein. Rather, these embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the
scope of the invention to those skilled in the art. In the
drawings, the thicknesses of layers and regions are exaggerated for
clarity. Like reference numerals in the drawings denote like
elements, and thus their description will be omitted.
[0022] Further, when a part (or element, device, etc.) is referred
to as being "connected" to another part (or element, device, etc.),
it should be understood that the former can be "directly connected"
to the latter, or "indirectly connected" to the latter via an
intervening part (or element, device, etc.). Furthermore, when it
is described that one comprises (or includes or has) certain
elements, it should be understood that it may comprise (or include
or has) only those elements, or it may comprise (or include or
have) other elements as well as those elements if there is no
specific limitation.
[0023] FIG. 1 is a cross-sectional view of an interposer according
to an embodiment of the present invention.
[0024] Referring to FIG. 1, the interposer according to the
embodiment of the present invention may include an insulation plate
10 and a via 12. The insulation plate 10 may include a resin or a
ceramic, and the via 12 passes through the insulation plate 10 in a
thickness direction. The insulation plate 10 may be a copper clad
laminate (CCL) in which copper layers are laminated on the top and
bottom surfaces thereof. The via 20 may be formed of a conductive
material, e.g., copper.
[0025] A first upper redistribution layer (RDL) 31 may be formed on
the top surface of the insulation plate 10 along a designed circuit
pattern, and a first upper protection layer 41 protecting the first
upper redistribution layer 31 may be formed on the top surface of
the first upper redistribution layer 31 to expose a portion of the
first upper redistribution layer 31. The first upper redistribution
layer 31 may be formed of a conductive material.
[0026] In addition, a second upper redistribution layer 32 may be
formed along a circuit pattern designed to expose a portion of the
first upper protection layer 41, and a second upper protection
layer 42 may be formed on the top surface of the second upper
redistribution layer 32 to expose a portion of the second upper
redistribution layer 32. The second upper redistribution layer 32
may be formed of a conductive material.
[0027] If necessary, an under bump metallization (UMB) for the
formation of bumps may be formed at the exposed portion of the
second upper redistribution layer 32.
[0028] A lower redistribution layer 33 may be formed on the bottom
surface of the insulation plate 10 along a designed circuit
pattern, and a lower protection layer 43 protecting the lower
redistribution layer 33 may be formed on the bottom surface of the
lower redistribution layer 33 to expose a portion of the lower
redistribution layer 33. The lower redistribution layer 33 may be
formed of a conductive material.
[0029] An under bump metallization for the formation of bumps may
be formed at the exposed portion of the lower redistribution layer
33.
[0030] FIGS. 2A to 2L illustrate a method for manufacturing an
interposer according to another embodiment of the present
invention.
[0031] FIG. 2A is a schematic cross-sectional view of a copper clad
laminate 11 where copper foil layers 11 are formed on both surfaces
of an insulation plate 10 including a resin or a ceramic.
[0032] In the case of using a silicon wafer, much expense may be
incurred in making the silicon wafer having a desired thickness.
However, in the case of using a copper clad laminate, the cost
reduction effect is achieved. In addition, since a large-sized
copper clad laminate, e.g., 405.times.510, may be used,
productivity is also improved.
[0033] Referring to FIG. 2B, a via hole 12 may be formed in the
insulation plate 10 in a thickness direction. The via hole 12 may
be formed through a mechanical method, such as laser cutting or
drilling.
[0034] In the case of using the silicon wafer, much expense may be
incurred because a via hole is formed by an etching process.
However, in the case of using the insulation plate 10, the cost
reduction effect is achieved because the via hole 12 may be formed
through a mechanical method.
[0035] Referring to FIG. 2C, seed layers for the formation of a via
may be formed on both sides of the via holes 12. The seed layer may
be formed of copper.
[0036] Referring to FIG. 2D, resists 14 for the formation of
redistribution layers may be formed on both surfaces of the
insulation plate 10 where the via hole 12 is formed.
[0037] Referring to FIGS. 2E and 2F, a conductive metal is plated
on the insulation plate 10 where the resists 14 are formed on both
surfaces thereof, and the resists 14 are removed to form a first
upper redistribution layer 31, a lower redistribution layer 33, and
a via 20 at the same time. The conductive metal used in the plating
may be copper.
[0038] In the case of using the silicon wafer, the via and the
redistribution layers cannot be formed at the same time, and
individual processes must be performed. Hence, much time and
expense are incurred. In the case of using the copper clad
laminate, the via 20, the first upper redistribution layer 31, and
the lower redistribution layer 33 can be formed at the same time,
but it is difficult to implement fine pitches. However, there is no
great problem because the first upper redistribution layer 31 and
the lower redistribution layer 33 are generally used as the ground
interconnection.
[0039] When the process of removing the resists illustrated in FIG.
2F is completed, the large-sized insulation plate 10 is processed
in a wafer form. Therefore, since a semiconductor manufacturing
process can be applied, fine pitches for subsequent redistribution
layers may be implemented.
[0040] Referring to FIG. 2G, a lower protection layer 43 protecting
the lower redistribution layer 33 may be formed on the bottom
surface of the insulation plate 10. As illustrated in FIG. 2G, the
lower protection layer 43 may be formed to expose a portion of the
lower redistribution layer 33. Furthermore, the lower protection
layer 43 may be formed of an insulating material.
[0041] Referring to FIG. 2H, an under bump metallization 52 for the
formation of bumps may be formed on the exposed lower
redistribution layer 33. Furthermore, although not illustrated,
necessary bumps may be formed on the under bump metallization
52.
[0042] Referring to FIG. 2I, a first upper protection layer 41
protecting the first upper redistribution layer 31 may be formed on
the top of the insulation plate 10. As illustrated in FIG. 2I, the
first upper protection layer 41 may also be formed to expose a
portion of the first upper redistribution layer 31. Furthermore,
the first upper protection layer 41 may be formed of an insulating
material.
[0043] Referring to FIG. 2J, a second upper redistribution layer 32
may be on the top surface of the first upper protection layer 41
along a designed circuit pattern. The second upper redistribution
layer 32 may be formed of a conductive material. As illustrated in
FIG. 2J, the second upper redistribution layer 32 may be formed to
expose a portion of the first upper protection layer 41.
[0044] Referring to FIG. 2K, a second upper protection layer 42
protecting the second upper redistribution layer 32 may be formed
on the top surface of the second upper redistribution layer 32. As
illustrated in FIG. 2K, the second upper protection layer 42 may be
formed to expose a portion of the second upper redistribution layer
32. Furthermore, the second upper protection layer 42 may be formed
of an insulating material.
[0045] Referring to FIG. 2L, an under bump metallization 51 for
formation of bumps may be formed at the exposed portion of the
second upper redistribution layer 32. Although not illustrated in
FIG. 2L, necessary bumps may be formed on the under bump
metallization 51.
[0046] Moreover, although a two-layered redistribution layer and a
protection layer are formed on the top surface of the insulation
plate 10 and a single-layered redistribution layer and a protection
layer are formed on the bottom surface of the insulation plate 10,
a plurality of redistribution layers and a plurality of protection
layers may be further laminated onto the top and bottom surfaces of
the insulation plate 10.
[0047] As set forth above, according to exemplary embodiments of
the invention, the interposer may be provided at low cost by
reducing material costs and manufacturing costs because the
interposer is manufactured using an insulation plate including a
resin or a ceramic, instead of a silicon wafer.
[0048] Moreover, since the large-sized insulation plate may be
used, a large quantity of interposers can be produced in a single
process, thereby improving the productivity of the interposers.
[0049] While the present invention has been shown and described in
connection with the exemplary embodiments, it will be apparent to
those skilled in the art that modifications and variations can be
made without departing from the spirit and scope of the invention
as defined by the appended claims.
* * * * *