U.S. patent application number 12/565171 was filed with the patent office on 2010-12-23 for method for fabricating semiconductor package and semiconductor package using the same.
This patent application is currently assigned to ELECTRONICS AND TELECOMMUNICATION RESEARCH INSTITUTE. Invention is credited to Hyun-Cheol Bae, Kwang-Seong Choi, Yong Sung Eom, Jong-Hyun Lee, Jong Tae Moon.
Application Number | 20100320596 12/565171 |
Document ID | / |
Family ID | 43353548 |
Filed Date | 2010-12-23 |
United States Patent
Application |
20100320596 |
Kind Code |
A1 |
Eom; Yong Sung ; et
al. |
December 23, 2010 |
METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR
PACKAGE USING THE SAME
Abstract
Provided is a method for fabricating semiconductor package and a
semiconductor package fabricated using the same. The method for
fabricating semiconductor package dopes a mixture including the
polymer material and the solder particle on the substrate in which
the terminal is formed and applies heat, and thus the solder
particle flows (or diffuses) toward the terminal in the heated
polymer resin to adhere to the exposed surface of the terminal,
i.e., the side surface and upper surface of the terminal, thereby
forming the solder layer. The solder layer improves the adhesive
strength between the terminal of the semiconductor chip and the
terminal of the substrate in the subsequent flip chip bonding
process.
Inventors: |
Eom; Yong Sung; (Daejeon,
KR) ; Choi; Kwang-Seong; (Daejeon, KR) ; Bae;
Hyun-Cheol; (Daejeon, KR) ; Lee; Jong-Hyun;
(Gyeonggi-do, KR) ; Moon; Jong Tae; (Daejeon,
KR) |
Correspondence
Address: |
RABIN & Berdo, PC
1101 14TH STREET, NW, SUITE 500
WASHINGTON
DC
20005
US
|
Assignee: |
ELECTRONICS AND TELECOMMUNICATION
RESEARCH INSTITUTE
Daejeon
KR
|
Family ID: |
43353548 |
Appl. No.: |
12/565171 |
Filed: |
September 23, 2009 |
Current U.S.
Class: |
257/737 ;
257/E21.508; 257/E23.023; 438/107; 438/612 |
Current CPC
Class: |
H01L 2224/83194
20130101; H01L 2924/01079 20130101; H01L 2924/014 20130101; H01L
24/81 20130101; H01L 2924/15787 20130101; H01L 2224/05669 20130101;
H01L 2924/01049 20130101; H01L 2224/1134 20130101; H01L 2924/00014
20130101; H01L 2924/01022 20130101; H01L 2224/818 20130101; H01L
2224/05669 20130101; H01L 2924/01082 20130101; H01L 2224/05568
20130101; H01L 2224/05644 20130101; H01L 2924/00013 20130101; H01L
24/29 20130101; H01L 2224/05655 20130101; H01L 2224/05666 20130101;
H01L 2224/73203 20130101; H01L 2924/0105 20130101; H01L 21/563
20130101; H01L 23/49816 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2924/15787 20130101; H01L 23/49827
20130101; H01L 24/16 20130101; H01L 2224/05655 20130101; H01L
2224/73104 20130101; H01L 2224/1152 20130101; H01L 2224/81192
20130101; H01L 2924/01033 20130101; H01L 21/486 20130101; H01L
2224/81801 20130101; H01L 2924/00013 20130101; H01L 2224/0556
20130101; H01L 2924/00014 20130101; H01L 2224/13099 20130101; H01L
2924/01047 20130101; H01L 2924/00 20130101; H01L 2224/0555
20130101; H01L 2224/05599 20130101; H01L 2924/00014 20130101; H01L
2924/00012 20130101; H01L 2924/00014 20130101; H01L 23/29 20130101;
H01L 24/32 20130101; H01L 2224/05644 20130101; H01L 2224/05666
20130101; H01L 2924/01005 20130101; H01L 2224/0554 20130101; H01L
2924/01078 20130101; H01L 2924/14 20130101; H01L 2924/01029
20130101; H01L 2924/01051 20130101; H01L 23/293 20130101; H01L
2224/818 20130101; H01L 2924/01006 20130101; H01L 2224/05573
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
257/737 ;
438/107; 438/612; 257/E21.508; 257/E23.023 |
International
Class: |
H01L 23/488 20060101
H01L023/488; H01L 21/60 20060101 H01L021/60 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 22, 2009 |
KR |
10-2009-0055478 |
Claims
1. A method for fabricating a semiconductor package, the method
comprising: forming a first terminal at a first substrate;
providing a mixture comprising a polymer resin and a solder
particle to cover at least one upper surface and side surface of
the first terminal; and heating the first substrate at a
temperature higher than a melting point of the solder particle to
form a solder layer covering the upper surface and side surface of
the first terminal.
2. The method of claim 1, wherein the first terminal protrudes
upward from an upper surface of the first substrate and comprises a
metal pad and a metal bump which is disposed on the metal pad.
3. The method of claim 2, wherein the metal bump has a pillar type
or a stud type.
4. The method of claim 1, further comprising forming a hole in the
first substrate, before forming the first terminal, wherein the
first terminal is formed to cover an inner side wall and bottom of
the hole, and the solder layer fills the hole.
5. The method of claim 4, further comprising planarizing a front
surface and rear surface of the first substrate.
6. The method of claim 1, wherein the mixture is extended to cover
a space between the first terminal and another first terminal
adjacent to the first terminal.
7. The method of claim 1, further comprising removing the polymer
resin to expose the solder layer, after forming the solder
layer.
8. The method of claim 7, further comprising: providing a flowable
hardening resin covering a side surface of the exposed solder
layer; disposing a second substrate, in which a second terminal is
formed, on the first substrate to come in contact with the second
terminal and the solder layer; and heating the first substrate at a
temperature higher than a melting point of the solder layer to
couple the first and second terminals through the solder layer, and
hardening the flowable hardening resin.
9. The method of claim 1, further comprising disposing a second
substrate, in which a second terminal is formed, on the first
substrate before heating the first substrate to bring the second
terminal to be adjacent to the first terminal.
10. The method of claim 9, wherein: the mixture further comprises a
hardening agent, and the polymer resin is hardened with the
hardening agent by heating the first substrate.
11. The method of claim 8, wherein the second substrate comprises a
semiconductor chip.
12. The method of claim 1, wherein the solder particle has a
diameter of about 0.1 to 70 .mu.m.
13. The method of claim 1, wherein the mixture comprises the solder
particle and the polymer resin which are mixed at a volume rate of
1:9 to 5:5.
14. A semiconductor package, comprising: a first substrate; a first
terminal on the first substrate; and a solder layer covering a
whole surface of the first terminal which is exposed, without
contacting the first substrate.
15. The semiconductor package of claim 14, further comprising: a
second substrate disposed on the first substrate; and a second
terminal formed at a lower surface of the second substrate to be
adjacent to the first terminal, wherein the solder layer is
extended to cover a side surface of the second terminal.
16. The semiconductor package of claim 15, further comprising: a
dielectric layer filling a space between the first and second
substrates; and a solder particle disposed in the dielectric layer
and apart from the solder layer.
17. The semiconductor package of claim 15, wherein the second
substrate comprises a semiconductor chip.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This U.S. non-provisional patent application claims priority
under 35 U.S.C. .sctn.119 of Korean Patent Application No.
10-2009-0055478, filed on Jun. 22, 2009, the entire contents of
which are hereby incorporated by reference.
BACKGROUND OF THE INVENTIVE CONCEPT
[0002] The present invention disclosed herein relates to a method
for fabricating semiconductor package and a semiconductor package
fabricated using the same.
[0003] As semiconductor integrated circuit applied to electronic
devices is highly densified and integrated, the multiplying of pin
and the narrowing of pitch progress rapidly in the electrode
terminal of semiconductor chip. In mounting on the interconnection
substrate of the semiconductor chip, moreover, a flip chip bonding
is widely used for decreasing interconnection delay. This flip chip
bonding brings the external electrode pad of the semiconductor chip
in contact with the pad of a mounting substrate, and by applying
heat, allows the two pads to be bonded in a reflow process. In such
a flip chip bonding process, since heat is applied and compression
is performed simply, the bonding strength between the electrode pad
of the semiconductor chip and the pad of the mounting substrate is
very low. Accordingly, the electrode pad of the semiconductor chip
and the pad of the mounting substrate are easily disconnected by a
physical impact.
SUMMARY OF THE INVENTIVE CONCEPT
[0004] The present invention provides a method for fabricating
semiconductor package, which is suitable for the multiplying of pin
and the narrowing of pitch, and can increase bonding strength.
[0005] The present invention also provides a semiconductor package,
which is suitable for the multiplying of pin and the narrowing of
pitch, and has bonding strength that has been increased.
[0006] Embodiments of the present invention provide a method for
fabricating semiconductor package including: forming a first
terminal in a first substrate; providing a mixture including a
polymer resin and a solder particle to cover at least one upper
surface and side surface of the first terminal; and heating the
first substrate at a temperature higher than a melting point of the
solder particle to form a solder layer covering the upper surface
and side surface of the first terminal.
[0007] In some embodiments, the first terminal may protrude upward
from an upper surface of the first substrate, and may include a
metal pad and a metal bump which is disposed on the metal pad. At
this point, the metal bump may have a pillar type or a stud
type.
[0008] In other embodiments, the method may further include forming
a hole in the first substrate, before forming the first terminal,
wherein the first terminal may cover a side wall and bottom of the
hole, and the solder layer may fill the hole. The method may
further include planarizing a front surface and rear surface of the
first substrate.
[0009] In still other embodiments, the mixture may be extended to
cover the first terminal and another first terminal adjacent to the
first terminal.
[0010] In even other embodiments, the method may further include
removing the polymer resin to expose the solder layer, after
forming the solder layer. The method may further include: providing
a flowable hardening resin covering a side surface of the exposed
solder layer; disposing a second substrate, in which a second
terminal is formed, on the first substrate to come in contact with
the second terminal and the solder layer; and heating the first
substrate at a temperature higher than a melting point of the
solder layer to couple the first and second terminals through the
solder layer, and hardening the flowable hardening resin.
[0011] In yet other embodiments, the method may further include
disposing a second substrate, in which a second terminal is formed,
on the first substrate before heating the first substrate to bring
the second terminal in contact with the first terminal. In this
case, the mixture may further include a hardening agent, and the
polymer resin may be hardened with the hardening agent by heating
the first substrate.
[0012] In further embodiments, the second substrate may include a
semiconductor chip.
[0013] In other embodiments of the present invention, a
semiconductor package includes: a first substrate; a first terminal
on the first substrate; and a solder layer covering a surface of
the first terminal which is exposed, without contacting the first
substrate.
[0014] In some embodiments, the semiconductor package may further
include: a second substrate disposed on the first substrate; and a
second terminal, adjacent to the first terminal, formed in a lower
surface of the second substrate, wherein the solder layer may be
extended to cover a side surface of the second terminal.
[0015] In other embodiments, the semiconductor package may further
include: a dielectric layer filling a space between the first and
second substrates; and a solder particle disposed in the dielectric
layer, and separated from the solder layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The accompanying figures are included to provide a further
understanding of the present invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
exemplary embodiments of the present invention and, together with
the description, serve to explain principles of the present
invention. In the figures:
[0017] FIGS. 1A through 1F are cross-sectional views illustrating a
process of fabricating a semiconductor package according to an
embodiment of the inventive concept;
[0018] FIGS. 2A through 2F are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept;
[0019] FIGS. 3A through 3F are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept;
[0020] FIGS. 4A through 4E are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept;
[0021] FIGS. 5A and 5B are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept;
[0022] FIGS. 6A and 6B are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept;
[0023] FIGS. 7A and 7B are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept;
[0024] FIGS. 8A and 8B are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept;
[0025] FIGS. 9A through 9D are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept; and
[0026] FIGS. 10A through 10D are cross-sectional views illustrating
a process of fabricating a semiconductor package according to
another embodiment of the inventive concept.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0027] Preferred embodiments of the present invention will be
described below in more detail with reference to the accompanying
drawings. The present invention may, however, be embodied in
different forms and should not be construed as limited to the
embodiments set forth herein. Rather, these embodiments are
provided so that this disclosure will be thorough and complete, and
will fully convey the scope of the present invention to those
skilled in the art. In the figures, the dimensions of layers and
regions are exaggerated for clarity of illustration. It will also
be understood that when a layer (or film) is referred to as being
`on` another layer or substrate, it can be directly on the other
layer or substrate, or intervening layers may also be present.
Further, it will be understood that when a layer is referred to as
being `under` another layer, it can be directly under, and one or
more intervening layers may also be present. In addition, it will
also be understood that when a layer is referred to as being
`between` two layers, it can be the only layer between the two
layers, or one or more intervening layers may also be present. Like
reference numerals refer to like elements throughout.
Embodiment 1
[0028] FIGS. 1A through 1F are across-sectional views illustrating
a process of fabricating a semiconductor package according to an
embodiment of the inventive concept.
[0029] Referring to FIG. 1A, a first substrate 1 in which a first
pad 2 is formed is prepared. The first substrate 1, for example,
may be a mounting substrate on which a semiconductor chip is
mounted. Alternatively, the first substrate 1 may be a silicon
substrate, a printed circuit board or a ceramic substrate. The
first pad 2 may be formed of titanium, nickel, platinum or metal
such as aurum, and may be formed in a process such as electric
plating. A pillar type bump 3 is formed on the first pad 2. The
pillar type bump 3, for example, may be formed of copper, and may
be formed in a process such as electric plating. The first pad 2
and the bump 3 may configure a first terminal 50.
[0030] Referring to FIG. 1B, a mixture 7 including a solder
particle 5 and a polymer resin 6 is doped on the first substrate 1
in which the pillar type bump 3 is formed. The mixture 7 covers the
both side surfaces and upper surface of the first terminal 50 and
fills a space between the first terminal 50 and another first
terminal 50 adjacent to it. In the mixture 7, the solder particle 5
and the polymer resin 6 may be mixed at a volume rate of 1:9 to
5:5. The solder particle 5, for example, may have a diameter of
about 0.1 to 100 .mu.m. The solder particle 5 may be plumbum,
stannum, indium, bismuth, antimony, argentum or metal particle such
as alloy of these. The polymer resin 6 may flow. The polymer resin
6 may remove an oxide layer from the surface of the solder particle
5 when being heated. The polymer resin 6, for example, may be an
epoxy-based resin, and may include bisphenol A and epichlorohydrin.
The mixture 7 may further include a reductant. The mixture 7 may
further include a deforming agent.
[0031] Referring to FIG. 1C, the mixture 7 is doped, and the first
substrate 1 is heated. At this point, the first substrate 1 may be
heated at a temperature higher than the melting point of the solder
particle 5. Therefore, the heated polymer resin 6 removes an oxide
layer from the surface of the solder particle 5, and the solder
particle 5 flows inside the polymer resin 6 to move to the surface
of the first pad 2 and the bump 3, thereby being adhered to the
surface. Consequently, a solder layer 10 covering the surface of
the first terminal 50 including the bump 3 and the first pad 2.
That is, the solder layer 10 is formed to cover the upper surface
and both side surfaces of the pillar type bump 3 and the both side
surfaces of the first pad 2. When the mixture 7 further includes a
deforming agent, the deforming agent suppresses the production of a
gas in the mixture 7, and thus the solder particle 5 allows wet
characteristic to be better expressed in the surface of the bump 3
and the surface of the first pad 2. The polymer resin 6 may be
changed into a state before gelation, for example, a resin layer 8
of an almost liquid state by the heating process. The solder
particle 5, which is far away from the bump 3 and the first pad 2,
cannot reach the surface of the bump 3 and the surface of the first
pad 2, and is left inside the resin layer 8.
[0032] Referring to FIG. 1D, the solder layer 10 is formed, and the
resin layer 8 is removed with a solvent agent. For example, the
solvent agent may be acetone, benzene, toluene or water. When
removing the resin layer 8, the solder particle 5 existing inside
the resin layer 8 may be removed together. Accordingly, the solder
layer 10 and the upper surface of the first substrate 1 peripheral
to it are exposed.
[0033] A semiconductor chip or another substrate may be mounted on
the first substrate 1 in FIG. 1D. This case will be described below
with reference to FIGS. 1E and 1F.
[0034] Referring to FIG. 1E, a flowable hardening resin 16 is doped
to cover the surface of the exposed solder layer 10 and the upper
surface of the first substrate 1. The flowable hardening resin 16
may fill a space between solder layers 10 covering the surfaces of
the adjacent first terminals 50. The flowable hardening resin 16
may be a material similar to the polymer resin 6, and may further
include a hardening agent. The flowable hardening resin 16 may also
have a function of removing an oxide layer. The solder particle 5
does not exit inside flowable hardening resin 16. The flowable
hardening resin is doped, and a second substrate 14 in which a
second pad 15 is formed is disposed on the first substrate 1. The
second substrate 14 may be another mounting substrate, or may be a
semiconductor chip. The second pad 15 may be called a second
terminal.
[0035] Referring to FIG. 1F, the second substrate 14 is disposed to
come in contact with the second pad 15 and the upper surface of the
solder layer 10, and the first substrate 1 is heated at a
temperature higher than the melting point of the solder layer 10.
Thus, the flowable hardening resin 16 removes an oxide layer that
may be formed in the surface of the solder layer 10, and the solder
layer 10 flows (or diffuses) to the both side surfaces of the
second pad 15, thereby being adhered. The solder layer 10,
therefore, may cover the first pad 2, the pillar type bump 3 and
the both side surfaces of the second pad 15. Moreover, the solder
layer 10 may be interposed between the pillar type bump 3 and the
second pad 15. The solder layer 10, accordingly, bonds the pillar
type bump 3 and the second pad 15, increasing the bonding strength
between the two substrates 1 and 14. Moreover, the flowable
hardening resin 16 reacts with a hardening agent included in it to
be hardened through a heating process, being changed into a
hardened underfill resin 17. Accordingly, as illustrated in FIGS.
1E and 1F, a flip chip bonding process and an underfill process for
the semiconductor chip may be performed at the same time.
[0036] Referring to a semiconductor package in FIG. 1F, the
electrical connection and physical coupling between the first
substrate 1 and the second substrate 14 are achieved by the first
pad 2, the pillar type bump 3, the second pad 15 and the solder
layer 10 covering their surfaces. The pillar type bump 3 maintains
and supports the pitch between the first substrate 1 and the second
substrate 14. Moreover, the underfill resin 17 fills a space
between the first substrate 1 and the second substrate 14,
protecting the semiconductor package against various external
environment factors such as moisture and physical impacts.
[0037] The first substrate 1 in FIG. 1D may be mounted on a mother
board such as a printed circuit board in an overturned state. At
this point, the first pad 2, the pillar type bump 3 and the solder
layer 10 covering their surfaces configure an external terminal
such as a solder bump, and may electrically connect with the mother
board. In this case, in the first substrate 1, the semiconductor
chip may be mounted in the surface opposite to a surface in which
the solder layer 10 is disposed.
Embodiment 2
[0038] FIGS. 2A through 2F are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept.
[0039] Referring to FIGS. 2A through 2F, in another embodiment of
the inventive concept, the pitch between first terminals 50 is
broader than the case of embodiment 1. In this way, when the pitch
between the first terminals 50 is broad, a mixture 7 including a
solder particle 5 and a polymer resin 6 may be selectively doped on
a desired position in a screen printer process, as illustrated in
FIG. 2B. Subsequently, when a heating process is performed, the
oxide layer of the solder particle 5 in the mixture 7 is removed,
and the solder particle 5 diffuses to the surface of the first
terminal 50 to reveal wet characteristic, thereby forming a solder
layer 10 covering the upper surface and both side surfaces of the
first terminal 50. As shown in FIG. 2C, since distance from the
edge of a region (on which the mixture 7 is doped) to the surface
of the first terminal 50 is shorter than the case of embodiment 1,
the solder particle 5 may not almost be left inside a resin layer
8. In FIG. 2E, the providing of a flowable hardening resin 16 may
be performed in a screen printer process. In addition, detailed
processes and process conditions may be the same as those of
embodiment 1.
Embodiment 3
[0040] FIGS. 3A through 3F are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept.
[0041] Referring to FIG. 3A, a first substrate 1 in which a first
pad 2 is formed is prepared. A stud type bump 4 is formed on the
first pad 2. The stud type bump 4 may be separately fabricated in a
stud type and be raised on the first pad 2. By performing a thermal
reflow process, the stud type bump 4 may be bonded on the first pad
2. For example, the stud type bump 4 may be formed of aurum, copper
or an alloy of these. The first pad 2 and the stud type bump 4 may
configure a first terminal 51.
[0042] Referring to FIG. 3B, a mixture 7 including a solder
particle 5 and a polymer resin 6 is doped on the first substrate 1
in which the stud type bump 4 is formed. The mixture 7 covers all
the exposed surfaces of the first terminal 50 and fills a space
between the first terminal 50 and another first terminal 50
adjacent to it. In the mixture 7, the solder particle 5 and the
polymer resin 6 may be mixed at a volume rate of 1:9 to 5:5. The
solder particle 5, for example, may have a diameter of about 0.1 to
100 .mu.m. The solder particle 5 may be plumbum, stannum, indium,
bismuth, antimony, argentum or metal particle such as alloy of
these. The polymer resin 6 may flow. The polymer resin 6 may remove
an oxide layer from the surface of the solder particle 5 when being
heated. The polymer resin 6, for example, may be an epoxy-based
resin, and may include bisphenol A and epichlorohydrin. The mixture
7 may further include a reductant. The mixture 7 may further
include a deforming agent.
[0043] Referring to FIG. 3C, the mixture 7 is doped, and the first
substrate 1 is heated. At this point, the first substrate 1 may be
heated at a temperature higher than the melting point of the solder
particle 5. Therefore, the heated polymer resin 6 removes an oxide
layer from the surface of the solder particle 5, and the solder
particle 5 flows inside the polymer resin 6 to move to the surface
of the first terminal 51, thereby being adhered to the surface.
Consequently, a solder layer 10 covering the surface of the first
terminal 50 including the bump 4 and the first pad 2. That is, the
solder layer 10 is formed to cover the bent surface of the stud
type bump 4 and the both side surfaces of the first pad 2. When the
mixture 7 further includes a deforming agent, the deforming agent
suppresses the production of a gas in the mixture 7, and thus the
solder particle 5 allows wet characteristic to be better expressed
in the surface of the bump 4 and the surface of the first pad 2.
The polymer resin 6 may be changed into a state before gelation,
for example, a resin layer 8 of an almost liquid state by the
heating process. The solder particle 5, which is far away from the
bump 4 and the first pad 2, cannot reach the surface of the bump 3
and the surface of the first pad 2, and is left inside the resin
layer 8.
[0044] Referring to FIG. 3D, the solder layer 10 is formed, and the
resin layer 8 is removed with a solvent agent. For example, the
solvent agent may be acetone, benzene, toluene or water. When
removing the resin layer 8, the solder particle 5 existing inside
the resin layer 8 may be removed together. Accordingly, the solder
layer 10 and the upper surface of the first substrate 1 peripheral
to it are exposed.
[0045] Referring to FIG. 3E, a flowable hardening resin 16 is doped
to cover the surface of the exposed solder layer 10 and the upper
surface of the first substrate 1. The flowable hardening resin 16
may fill a space between solder layers 10 covering the surfaces of
the adjacent first terminals 50. The flowable hardening resin 16
may be a material similar to the polymer resin 6, and may further
include a hardening agent. The flowable hardening resin 16 may also
have a function of removing an oxide layer. The solder particle 5
does not exit inside flowable hardening resin 16. The flowable
hardening resin is doped, and a second substrate 14 in which a
second pad 15 is formed is disposed on the first substrate 1. The
second substrate 14 may be another mounting substrate, or may be a
semiconductor chip. The second pad 15 may be called a second
terminal.
[0046] Referring to FIG. 3F, the second substrate 14 is disposed to
come in contact with the second pad 15 and the upper surface of the
solder layer 10, and the first substrate 1 is heated at a
temperature higher than the melting point of the solder layer 10.
Thus, the flowable hardening resin 16 removes an oxide layer that
may be formed in the surface of the solder layer 10, and the solder
layer 10 flows (or diffuses) to the both side surfaces of the
second pad 15, thereby being adhered. The solder layer 10,
therefore, may cover the first pad 2, the stud type bump 4 and the
both side surfaces of the second pad 15. The solder layer 10,
accordingly, bonds the stud type bump 4 and the second pad 15,
increasing the bonding strength between the two substrates 1 and
14. Moreover, the flowable hardening resin 16 reacts with a
hardening agent included in it to be hardened through a heating
process, being changed into a hardened underfill resin 17.
Accordingly, as illustrated in FIGS. 3E and 3F, a flip chip bonding
process and an underfill process for the semiconductor chip may be
performed at the same time.
[0047] Referring to a semiconductor package in FIG. 3F, the
electrical connection and physical coupling between the first
substrate 1 and the second substrate 14 are achieved by the first
pad 2, the stud type bump 4, the second pad 15 and the solder layer
10 covering their surfaces. The stud type bump 4 maintains and
supports the pitch between the first substrate 1 and the second
substrate 14. Moreover, the underfill resin 17 fills a space
between the first substrate 1 and the second substrate 14,
protecting the semiconductor package against various external
environment factors such as moisture and physical impacts.
[0048] The first substrate 1 in FIG. 3D may be mounted on a mother
board such as a printed circuit board in an overturned state. At
this point, the first pad 2, the stud type bump 4 and the solder
layer 10 covering their surfaces configure an external terminal
such as a solder bump, and may electrically connect with the mother
board. In this case, in the first substrate 1, the semiconductor
chip may be mounted in the surface opposite to a surface in which
the solder layer 10 is disposed.
Embodiment 4
[0049] FIGS. 4A through 4E are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept.
[0050] Referring to FIGS. 4A through 4E, in another embodiment of
the inventive concept, the pitch between first terminals 51 is
broader than the case of embodiment 1. In this way, when the pitch
between the first terminals 51 is broad, a mixture 7 including a
solder particle 5 and a polymer resin 6 may be selectively doped on
a desired position in a screen printer process, as illustrated in
FIG. 4B. Subsequently, when a heating process is performed, the
oxide layer of the solder particle 5 in the mixture 7 is removed,
and the solder particle 5 diffuses to the surface of the first
terminal 51 to reveal wet characteristic, thereby forming a solder
layer 10 covering the bent surface of the first terminal 51. As
shown in FIG. 4C, since distance from the edge of a region (on
which the mixture 7 is doped) to the surface of the first terminal
51 is shorter than the case of embodiment 3, the solder particle 5
may not almost be left inside a resin layer 8. In FIG. 4E, the
providing of a flowable hardening resin 16 may be performed in a
screen printer process. In addition, detailed processes and process
conditions may be the same as those of embodiment 3.
Embodiment 5
[0051] FIGS. 5A and 5B are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept.
[0052] Referring to FIG. 5A, a first substrate 1 in which a first
pad 2 is formed is prepared. A pillar type bump 3 is formed on the
first pad 2. The first pad 2 and the pillar type bump 3 may
configure a first terminal 50. A mixture 26 including a solder
particle 5 and a flowable hardening resin 24 is doped on the first
substrate 1 in which the pillar type bump 3 is formed. The mixture
26 covers all the both side surfaces and upper surface of the first
terminal 50 and fills a space between the first terminal 50 and
another first terminal 50 adjacent to it. In the mixture 26, the
solder particle 5 and the flowable hardening resin 24 may be mixed
at a volume rate of 1:9 to 5:5. The solder particle 5, for example,
may have a diameter of about 0.1 to 100 .mu.m. The solder particle
5 may be plumbum, stannum, indium, bismuth, antimony, argentum or
metal particle such as alloy of these. The flowable hardening resin
24 may flow and remove an oxide layer. Moreover, the flowable
hardening resin 24 may include a hardening agent. The flowable
hardening resin 24 may further include at least one of a reductant,
a catalyst and a deforming agent. A second substrate 14 in which a
second pad 15 is formed is disposed on the first substrate 1 on
which the mixture 26 is doped.
[0053] Referring to FIG. 5B, the second substrate 14 is disposed to
come in contact with the first terminal 50 and the upper surface of
the pillar type bump 3, and the first substrate 1 is heated at a
temperature higher than the melting point of the solder particle 5.
Thus, the flowable hardening resin 24 removes an oxide layer that
may be formed in the surface of the solder particle 5, and the
solder particle 5 flows (or diffuses) to the both side surfaces of
the first terminal 50 and the both side surfaces of the second pad
15 to be adhered, thereby forming a solder layer 10. The solder
layer 10, therefore, may cover the first pad 2, the pillar type
bump 3 and the both side surfaces of the second pad 15. The solder
layer 10, accordingly, bonds the first terminal 50 and the second
pad 15, increasing the bonding strength between the two substrates
1 and 14. The flowable hardening resin 24 reacts with a hardening
agent included in it to be hardened through a heating process,
being changed into a hardened underfill resin 25. A solder particle
5 that cannot form the solder layer 10 may be left inside the
hardened underfill resin 25. However, since the left solder
particle 5 is disposed inside the hardened underfill resin 25
having dielectric properties, limitations such as electrical short
between the two substrates 1 and 14 are prevented.
[0054] According to another embodiment of the inventive concept, a
flip chip bonding process and an underfill process are performed at
the same time, and the bonding strength between the two substrates
1 and 14 is increased by the solder layer 10. The hardened
underfill resin 25 further increases the bonding strength between
the two substrates 1 and 14 and simultaneously protects a
semiconductor package against an external environment. Although a
process of fabricating the semiconductor package according to
another embodiment of the inventive concept is similar to the
process of embodiment 1, it does not all perform the processes of
FIGS. 1A through 1F, thereby being simplified. Accordingly, the
cost is saved and the process time is shortened.
Embodiment 6
[0055] FIGS. 6A and 6B are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept.
[0056] Referring to FIGS. 6A and 6B, in another embodiment of the
inventive concept, the pitch between first terminals 50 is broader
than the case of embodiment 5. In this way, when the pitch between
the first terminals 50 is broad, a mixture 7 including a solder
particle 5 and a flowable hardening resin 24 may be selectively
doped on a desired position in a screen printer process, as
illustrated in FIG. 6A. A second substrate 14 in which a second pad
15 is formed is disposed on the first substrate 1, and by applying
heat and compression, a solder layer 10 covering the first terminal
50 and the both side walls of the second pad 15 is formed. As shown
in FIG. 6B, since distance from the edge of a region (on which the
mixture 26 is doped) to the surface of the first terminal 50 is
shorter than the case of embodiment 5, the solder particle 5 may
not almost be left inside the hardened underfill resin 25. In
addition, detailed processes and process conditions may be the same
as those of embodiment 5.
Embodiment 7
[0057] FIGS. 7A and 7B are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept.
[0058] Referring to FIG. 7A, a first substrate 1 in which a first
pad 2 is formed is prepared. A stud type bump 4 is formed on the
first pad 2. For example, the stud type bump 4 may be formed of
aurum, copper or an alloy of these. The first pad 2 and the stud
type bump 4 may configure a first terminal 51. A mixture 26
including a solder particle 5 and a flowable hardening resin 24 is
doped on the first substrate 1 in which the stud type bump 4 is
formed. The mixture 26 covers the bent surface of the first
terminal 51 and fills a space between the first terminal 51 and
another first terminal 51 adjacent to it. In the mixture 26, the
solder particle 5 and the flowable hardening resin 24 may be mixed
at a volume rate of 1:9 to 5:5. The solder particle 5, for example,
may have a diameter of about 0.1 to 100 .mu.m. The solder particle
5 may be plumbum, stannum, indium, bismuth, antimony, argentum or
metal particle such as alloy of these. The flowable hardening resin
24 may flow and remove an oxide layer. Moreover, the flowable
hardening resin 24 may include a hardening agent. The flowable
hardening resin 24 may further include at least one of a reductant,
a catalyst and a deforming agent. A second substrate 14 in which a
second pad 15 is formed is disposed on the first substrate 1 on
which the mixture 26 is doped.
[0059] Referring to FIG. 7B, the second substrate 14 is disposed to
come in contact with the first terminal 51 and the upper surface of
the stud type bump 4, and the first substrate 1 is heated at a
temperature higher than the melting point of the solder particle 5.
Thus, the flowable hardening resin 24 removes an oxide layer that
may be formed in the surface of the solder particle 5, and the
solder particle 5 flows (or diffuses) to the bent surface of the
first terminal 51 and the both side surfaces of the second pad 15
to be adhered, thereby forming a solder layer 10. The solder layer
10, therefore, may cover the first pad 2, the stud type bump 4 and
the both side surfaces of the second pad 15. The solder layer 10,
accordingly, bonds the first terminal 51 and the second pad 15,
increasing the bonding strength between the two substrates 1 and
14. The flowable hardening resin 24 reacts with a hardening agent
included in it to be hardened through a heating process, being
changed into a hardened underfill resin 25. A solder particle 5
that cannot form the solder layer 10 may be left inside the
hardened underfill resin 25. However, since the left solder
particle 5 is disposed inside the hardened underfill resin 25
having dielectric properties, limitations such as electrical short
between the two substrates 1 and 14 are prevented.
[0060] According to another embodiment of the inventive concept, a
flip chip bonding process and an underfill process are performed at
the same time, and the bonding strength between the two substrates
1 and 14 is increased by the solder layer 10. The hardened
underfill resin 25 further increases the bonding strength between
the two substrates 1 and 14 and simultaneously protects a
semiconductor package against an external environment. Although a
process of fabricating the semiconductor package according to
another embodiment of the inventive concept is similar to the
process of embodiment 3, it does not all perform the processes of
FIGS. 3A through 3F, thereby being simplified. Accordingly, the
cost is saved and the process time is shortened.
Embodiment 8
[0061] FIGS. 8A and 8B are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept.
[0062] Referring to FIGS. 8A and 8B, in another embodiment of the
inventive concept, the pitch between first terminals 51 is broader
than the case of embodiment 7. In this way, when the pitch between
the first terminals 51 is broad, a mixture 7 including a solder
particle 5 and a flowable hardening resin 24 may be selectively
doped on a desired position in a screen printer process, as
illustrated in FIG. 8A. A second substrate 14 in which a second pad
15 is formed is disposed on the first substrate 1, and by applying
heat and compression, a solder layer 10 covering the first terminal
51 and the both side walls of the second pad 15 is formed. As shown
in FIG. 8B, since distance from the edge of a region (on which the
mixture 26 is doped) to the surface of the first terminal 51 is
shorter than the case of embodiment 7, the solder particle 5 may
not almost be left inside the hardened underfill resin 25. In
addition, detailed processes and process conditions may be the same
as those of embodiment 7.
Embodiment 9
[0063] FIGS. 9A through 9D are cross-sectional views illustrating a
process of fabricating a semiconductor package according to another
embodiment of the inventive concept.
[0064] Referring to FIG. 9A, a via hole 31 is formed in a first
substrate 30. Furthermore, a seed layer covering the side wall and
bottom of the via hole 31 is formed. The seed layer 27 may be
formed of titanium, nickel, platinum, aurum, copper or an alloy of
these. The seed layer 27 may be formed in a Chemical Vapor
Deposition (CVD) process or an Atomic Layer Deposition (ALD)
process. Additionally, a planarization etching process may be
further performed for forming the seed layer 27 covering the side
wall and bottom of the via hole 31. The seed layer 27 may
correspond to the first terminal of embodiment 1.
[0065] Referring to FIG. 9B, a mixture 7 including a solder
particle 5 and a polymer resin 6 is doped on the first substrate 30
in which the seed layer 27 is formed. The mixture 7 is doped to
fill the inside of the via hole 31. For this, vacuum may be given
to the first substrate 30. The physical properties of the polymer
resin 6 and the solder particle 5 may be the same as those of
embodiment 1.
[0066] Referring to FIG. 9C, by heating the first substrate 30 at a
temperature higher than the melting point of the solder particle 5,
a solder via 11 covering the exposed surface of the seed layer 27
and filling the inside of the via hole 31 is formed. The solder via
11 is not formed inside a resin layer 8, and a left solder particle
5 may be included in the resin layer 8.
[0067] Referring to FIG. 9D, the resin layer is removed with a
solvent agent. At this point, a solder particle 5 that is left
inside the resin layer 8 may also be removed together. Furthermore,
by performing a planarization removal process on the front surface
and rear surface of the first substrate 30, a terminalion of the
upper portion and lower portion of the first substrate 30 is
removed, and a seed pattern 27a covering the inner side wall of the
via hole 31 and a solder via plug 11a filling the via hole 31 are
formed.
[0068] Subsequently, a rewiring electrically connected to the
solder via plug 11a may be formed in the front surface and rear
surface of the first substrate 30 including the solder via plug
11a. The first substrate 30 may be used as a mounting substrate
such as a printed circuit board or a ceramic substrate on which a
semiconductor chip is mounted. Alternatively, the first substrate
30 may be a semiconductor chip including a through via such as a
through silicon via.
Embodiment 10
[0069] FIGS. 10A through 10D are cross-sectional views illustrating
a process of fabricating a semiconductor package according to
another embodiment of the inventive concept.
[0070] Referring to FIGS. 10A through 10D, in another embodiment of
the inventive concept, the pitch between via holes 31 formed on a
first substrate 30 is broader than the case of embodiment 9. In
this case, a mixture 7 including a solder particle 5 and a polymer
resin 6 may be doped in a screen printer process. At this point,
like embodiment 9, vacuum may be given to the first substrate 30 in
order for the mixture 7 to fill the via hole 31. In addition, the
order and condition of a process may be the same as those of
embodiment 9.
[0071] The method for fabricating semiconductor package according
to an embodiment of the inventive concept dopes a mixture including
the polymer material and the solder particle on the substrate in
which the terminal is formed and applies heat, and thus the solder
particle flows (or diffuses) toward the terminal in the heated
polymer resin to adhere to the exposed surface of the terminal,
i.e., the side surface and upper surface of the terminal, thereby
forming the solder layer. The solder layer improves the adhesive
strength between the terminal of the semiconductor chip and the
terminal of the substrate in the subsequent flip chip bonding
process.
[0072] In the method for fabricating semiconductor package
according to an embodiment of the inventive concept, moreover, the
pad of the substrate may protrude from the substrate, and may be
configured with the pad and the bump disposed on it. The pitch
between the semiconductor chip and the substrate can be constantly
maintained by the terminal that is configured with the pad and the
bump. Compared with a case in which the terminal includes only the
pad without including the bump and there is the solder layer
covering the surface of the terminal, in an embodiment of the
inventive concept where the terminal includes both the pad and the
bump, the risk of electrical short (which is caused by the contact
of two adjacent solder layers) is removed because the bump serves
as the support bar between the semiconductor chip and the
substrate. Accordingly, the method for fabricating semiconductor
package can be easily applied to the multiplying of pin and the
narrowing of pitch.
[0073] In the semiconductor package according to another embodiment
of the inventive concept, bonding strength can increase by the
solder layer covering the surfaces of the pads that are disposed
between the two substrates or between the semiconductor chip and
the mounting substrate.
[0074] The above-disclosed subject matter is to be considered
illustrative, and not restrictive, and the appended claims are
intended to cover all such modifications, enhancements, and other
embodiments, which fall within the true spirit and scope of the
present invention. Thus, to the maximum extent allowed by law, the
scope of the present invention is to be determined by the broadest
permissible interpretation of the following claims and their
equivalents, and shall not be restricted or limited by the
foregoing detailed description.
* * * * *