U.S. patent application number 11/703900 was filed with the patent office on 2007-08-30 for chip stack package.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Se-Young Jeong, Soon-Bum Kim, Ung-Kwang Kim, Kang-Wook Lee, Sung-Min Sim, Young-Hee Song.
Application Number | 20070200216 11/703900 |
Document ID | / |
Family ID | 35479800 |
Filed Date | 2007-08-30 |
United States Patent
Application |
20070200216 |
Kind Code |
A1 |
Kim; Soon-Bum ; et
al. |
August 30, 2007 |
Chip stack package
Abstract
Provided is a chip stack package that may include a lower
semiconductor chip, an upper semiconductor chip stacked on the
lower semiconductor chip, and at least one adhesive formed in space
between the lower semiconductor chip and the upper semiconductor
chip. The at least one adhesive may include a first adhesive and a
second adhesive. The first adhesive may be formed in a portion of
the space, and the second adhesive may be formed in the space
except for a region in which the first adhesive is provided. The
space between adjacent semiconductor chips may be completely filled
with the at least one adhesive. Therefore, a chip stack package
according to the exemplary embodiments of the present invention may
exhibit improved mechanical stability and reliability.
Inventors: |
Kim; Soon-Bum; (Suwon-si,
KR) ; Kim; Ung-Kwang; (Yongin-si, KR) ; Lee;
Kang-Wook; (Suwon-si, KR) ; Jeong; Se-Young;
(Seoul, KR) ; Song; Young-Hee; (Yongin-si, KR)
; Sim; Sung-Min; (Seongnam-si, KR) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON
VA
20195
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
|
Family ID: |
35479800 |
Appl. No.: |
11/703900 |
Filed: |
December 19, 2006 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11038210 |
Jan 21, 2005 |
7151009 |
|
|
11703900 |
Dec 19, 2006 |
|
|
|
Current U.S.
Class: |
257/686 ;
257/E21.503; 257/E21.705; 257/E23.011; 257/E25.013 |
Current CPC
Class: |
H01L 2225/06541
20130101; H01L 2924/12042 20130101; H01L 2224/16145 20130101; H01L
2224/73204 20130101; H01L 25/0657 20130101; H01L 2224/05573
20130101; H01L 2924/12042 20130101; H01L 2924/15331 20130101; H01L
24/32 20130101; H01L 24/81 20130101; H01L 2924/15311 20130101; H01L
2224/274 20130101; H01L 2224/73203 20130101; H01L 23/3128 20130101;
H01L 2924/01029 20130101; H01L 23/3114 20130101; H01L 2225/06513
20130101; H01L 2924/14 20130101; H01L 2924/01079 20130101; H01L
2224/32225 20130101; H01L 2924/00 20130101; H01L 2224/73204
20130101; H01L 2224/16225 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2224/32145 20130101;
H01L 2224/32225 20130101; H01L 2224/16225 20130101; H01L 2224/32225
20130101; H01L 2224/16145 20130101; H01L 2224/73204 20130101; H01L
2924/15311 20130101; H01L 2224/8121 20130101; H01L 25/50 20130101;
H01L 24/29 20130101; H01L 2225/06582 20130101; H01L 2224/83191
20130101; H01L 21/563 20130101; H01L 2924/01033 20130101; H01L
2224/83194 20130101; H01L 23/481 20130101; H01L 2924/01006
20130101; H01L 2224/13025 20130101; H01L 2224/16225 20130101; H01L
2224/32145 20130101; H01L 2924/3511 20130101; H01L 2224/81815
20130101; H01L 2224/73204 20130101 |
Class at
Publication: |
257/686 |
International
Class: |
H01L 23/02 20060101
H01L023/02 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 18, 2004 |
KR |
2004-45567 |
Claims
1. A chip stack package including: a first semiconductor chip; a
second semiconductor chip stacked on the first semiconductor chip;
connector for electrically connecting the first semiconductor chip
to the second semiconductor chip; and at least one adhesive formed
in a space between the first semiconductor chip and the second
semiconductor chip, the at least one adhesive including a first
adhesive and a second adhesive, the first adhesive being formed in
a peripheral region on which the connector is provided, the second
adhesive being formed in the space remaining between the first
semiconductor chip and the second semiconductor chip except for a
region in which the first adhesive is provided.
2. The chip stack package according to claim 1, wherein the first
semiconductor chip includes a plurality of first conductive
connectors and the second semiconductor chip includes a plurality
of second conductive connectors, and the first conductive
connectors are electrically connected to corresponding second
conductive connectors through the connector.
3. The chip stack package according to claim 2, wherein the first
conductive connectors are formed in a peripheral region of the
first semiconductor chip and the second conductive connectors are
formed in a peripheral region of the second semiconductor chip.
4. The chip stack package according to claim 2, wherein the first
conductive connectors are formed in a central region of the first
semiconductor chip and the second conductive connectors are formed
in a central region of the second semiconductor chip.
5. The chip stack package according to claim 2, wherein the first
and second conductive connectors are through electrodes.
6. The chip stack package according to claim 5, wherein the
connector is conductive protrusions formed on at least one end of
the first and second conductive connectors.
7. The chip stack package according to claim 6, wherein the
conductive protrusions are conductive bumps.
8. The chip stack package according to claim 1, wherein the first
adhesive is formed by curing a flowable adhesive composition and
the second adhesive is a solid adhesive.
9. The chip stack package according to claim 1, wherein the first
adhesive has the material properties different from the second
adhesive.
10. The chip stack package according to claim 3, wherein the second
adhesive covers at least a central region of the first
semiconductor chip.
11. The chip stack package according to claim 8, wherein the second
adhesive is a multi-layer adhesive tape.
12. The chip stack package according to claim 11, wherein the
multi-layer adhesive tape includes a core layer between an upper
adhesive layer and a lower adhesive layer.
13. A chip stack package including: a substrate having an upper
surface and a lower surface; a first semiconductor chip stacked on
the upper surface of the substrate; a second semiconductor chip
stacked on the first semiconductor chip; connector for electrically
connecting the substrate to the first semiconductor chip and the
first semiconductor chip to the second semiconductor chip; and at
least one adhesive formed in spaces between the substrate and the
first semiconductor chip and between the first semiconductor chip
and the second semiconductor chip, the at least one adhesive
including a first adhesive and a second adhesive, the first
adhesive being formed in a peripheral region on which the connector
is provided, the second adhesive being formed in the spaces except
for a region in which the first adhesive is provided.
14. The chip stack package according to claim 13, wherein the
substrate has a plurality of substrate pads, the first
semiconductor chip includes a plurality of first conductive
connectors and the second semiconductor chip includes a plurality
of second conductive connectors, and the substrate pads are
electrically connected to the first conductive connectors through
the connector and the first conductive connectors are electrically
connected to the second conductive connectors through the
connector.
15. The chip stack package according to claim 14, wherein the first
conductive connectors are formed in a peripheral region of the
first semiconductor chip and the second conductive connectors are
formed in a peripheral region of the second semiconductor chip.
16. The chip stack package according to claim 14, wherein the first
conductive connectors are formed in a central region of the first
semiconductor chip and the second conductive connectors are formed
in a central region of the second semiconductor chip.
17. The chip stack package according to claim 14, wherein the first
and second conductive connectors are through electrodes.
18. The chip stack package according to claim 17, wherein the
connector is conductive protrusions formed on at least one end of
the first and second conductive connectors.
19. The chip stack package according to claim 18, wherein the
conductive protrusions are conductive bumps.
20. The chip stack package according to claim 13, wherein the first
adhesive is formed by curing a flowable adhesive composition and
the second adhesive is a solid adhesive.
21. The chip stack package according to claim 13, wherein the
second adhesive includes a substrate attaching adhesive for
attaching the substrate to the first semiconductor chip and a chip
attaching adhesive for attaching the second semiconductor chip to
the first semiconductor chip.
22. The chip stack package according to claim 13, wherein the first
adhesive has the material properties different from the second
adhesive.
23. The chip stack package according to claim 15, wherein the
second adhesive covers at least central regions of the substrate
and the first semiconductor chip.
24. The chip stack package according to claim 20, wherein the
second adhesive is a multi-layer adhesive tape.
25. The chip stack package according to claim 24, wherein the
multi-layer adhesive tape includes a core layer between an upper
adhesive layer and a lower adhesive layer.
26. The chip stack package according to claim 13, further including
external connection terminals formed on the lower surface of the
substrate.
Description
RELATED APPLICATION DATA
[0001] This application is a Continuation-In-Part of U.S. patent
application Ser. No. 11/038,210, filed on Jan. 21, 2005, now
pending, which claims priority under 35 U.S.C. .sctn. 119 of Korean
Patent Application No. 2004-45567, filed on Jun. 18, 2004, the
entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a chip stack package and,
more particularly, to a wafer level chip scale package.
[0004] 2. Description of the Related Art
[0005] The electronic industry is continually seeking methods,
techniques and designs that will result in the manufacture of
electronic products that are smaller, lighter, faster, more
efficient, operate at higher speeds, provide multiple functions
and/or result in improved performance, at an effective cost. One of
the methods that have been used for attaining such goals is
improved package assembly techniques that have resulted in the
development of new types of packages such as chip scale or chip
size packages (CSP). The CSPs may be manufactured at chip level or
at wafer level, with those manufactured at the wafer level also
referred to as wafer level chip scale packages (WLCSP).
[0006] Typically, a WLCSP will include a stack of a plurality of
semiconductor chips that are interconnected by bump connections.
For example, each semiconductor chip may include electrode pads
formed on the active surface and through electrodes formed at or
along the edges of the semiconductor chip. The through electrodes
may, in turn, be connected to the electrode pads by redistribution
lines. The corresponding through electrodes provided on adjacent
semiconductor chips may then be electrically connected with bump
connections. Although the semiconductor chips in the chip stack are
physically and electrically connected, the formation of such a
stack using only bump bonding tends to result in a space or void
being formed between the opposing surfaces of two adjacent
semiconductor chips. Such spaces may cause reduced mechanical
strength and increase the likelihood of reliability faults in the
chip stack package. Therefore, the space between adjacent
semiconductor chips should be filled to produce a stronger, more
durable chip stack package. In a conventional method for
manufacturing a WLCSP, liquid adhesive and/or adhesive tape may be
used to fill the space between adjacent semiconductor chips.
[0007] FIG. 1 is a cross-sectional view of an example of a
conventional WLCSP 130. The WLCSP 130 illustrated in FIG. 1 may be
manufactured by sequentially using wafer preparing, wafer stacking,
wafer sawing and liquid adhesive injection processes.
[0008] A plurality of substantially identical wafers (not shown),
each having a plurality of semiconductor chips 111, may be prepared
using any conventional semiconductor manufacturing process. Each
semiconductor chip 111 is provided with a plurality of through
electrodes 113 arranged in a peripheral region of the semiconductor
chip and bumps 117 formed on at least one end surface of the
through electrodes. Alternatively, instead of forming the bumps
117, the through electrodes 113 may be constructed so as to
protrude above a surrounding surface of the semiconductor chip 111
for providing connection between adjacent semiconductor
devices.
[0009] A plurality of such wafers are then vertically stacked so
that the corresponding through electrodes 113 and/or bumps 117 of
adjacent semiconductor chips 111 are aligned and brought into
contact so as to provide electrical connection between adjacent
semiconductor chips. The stacked wafers are then divided into
individual chip stack packages 130 and a liquid adhesive 123 may be
injected into a space remaining between adjacent semiconductor
chips 111 and cured to reduce or eliminate voids from the chip
stack package.
[0010] The WLCSP in which the spaces between adjacent semiconductor
chips has been filled with an adhesive may exhibit improved
mechanical strength and reliability in comparison with a similarly
constructed WLCSP in which the vacant spaces between the adjacent
semiconductor chips have not been filled.
[0011] However, because the liquid adhesive 123 used to fill the
spaces between the adjacent semiconductor chips 111 typically
includes metallic and/or non-metallic particulate filler materials,
its flow characteristics may make it difficult to fill the space(s)
between adjacent semiconductor chips completely or consistently,
particularly for chip stacks having relatively small chip-to-chip
spacing. Thus, as illustrated in FIG. 1, a WLCSP 130 manufactured
with such a liquid adhesive 123 may still include one or more
vacant spaces or voids 135 between adjacent semiconductor chips
111. One proposal for addressing the problem of voids in a WLCSP is
to use an adhesive tape rather than a liquid adhesive.
[0012] FIG. 2 is a cross-sectional view of another example of a
conventional WLCSP 230. The WLCSP 230 illustrated in FIG. 2 may be
manufactured by sequentially using wafer preparing, adhesive tape
attaching, wafer stacking and wafer sawing processes.
[0013] A plurality of substantially identical wafers (not shown),
each having a plurality of semiconductor chips 211, each having a
plurality of semiconductor chips 111, may be prepared using any
conventional semiconductor manufacturing process. Each
semiconductor chip 211 will typically include a plurality of
through electrodes 213 arranged in a peripheral region of the
semiconductor chip. The through electrodes 213 may be constructed
with protruding portions (not shown) that extend above the adjacent
surface of the semiconductor chip or may be provided with bumps 217
formed on at least on surface of the through electrodes.
[0014] An adhesive tape 221 may then be attached to the
semiconductor chip 211 while still at the wafer level, the adhesive
tape 221 typically having openings provided therein to avoid
interfering with the bumps 217 or protruding portions (not shown)
by maintaining some minimum separation distance between the
adhesive tape and the connecting structures.
[0015] A plurality of such wafers are then vertically stacked so
that the corresponding through electrodes 213 and bumps 217 of
adjacent semiconductor chips 211 are aligned and brought into
contact so as to provide electrical connection between adjacent
semiconductor chips. The stacked and connected wafers may then be
divided into individual chip stack packages 230.
[0016] A WLCSP manufactured using an adhesive tape may exhibit
improved filling performance and mechanical strength in comparison
with a WLCSP manufactured with a liquid adhesive. However, the
adhesive tape may result in uneven pressure being applied to one or
more of the semiconductor chips during a chip stacking process that
may result in warpage of one, or more of the semiconductor chips.
Further, as illustrated in FIG. 2, during the assembly process, the
temperature and/or pressures applied to the chip stack may be
sufficient to cause the adhesive tape composition 224 to liquefy
and flow out from between the adjacent semiconductor chips and onto
the lateral or side surfaces(s) of the package.
SUMMARY OF THE INVENTION
[0017] An exemplary embodiment of the present invention is directed
to a chip stack package having improved mechanical strength and
reliability.
[0018] The chip stack package in accordance with an exemplary
embodiment of the present invention may include a first
semiconductor chip, a second semiconductor chip stacked on the
first semiconductor chip, a connector for connecting the first
semiconductor chip to the second semiconductor chip, and at least
one adhesive formed in a space between the first semiconductor chip
and the second semiconductor chip. The at least one adhesive may
include a first adhesive and a second adhesive. The first adhesive
may be formed in a portion of the space between the first
semiconductor chip and the second semiconductor chip and be
positioned in a peripheral region on which the connector is
provided. The second adhesive may be formed in the space remaining
between the first semiconductor chip and the second semiconductor
chip except for a region in which the first adhesive is
provided.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Exemplary embodiments of the present invention will be
readily understood with reference to the detailed description
provided below when read in conjunction with the accompanying
drawings in which similar or identical reference numerals are used
to designate similar or corresponding structural elements, and in
which:
[0020] FIG. 1 is a cross-sectional view of an example of a
conventional WLCSP;
[0021] FIG. 2 is a cross-sectional view of another example of a
conventional WLCSP;
[0022] FIG. 3A-FIG. 3F are cross-sectional views of a method for
manufacturing a WLCSP in accordance with an exemplary embodiment of
the present invention; and
[0023] FIG. 4 is a cross-sectional view of a WLCSP manufactured by
a method in accordance with another exemplary embodiment of the
present invention.
[0024] These drawings are provided for illustrative purposes only
and are not drawn to scale. The spatial relationships and relative
sizing of the elements illustrated in the various embodiments may
have been reduced, expanded or rearranged to improve the clarity of
the figure with respect to the corresponding description. The
figures, therefore, should not be interpreted as accurately
reflecting the relative sizing or precise positioning of the
corresponding structural elements that could be encompassed by an
actual device manufactured according to the exemplary embodiments
of the invention.
DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
[0025] The present invention will now be described more fully
hereinafter with reference to the accompanying drawings, in which
exemplary embodiments of the invention are illustrated. In light of
this detailed description, those of ordinary skill in the art will
appreciate that this invention may be embodied in many different
forms and should not, therefore, be construed as limited to the
particular exemplary embodiments set forth herein. Rather, these
exemplary embodiments are provided so that this disclosure will be
thorough and complete, and will fully convey the scope of the
invention to those skilled in the art.
[0026] In the description, well-known structures and conventional
processes have not been described or illustrated in detail to avoid
obscuring the present invention. It will be appreciated that for
simplicity and clarity of illustration, some elements illustrated
in the figures have not necessarily been drawn to scale. For
example, the dimensions of some of the elements have been
exaggerated or reduced relative to other elements for clarity.
[0027] FIGS. 3A-3F are cross-sectional views of a method for
manufacturing a WLCSP in accordance with an exemplary embodiment of
the present invention. As illustrated in FIGS. 3A-3F, the disclosed
method for manufacturing a WLCSP includes the steps of providing a
plurality of wafers, applying a solid adhesive to at least one of
the wafers, stacking the wafers so that the solid adhesive is
positioned between two adjacent wafers, sawing the stacked wafers
to separate semiconductor chip stacks and applying a liquid
adhesive to the semiconductor chip stacks.
[0028] As illustrated in FIG. 3A, a wafer 10 may be prepared using
any appropriate semiconductor device manufacturing process. The
prepared wafer 10 will include a plurality of semiconductor chips
11, with each semiconductor chip including a plurality of through
electrodes 13 formed through a peripheral region of the
semiconductor chip. Conductive bumps 17 may then be formed on and
electrically connected to at least one end of the through
electrodes 13. The through electrodes 13 may, in turn, be
electrically connected to integrated circuits provided on an
interior region of the semiconductor chips 11 by conductive
redistribution patterns (not shown). Alternatively, the through
electrodes 13 may constructed so as to include a protruding portion
that extends above the surrounding surface of the semiconductor
chip 11 and eliminate the need to form bumps. The conductive bumps
17 may include solder, nickel, gold, copper, metal alloys or other
materials having suitable electrical conductivity and are capable
of forming conductive bonds with the material(s) used to form the
through electrodes, i.e., good bondability.
[0029] Although this exemplary embodiment show the through
electrodes 13 formed through the peripheral region of the
semiconductor chip 11, the through electrodes 13 may be not limited
in this regard. For example, the through electrodes 13 may be
formed in a central region of the semiconductor chip 11.
[0030] As illustrated in FIG. 3B, a solid adhesive 21 as a second
adhesive, for example an adhesive tape or sheet, is attached to or
formed on a portion of a surface of the semiconductor chips 11
formed on the wafer 10. The solid adhesive 21 may be formed on an
interior region of a surface of the semiconductor chip 11 and be
located completely within the peripheral surface region through
which the through electrodes 13 are formed and on which the bumps
17 may be attached. The solid adhesive 21 will typically be sized
and configured so as to maintain a minimum spacing between the
solid adhesive and any protruding portions of the through
electrodes 13 or bumps 17 and so that the solid adhesive defines
the perimeter of the space or void in which the through electrodes
or bumps are positioned. The space or void will also have at least
one open side adjacent a side or lateral surface of the
semiconductor chips to allow for the subsequent introduction of a
flowable adhesive composition.
[0031] The solid adhesive 21 used in this exemplary embodiment may
be a multi-layer adhesive tape that includes an intermediate base
film 21a with adhesive layers 21b provided on both sides of the
base film to provide the desired strength and adhesive performance.
It will be appreciated that other solid adhesive materials, such as
a single layer tape or an alternate multi-layer adhesive tape
having other or different layers to provide particular performance
modifications, may be used. It will also be appreciated that the
solid adhesive may be formed in place by printing or otherwise
depositing an adhesive composition on designated portions of the
surface of the semiconductor chips 11 and is not, therefore,
limited to any particular construction of or method of forming the
solid adhesive 21.
[0032] If the through electrodes 13 are formed in the peripheral
region of the semiconductor chip 11, the solid adhesive 21 may be
formed in a central region of the semiconductor chip 11 or be
formed in a portion of the peripheral region on which the through
electrodes 13 are provided, including the central region.
[0033] As illustrated in FIG. 3C, after the solid adhesive has been
provided on the wafer surface, a plurality of wafers can then be
aligned and vertically stacked to interconnect corresponding
semiconductor chips 11 on adjacent wafers by connecting
corresponding electrodes 13 and/or bumps 17 to provide both
mechanical and electrical connections between the adjacent
semiconductor chips. The adjacent semiconductor chips 11 will also
be attached by the solid adhesive 21 arranged between the opposing
surfaces of the semiconductor chips. The solid adhesive 21 may also
provide some resilience that will allow for absorption or dampening
of at least some of the physical or mechanical shocks to which the
semiconductor chip 11 may be subjected during manufacture
including, for example, forces applied during the wafer stacking
process.
[0034] As illustrated in FIG. 3D, after the stacking operation, the
stacked wafers 10 may be divided into individual chip stack
packages including a plurality of vertically stacked semiconductor
devices 11. The wafers 10 may, for example, be separated along
scribe lines 15 using a high-speed rotary diamond blade 50, a laser
beam scribing apparatus or any other suitable apparatus for
removing or weakening those portions of the wafers that lie between
adjacent semiconductor chips so that the chip stack packages may be
separated.
[0035] As illustrated in FIG. 3E, a flowable adhesive composition
23 as a first adhesive may then be injected into the spaces
remaining between the adjacent semiconductor chips 11. For example,
the flowable adhesive composition 23 may be a liquid adhesive that
is applied sequentially or simultaneously into the portions of the
space between the semiconductor chips 11 that are exposed along the
lateral or side surfaces of the semiconductor chips. When using a
liquid adhesive, the flowable adhesive composition 23 may be
injected into or otherwise inserted or deposited into the space.
The flowable adhesive composition will typically flow into the
space or void from the lateral edge of the semiconductor chip to
the exterior portion of the solid adhesive 21 at least partially as
the result of capillary action and, in so doing, will surround and
encapsulate those portions of the through electrodes 13 and/or
bumps 17 that are present within the space. In this manner, the
spaces or voids between the adjacent semiconductor chips 11 may be
completely filled with the first adhesive and the second adhesive.
The flowable adhesive composition 23 may include liquid adhesive
such as an epoxy resin adhesive, an adhesive suspension or a fine
powder.
[0036] After application, the flowable adhesive composition 23 may
be cured by any appropriate method including, for example,
self-curing, heating or UV irradiation. The cured flowable adhesive
composition 23 may become a first adhesive of the resulting
package. The exemplary embodiment of the manufacturing method
described above may produce a completed WLCSP 30 as illustrated in
FIG. 3F.
[0037] The WLCSP manufactured by a method in accordance with the
exemplary embodiment described above will tend to increase the
extent to which the space formed between adjacent semiconductor
chips may be filled by using a combination of a first adhesive (a
flowable adhesive composition) and a second adhesive (a solid
adhesive). By locating the solid adhesive on a more central portion
of the surface of the semiconductor chip, both the space that the
later-applied flowable adhesive composition will be filling and the
strength requirements for the cured flowable adhesive composition
may be reduced. Similarly, because the flowable adhesive
composition will no longer need to flow to the center of the
semiconductor chip, the flow channel length will be reduced
accordingly. If; for example, the distance between adjacent
semiconductor chips is 30 .mu.m or less, a range of conventional
liquid adhesive compositions may be used for filling the space. It
is expected that in most instances the distance between adjacent
semiconductor chips is will be between about 10 .mu.m and 50
.mu.m.
[0038] Although this exemplary embodiment shows at least one
adhesive including a solid adhesive and a flowable adhesive
composition, the at least one adhesive may not be limited in this
regard. For example, the at least one adhesive may be selected
according to various standards, for example, TG (glass transition
temperature), Young's Modulus or CTE (Coefficient of Thermal
Expansion).
[0039] FIG. 4 is a cross-sectional view of a WLCSP 70 in accordance
with another exemplary embodiment of the present invention. As
illustrated in FIG. 4, the WLCSP 70 may further include a substrate
on which the lowermost semiconductor chip 11' of a WLCSP such as
that illustrated in FIG. 3F may be mounted or, alternatively, to
which a WLCSP may be attached. As illustrated in FIG. 4, in the
lowest semiconductor chip 1' the through electrodes 13 may be
bump-bonded to corresponding substrate pads 43.
[0040] The lowest semiconductor chip 11' may be attached to the
substrate 41 using a solid adhesive 21', which may be the same
solid adhesive 21 that is used to attach adjacent semiconductor
chips 11, 11' within the chip stack. An epoxy resin adhesive may be
injected into a space or void remaining between the substrate 41
and the lowest semiconductor chip 11' except for a region in which
the solid adhesive 21' is provided. The epoxy resin adhesive may be
cured to completely fill the spaces or voids between the substrate
41 and the lowest semiconductor chip 11'. Connecting bumps 45 may
be provided on a surface of the substrate 41 separated from the
chip stack, typically on a surface of the substrate 41 opposite the
surface to which the chip stack is attached, for allowing
connection of the stacked semiconductor chips 11, 11'.alpha.to
external devices or circuits and thereby complete formation of the
WLCSP 70.
[0041] Although in this exemplary embodiment, a solid adhesive 21'
used in attaching the lowest semiconductor chip 11' to the
substrate 41 is the same solid adhesive 21 that is used to attach
adjacent semiconductor chips 11, 11' within the chip stack, the
solid adhesive 21' may not be necessarily the same solid adhesive
that is used to attach adjacent semiconductor chips 11, 11' within
the chip stack.
[0042] Accordingly, a method for manufacturing a WLCSP in
accordance with an exemplary embodiment of the present invention
may improve physical or mechanical stability and reliability during
a chip stacking process at wafer level or chip level. The
sufficiency of the bump connections may be inspected or otherwise
tested after the chip stacking process to confirm that the
connection process was at least nominally successful. Sample
devices may be subjected to additional destructive and/or
accelerated life testing for evaluating the yield and stability of
the produced WLCSP devices.
[0043] Although certain exemplary embodiments of the present
invention have been described in detail above, it should be
understood that many variations and/or modifications of the basic
inventive concepts herein taught, which may appear to those skilled
in the art, will still fall within the spirit and scope of the
exemplary embodiments of the present invention as defined in the
appended claims. For example, the present invention may be employed
in a chip stack package having a stack structure that utilizes a
flip chip bonding process at the chip level. Further, the present
invention may be incorporated in the manufacture of semiconductor
devices having a space between wafers, between semiconductor chips,
and/or between a single semiconductor chip or a chip stack and a
substrate.
* * * * *