U.S. patent application number 11/307615 was filed with the patent office on 2007-08-16 for 3-d package stacking system.
This patent application is currently assigned to STATS CHIPPAC LTD.. Invention is credited to Seng Guan Chow, Byung Joon Han, Il Kwon Shim.
Application Number | 20070187826 11/307615 |
Document ID | / |
Family ID | 38367538 |
Filed Date | 2007-08-16 |
United States Patent
Application |
20070187826 |
Kind Code |
A1 |
Shim; Il Kwon ; et
al. |
August 16, 2007 |
3-D PACKAGE STACKING SYSTEM
Abstract
The present invention provides a system for 3D package stacking
system, comprising providing a substrate, attaching a ball grid
array package, in an inverted position, to the substrate, forming a
lower package, the lower package having the ball grid array package
and the substrate encapsulated by a molding compound and attaching
a second integrated circuit package over the lower package.
Inventors: |
Shim; Il Kwon; (Singapore,
SG) ; Han; Byung Joon; (Singapore, SG) ; Chow;
Seng Guan; (Singapore, SG) |
Correspondence
Address: |
ISHIMARU & ZAHRT LLP
333 W. EL CAMINO REAL
SUITE 330
SUNNYVALE
CA
94087
US
|
Assignee: |
STATS CHIPPAC LTD.
5 Yishun Street 23
Singapore
SG
|
Family ID: |
38367538 |
Appl. No.: |
11/307615 |
Filed: |
February 14, 2006 |
Current U.S.
Class: |
257/738 ;
257/E25.023 |
Current CPC
Class: |
H01L 2224/73265
20130101; H01L 2224/48091 20130101; H01L 24/73 20130101; H01L
2224/48465 20130101; H01L 2224/48465 20130101; H01L 2924/00014
20130101; H01L 2224/32225 20130101; H01L 2225/1058 20130101; H01L
2924/15311 20130101; H01L 2924/19107 20130101; H01L 23/3128
20130101; H01L 2224/48465 20130101; H01L 25/105 20130101; H01L
2224/73265 20130101; H01L 2924/181 20130101; H01L 2924/181
20130101; H01L 2924/00014 20130101; H01L 2224/48091 20130101; H01L
2225/1023 20130101; H01L 2924/14 20130101; H01L 25/03 20130101;
H01L 2225/1052 20130101; H01L 2224/73207 20130101; H01L 2224/73253
20130101; H01L 2924/00014 20130101; H01L 2924/19105 20130101; H01L
24/48 20130101; H01L 2224/16225 20130101; H01L 25/16 20130101; H01L
2924/15311 20130101; H01L 2224/48227 20130101; H01L 2924/00012
20130101; H01L 2924/00 20130101; H01L 2224/48227 20130101; H01L
2924/00014 20130101; H01L 2924/00012 20130101; H01L 2924/19041
20130101; H01L 2924/207 20130101; H01L 2224/45099 20130101; H01L
2224/48227 20130101; H01L 2224/32225 20130101; H01L 2224/45015
20130101; H01L 2224/32225 20130101; H01L 2924/00 20130101; H01L
2224/48091 20130101; H01L 2924/00 20130101; H01L 2224/73265
20130101; H01L 2224/48227 20130101 |
Class at
Publication: |
257/738 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Claims
1. A system for 3D package stacking system, comprising: providing a
substrate; attaching a ball grid array package, in an inverted
position, to the substrate; forming a lower package, the lower
package having the ball grid array package and the substrate
encapsulated by a molding compound; and attaching a second
integrated circuit package over the lower package.
2. The system as claimed in claim 1 further comprising forming a
BGA interposer in the ball grid array package.
3. The system as claimed in claim 1 further comprising attaching an
encapsulated integrated circuit between the substrate and the ball
grid array package within the lower package.
4. The system as claimed in claim 1 further comprising mounting an
IC spacer over an integrated circuit die attached between the
substrate and the ball grid array package.
5. The system as claimed in claim 1 further comprising applying an
underfill material to stabilize the second integrated circuit
package mounted over the lower package.
6. A 3D package stacking system, comprising: providing a substrate
having embedded components electrically attached to a top substrate
surface; attaching a ball grid array package, in an inverted
position, to the substrate further comprises connecting a bond wire
between the substrate and the ball grid array package; forming a
lower package, the lower package having the ball grid array package
and the substrate encapsulated by a molding compound, wherein
solder balls of the ball grid array package protrude from the
molding compound of the lower package; and attaching a second
integrated circuit package over the lower package further comprises
providing a signal path through the lower package to a printed
circuit board interface.
7. The system as claimed in claim 6 further comprising forming a
BGA interposer in the ball grid array package, wherein the BGA
interposer establishes the connection pattern for the second
integrated circuit package mounted over the lower package.
8. The system as claimed in claim 6 further comprising attaching an
encapsulated integrated circuit between the substrate and the ball
grid array package, wherein the encapsulated integrated circuit is
electrically attached to the substrate and the ball grid array
package.
9. The system as claimed in claim 6 further comprising utilizing an
IC spacer over an integrated circuit die attached between the
substrate and the ball grid array package, wherein the die is
electrically attached to the substrate and the ball grid array
package.
10. The system as claimed in claim 6 further comprising applying an
underfill material to stabilize the second integrated circuit
package mounted over the lower package.
11. A 3D package stacking system, comprising: a substrate; a ball
grid array package, in an inverted position, attached to the
substrate; a lower package comprising the ball grid array package
and the substrate encapsulated by a molding compound; and a second
integrated circuit package attached over the lower package.
12. The system as claimed in claim 11 further comprising a BGA
interposer in the ball grid array package.
13. The system as claimed in claim 11 further comprising an
encapsulated integrated circuit attached between the substrate and
the ball grid array package.
14. The system as claimed in claim 11 further comprising an IC
spacer mounted over an integrated circuit die attached between the
substrate and the ball grid array package.
15. The system as claimed in claim 11 further comprising an
underfill material to stabilize the second integrated circuit
package mounted over the lower package.
16. The system as claimed in claim 11, wherein a substrate, a ball
grid array package, in an inverted position, attached to the
substrate, a lower package comprising the ball grid array package
and the substrate encapsulated by a molding compound and a second
integrated circuit package attached over the lower package; further
comprising: embedded components electrically attached to a top
substrate surface; a bond wire connected between the substrate and
the ball grid array package; solder balls of the ball grid array
package protrude from the molding compound of the lower package;
and a signal path for the second integrated circuit package through
the lower package to a printed circuit board interface.
17. The system as claimed in claim 16 further comprising a BGA
interposer in the ball grid array package, wherein the BGA
interposer establishes the connection pattern for the second
integrated circuit package mounted over the lower package.
18. The system as claimed in claim 16 further comprising an
encapsulated integrated circuit attached between the substrate and
the ball grid array package, wherein the encapsulated integrated
circuit is electrically attached to the substrate and the ball grid
array package.
19. The system as claimed in claim 16 further comprising an IC
spacer, mounted over an integrated circuit die, attached between
the substrate and the ball grid array package, wherein the die is
electrically attached to the substrate and the ball grid array
package.
20. The system as claimed in claim 16 further comprising an
underfill material to stabilize the second integrated circuit
package mounted over the lower package.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application contains subject matter related to a
concurrently filed U.S. patent application Ser. No. 11/354,806,
assigned to STATS ChipPAC Ltd.
[0002] The present application contains subject matter related to
co-pending U.S. patent application Ser. No. 11/306,627, assigned to
STATS ChipPAC Ltd.
[0003] The present application contains subject matter also related
to co-pending U.S. patent application Ser. No. 11/306,628, assigned
to STATS ChipPAC Ltd.
[0004] The present application contains subject matter also related
to co-pending U.S. patent application Ser. No. 11/326,211, assigned
to STATS ChipPAC Ltd.
[0005] The present application contains subject matter also related
to co-pending U.S. patent application Ser. No. 11/326,206, assigned
to STATS ChipPAC Ltd.
TECHNICAL FIELD
[0006] The present invention relates generally to integrated
circuit package systems, and more particularly to a system for
stacking 3D package structures.
BACKGROUND ART
[0007] In the electronics industry, as products such as cell
phones, camcorders and digital media players become smaller and
smaller, increased miniaturization of integrated circuit (IC) or
chip packages has become more and more critical. At the same time,
higher performance and lower cost have become essential for new
products.
[0008] In response to the demands for newer packaging, many
innovative package designs have been conceived and brought to
market. The multi-chip module has achieved a prominent role in
reducing the board space used by modern electronics. However,
multi-chip modules, whether vertically or horizontally arranged,
can also present problems because they usually must be assembled
before the component chips and chip connections can be tested. That
is, because the electrical bond pads on a die are so small, it is
difficult to test die before assembly onto a substrate. Thus, when
die are mounted and connected individually, the die and connections
can be tested individually, and only known-good-die ("KGD") that is
free of defects is then assembled into larger circuits. A
fabrication process that uses KGD is therefore more reliable and
less prone to assembly defects introduced due to bad die. With
conventional multi-chip modules, however, the die cannot be
individually identified as KGD before final assembly, leading to
KGD inefficiencies and assembly process yield problems.
[0009] A multi-chip module may include stacking multiple die in a
package. Two of the common die stacking methods are: (a) larger
lower die combined with a smaller upper die, and (b) so-called
same-size die stacking. With the former, the die can be very close
vertically because the electrical bond pads on the perimeter of the
lower die extend beyond the edges of the smaller die on top. With
same-size die stacking, the upper and lower die are spaced more
vertically apart to provide sufficient clearance for the wire bonds
to the lower die. As discussed, both these methods have inherent
KGD and assembly process yield loss disadvantages since KGD cannot
be used for fabricating these configurations.
[0010] Another previous design is package level stacking or package
on package (POP). This concept includes stacking of two or more
packages. KGD and assembly process yields are not an issue since
each package can be tested prior to assembly, allowing KGD to be
used in assembling the stack. But package level stacking can pose
other problems. One problem is package-to-package assembly process
difficulties caused by irregularities in the flatness/coplanarity
of the lower package. Another problem results from the increased
stiffness of the overall assembly, which can lead to reduced board
level reliability. Still another problem can arise from poor heat
dissipation from the upper package. Thus, despite the advantages of
recent developments in semiconductor fabrication and packaging
techniques, there is a continuing need for improved packaging
methods, systems, and designs for increasing semiconductor die
density in PCB assemblies.
[0011] Thus, a need still remains for an efficient 3D package
stacking process. In view of the ever-increasing need to save costs
and improve efficiencies, it is more and more critical that answers
be found to these problems. Solutions to these problems have been
long sought but prior developments have not taught or suggested any
solutions and, thus, solutions to these problems have long eluded
those skilled in the art.
DISCLOSURE OF THE INVENTION
[0012] The present invention provides a system for 3D Package
stacking system, comprising providing a substrate, attaching a ball
grid array package, in an inverted position, to the substrate,
forming a lower package, the lower package having the ball grid
array package and the substrate encapsulated by a molding compound
and attaching a second integrated circuit package over the lower
package.
[0013] Certain embodiments of the invention have other aspects in
addition to or in place of those mentioned or obvious from the
above. The aspects will become apparent to those skilled in the art
from a reading of the following detailed description when taken
with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a cross-sectional view of a 3D package stacking
system, in an embodiment of the present invention;
[0015] FIG. 2 is a bottom view of the first BGA interposer of FIG.
1;
[0016] FIG. 3 is a cross-sectional view of a 3D package stacking
system, in an alternative embodiment of the present invention;
[0017] FIG.4 is a cross-sectional view of a 3D package stacking
system, in another alternative embodiment of the present
invention;
[0018] FIG.5 is a cross-sectional view of a 3D package stacking
system, in yet another alternative embodiment of the present
invention;
[0019] FIG. 6 is a cross-sectional view of a wafer level chip scale
package, in an alternative embodiment of the 3D package stacking
system of FIG. 1;
[0020] FIG. 7 is a cross-sectional view of the 3D package stacking
system, in an intermediate stage of fabrication; and
[0021] FIG. 8 is a flow chart of a system for 3D package stacking
system in an embodiment of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
[0022] In the following description, numerous specific details are
given to provide a thorough understanding of the invention.
However, it will be apparent that the invention may be practiced
without these specific details. In order to avoid obscuring the
present invention, some well-known circuits, system configurations,
and process steps are not disclosed in detail. Likewise, the
drawings showing embodiments of the device are semi-diagrammatic
and not to scale and, particularly, some of the dimensions are for
the clarity of presentation and are shown greatly exaggerated in
the drawing FIGs. In addition, where multiple embodiments are
disclosed and described having some features in common, for clarity
and ease of illustration, description, and comprehension thereof,
the same numbers are used in all the drawing FIGs. to relate to the
same elements.
[0023] The term "horizontal" as used herein is defined as a plane
parallel to the conventional plane or surface of the attached die
regardless of its orientation. The term "vertical" refers to a
direction perpendicular to the horizontal as just defined. Terms,
such as "on", "above", "below", "bottom", "top", "side" (as in
"sidewall"), "higher", "lower", "upper", "over", and "under", are
defined with respect to the horizontal plane. The term "processing"
as used herein includes deposition of material or photoresist,
patterning, exposure, development, etching, cleaning, and/or
removal of the material or photoresist as required in forming a
described structure.
[0024] Referring now to FIG. 1, therein is shown a cross-sectional
view of a 3D package stacking system 100, in an embodiment of the
present invention. The 3D package stacking system 100 includes a
substrate 102, having a top substrate surface 104 and a bottom
substrate surface 106, embedded components 108, such as filter
capacitors, inductors, diodes, voltage regulators or resistors. The
3D package stacking system 100 also includes a first ball grid
array package 110 mounted inverted, on the top substrate surface
104, utilizing an adhesive 112, such as die attach material, film
adhesive or thermal epoxy. The first ball grid array package 110
can be electrically and functionally tested prior to assembly. The
first ball grid array package 110 comprises a first integrated
circuit 114 mounted on a first BGA interposer 116 with a die attach
material 118. The first BGA interposer 116 may be assembled from a
material such as glass epoxy laminate, flexible circuit tape,
ceramic or resin coated metal alloy. Electrical interconnects 120,
such as bond wires, electrically connect the first integrated
circuit 114 to the first BGA interposer 116 and to the top
substrate surface 104. The first integrated circuit 114, the
electrical interconnects 120 and the die attach material 118 are
encapsulated in a first molding compound 122. First interface
interconnects 124, such as solder balls, stud bumps or solder
column interposers, are attached to terminal pads 126.
[0025] A second molding compound 128 encapsulates the first ball
grid array package 110, the embedded components 108, the electrical
interconnects 120 and the top substrate surface 104. During the
application of the second molding compound 128, a film assisted
molding technique is used to leave the top surface of the first
interface interconnects 124 exposed for further connection.
[0026] A second integrated circuit package 130 is electrically
connected to the exposed array of the first interface interconnects
124. The second integrated circuit package 130 can be electrically
and functionally tested prior to assembly. The second integrated
circuit package 130 comprises a second BGA interposer 132, having a
second integrated circuit 134 attached to the second BGA interposer
132 with the die attach material 118. The second BGA interposer 132
is assembled from a material such as glass epoxy laminate, flexible
circuit tape, ceramic or resin coated metal alloy. The second
integrated circuit 134 is electrically connected to the second BGA
interposer 132 by the electrical interconnects 120.
[0027] A signal originating in the second integrated circuit 134
would propagate through the electrical interconnects 120, through
the second BGA interposer 132, through the terminal pads 126 and
the first interface interconnects 124. When the signal enters the
first BGA interposer 116, it can either be routed to the first
integrated circuit 114, to the substrate 102 or both. The signal
path to the printed circuit board (not shown) is completed by
substrate contacts 138 and second interface connections 140, such
as solder balls, stud bumps or solder columns.
[0028] Referring now to FIG. 2, therein is shown a bottom view of
the first BGA interposer 116 of FIG. 1. The bottom view of the
first BGA interposer 116 depicts the first interface interconnects
124 mounted on the terminal pads 126, of FIG. 1. An interposer
substrate 202 supports bond fingers 204, the terminal pads 126 of
FIG. 1 and the first interface interconnects 124. The interposer
substrate 202 may be assembled from a material such as glass epoxy
laminate, flexible circuit tape, ceramic or resin coated metal
alloy. The array of the first interface interconnects 124 is shown
for demonstration purposes. The actual number of elements in the
array of the first interface interconnects 124 can be any number as
required. Each of the bond fingers 204 is electrically connected to
one or more of the first interface interconnects 124. The
connections are made through substrate traces (not shown) or
embedded wires (not shown) in the first BGA interposer 116.
[0029] Referring now to FIG. 3, therein is shown a cross-sectional
view of a 3D package stacking system 300, in an alternative
embodiment of the present invention. The 3D package stacking system
300 depicts the substrate 102 having the embedded components 108
electrically attached to the top substrate surface 104. A third
integrated circuit 302 is mounted on the top substrate surface 104
with the die attach material 118. The electrical interconnects 120,
such as bond wires, electrically connect the third integrated
circuit 302 to the top substrate surface 104 for further
interconnect. The third integrated circuit 302 can be electrically
and functionally tested once it is mounted to the substrate 102.
Once it is verified to be a KGD, the third integrated circuit 302
is encapsulated in a fourth molding compound 304 for further
assembly.
[0030] A third ball grid array package 306 is inverted and mounted
on the fourth molding compound 304 utilizing the adhesive 112. The
third ball grid array package 306 is electrically and functionally
tested prior to mounting. The third ball grid array package 306
comprises a fourth integrated circuit 308 mounted on a third BGA
interposer 310 with the die attach material 118 encapsulated in a
fifth molding compound 312. The electrical interconnects 120, such
as bond wires, electrically connect the fourth integrated circuit
308 to the third BGA interposer 310 and to the top substrate
surface 104. Any signal communication between the third integrated
circuit 302 and the fourth integrated circuit 308 is through
electrical connections (not shown) in the substrate 102.
[0031] The third BGA interposer 310 has the terminal pads 126, with
the first interface interconnects 124 attached, and the bond
fingers 204 electrically connected to the top substrate surface
104, by the electrical interconnects 120, such as bond wires. The
second molding compound 128 encapsulates the third ball grid array
package 306, the fourth molding compound 304, the electrical
interconnects 120, the embedded components 108 and a portion of the
top substrate surface 104. During the application of the second
molding compound 128, a film assisted molding technique is used to
leave the top surface, of the first interface interconnects 124,
exposed for further connection. An additional BGA package, such as
the second integrated circuit package 130, is electrically attached
to the exposed portion of the first interface interconnects 124. In
this example it is understood that the second integrated circuit
package 130 is only an example and any compatible BGA package could
be electrically connected to the first interface interconnects 124.
The signal path to the printed circuit board (not shown) is through
the substrate contacts 138 on the bottom substrate surface 106 and
the second interface connections 140, such as solder balls, stud
bumps or solder columns.
[0032] Referring now to FIG. 4, therein is shown a cross-sectional
view of a 3D package stacking system 400, in an alternative
embodiment of the present invention. The 3D package stacking system
400 includes the substrate 102 having an integrated circuit die 402
attached to the top substrate surface 104 with the die attach
material 118. The integrated circuit die 402 is electrically
connected to the substrate 102 with the electrical interconnects
120, such as bond wires. The embedded components 108 are added to
the top substrate surface 104, then the assembly is electrically
and functionally tested in order to verify the KGD prior to further
assembly.
[0033] An IC spacer 404 is applied to the integrated circuit die
402 in order to allow a clearance for the electrical interconnects
120. The third ball grid array package 306, or a different BGA
package of similar construction, is inverted and attached to the IC
spacer 404. The third ball grid array package 306 is electrically
connected to the top substrate surface 104 with the electrical
interconnects 120, such as bond wires. The first interface
interconnects 124 are attached to the terminal pads 126 of the
third ball grid array package 306.
[0034] The second molding compound 128 encapsulates the third ball
grid array package 306, the integrated circuit die 402, the IC
spacer 404, the electrical interconnects 120, the embedded
components 108 and a portion of the top substrate surface 104.
During the application of the second molding compound 128, a film
assisted molding technique is used to leave the top surface, of the
first interface interconnects 124, exposed for further connection.
An additional BGA package, such as the second integrated circuit
package 130, is electrically attached to the exposed portion of the
first interface interconnects 124. In this example it is understood
that the second integrated circuit package 130 is only an example
and any compatible BGA package could be electrically connected to
the first interface interconnects 124. The signal path to the
printed circuit board (not shown) is through the substrate contacts
138 on the bottom substrate surface 106 and the second interface
connections 140, such as solder balls, stud bumps or solder
columns.
[0035] Referring now to FIG. 5, therein is shown a cross-sectional
view of a 3D package stacking system 500, in yet another
alternative embodiment of the present invention. The 3D package
stacking system 500 includes the substrate 102 having the first
ball grid array package 110 inverted and attached to the top
substrate surface 104 with the adhesive 112. The first ball grid
array package 110 is electrically and functionally tested prior to
assembly. The embedded components 108 are electrically attached to
the top substrate surface 104, the electrical interconnects 120,
such as bond wires, electrically connect the first ball grid array
package 110 to the top substrate surface 104 and the first
interface interconnects 124 are attached to the terminal pads 126
of the first ball grid array package 110.
[0036] The second molding compound 128 encapsulates the first ball
grid array package 110, the electrical interconnects 120, the
embedded components 108 and a portion of the top substrate surface
104. During the application of the second molding compound 128, a
film assisted molding technique is used to leave the top surface,
of the first interface interconnects 124, exposed for further
connection.
[0037] An additional package, such as the second integrated circuit
package 130, is electrically attached to the exposed portion of the
first interface interconnects 124. In this example it is understood
that the second integrated circuit package 130 is only an example
and any compatible BGA package, land grid array package, leaded
package, QFN package or direct chip attach could be electrically
connected to the first interface interconnects 124.
[0038] An underfill material 502 is injected under the second
integrated circuit package 130. The underfill material 502 is used
to stabilize the second integrated circuit package 130 and remove
stress from the first interface interconnects 124. The signal path
to the printed circuit board (not shown) is through the substrate
contacts 138 on the bottom substrate surface 106 and the second
interface connections 140, such as solder balls, stud bumps or
solder columns.
[0039] Referring now to FIG. 6, therein is shown a cross-sectional
view of a wafer level chip scale package 600, in an alternative
embodiment of the 3D package stacking system 100 of FIG. 1. The
wafer level chip scale package 600 includes a redistributed line
die 602 attached to the top substrate surface 104, of the substrate
102, with the adhesive 112. Contact pads 604 arranged around the
periphery of the redistributed line die 602 are electrically
connected to the top substrate surface 104 with the electrical
interconnects 120. Bump pads 606 are arrayed in the interior space
of the redistributed line die 602 and are attached to the first
interface interconnects 124. The embedded components 108 are
electrically connected to the top substrate surface 104 of the
substrate 102 and the redistributed line die 602 is electrically
and functionally tested prior to further assembly.
[0040] The second molding compound 128 encapsulates the
redistributed line die 602, the embedded components 108, the
electrical interconnects 120, the first interface interconnects 124
and a portion of the top substrate surface 104. During the
application of the second molding compound 128, a film assisted
molding technique is used to leave the top surface, of the first
interface interconnects 124, exposed for further connection.
[0041] An additional package, such as the second integrated circuit
package 130, is electrically attached to the exposed portion of the
first interface interconnects 124. In this example it is understood
that the second integrated circuit package 130 is only an example
and any compatible BGA package, land grid array package, leaded
package or direct chip attach could be electrically connected to
the first interface interconnects 124.
[0042] The underfill material 502 is injected under the second
integrated circuit package 130. The underfill material 502 is used
to stabilize the second integrated circuit package 130 and remove
stress from the first interface interconnects 124. The signal path
to the printed circuit board (not shown) is through the substrate
contacts 138 on the bottom substrate surface 106 and the second
interface connections 140, such as solder balls, stud bumps or
solder columns.
[0043] Referring now to FIG. 7, therein is shown a cross-sectional
view of the 3D package stacking system 100, in an intermediate
stage of fabrication. The 3D package stacking system 100 includes a
lower package 702, such as a package in package, having the first
ball grid array package 110 inverted and attached to the top
substrate surface 104, of the substrate 102, with the adhesive 112.
The electrical interconnects 120 connect the first ball grid array
package 110 to the top substrate surface 104. The embedded
components 108 are electrically connected to the top substrate
surface 104 and the first interface interconnects 124 are attached
to the terminal pads 126 of the first ball grid array package
110.
[0044] The second molding compound 128 encapsulates the first ball
grid array package 110, the embedded components 108, the electrical
interconnects 120 and partially the top substrate surface 104.
During the application of the second molding compound 128, a film
assisted molding technique is used to leave the top surface, of the
first interface interconnects 124, exposed for further connection.
An alternative process for exposing the first interface
interconnects 124 is to use a chemical mechanical planarization
process to cut down the top planar layer of the lower package 702.
The first interface interconnects 124 that are exposed can be
flattened to a planar surface by coining, pressing, polishing or
lapping as well. Another option is that the first interface
interconnects 124 can be flattened during the molding process. In
order to facilitate this process, the material used for the first
interface interconnects 124 would have to be characterized as
having softness that the deformation in response to the mold chase
clamping force would not cause the damage to the BGA interposer 116
or the mold chase (not shown).
[0045] An additional package, such as the second integrated circuit
package 130, is electrically attached to the exposed portion of the
first interface interconnects 124. In this example it is understood
that the second integrated circuit package 130 is only an example
and any compatible BGA package, land grid array package, leaded
package, QFN package or direct chip attach could be electrically
connected to the first interface interconnects 124.
[0046] Referring now to FIG. 8, therein is shown a flow chart of a
method for producing a 3D package stacking system 800 for 3D
package stacking system 100 in an embodiment of the present
invention. The system 800 includes providing a substrate in a block
802; attaching a ball grid array package, in an inverted position,
to the substrate in a block 804; forming a lower package, the lower
package having the ball grid array package and the substrate
encapsulated by a molding compound in a block 806; and attaching a
second integrated circuit package over the lower package in a block
808.
[0047] In greater detail, a method for fabricating a 3D package
stacking system, in an embodiment of the present invention, is
performed as follows: [0048] 1. Providing a substrate having
embedded components electrically attached to a top substrate
surface. (FIG. 1) [0049] 2. Attaching a ball grid array package, in
an inverted position, to the substrate further comprises connecting
a bond wire between the substrate and the ball grid array package.
(FIG. 1) [0050] 3. Forming a lower package, the lower package
having the ball grid array package and the substrate encapsulated
by a molding compound, wherein solder balls of the ball grid array
package protrude from the molding compound of the lower package.
(FIG. 1) [0051] 4. Attaching a second integrated circuit package
over the lower package further comprises providing a signal path
through the lower package to a printed circuit board interface.
(FIG. 1)
[0052] It has been discovered that the present invention thus has
numerous aspects.
[0053] An aspect is that the present invention improves
manufacturing yields due to the use of Known Good Die in the
process. Another aspect is that the BGA interposer provides not
only the design flexibility for the base assembly package but also
the option of functional changes to the top module.
[0054] Yet another important aspect of the present invention is
that it valuably supports and services the historical trend of
reducing costs, simplifying systems, and increasing performance.
These and other valuable aspects of the present invention
consequently further the state of the technology to at least the
next level.
[0055] Thus, it has been discovered that the 3D package stacking
system method and apparatus of the present invention furnish
important and heretofore unknown and unavailable solutions,
capabilities, and functional aspects for 3D package optimization
and cost reduction. The resulting processes and configurations are
straightforward, cost-effective, uncomplicated, highly versatile
and effective, can be implemented by adapting known technologies,
and are thus readily suited for efficiently and economically
manufacturing 3D package devices fully compatible with conventional
manufacturing processes and technologies.
[0056] While the invention has been described in conjunction with a
specific best mode, it is to be understood that many alternatives,
modifications, and variations will be apparent to those skilled in
the art in light of the aforegoing description. Accordingly, it is
intended to embrace all such alternatives, modifications, and
variations which fall within the scope of the included claims. All
matters hithertofore set forth herein or shown in the accompanying
drawings are to be interpreted in an illustrative and non-limiting
sense.
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