U.S. patent application number 11/681457 was filed with the patent office on 2007-06-28 for printed circuit board including embedded capacitor having high dielectric constant and method of fabricating same.
This patent application is currently assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD.. Invention is credited to Jin-Yong Ahn, Suk-Hyeon Cho, Jong-Kuk Hong, Ho-Sik Jun, Seok-Kyu Lee, Chang-Sup Ryu.
Application Number | 20070146980 11/681457 |
Document ID | / |
Family ID | 36093886 |
Filed Date | 2007-06-28 |
United States Patent
Application |
20070146980 |
Kind Code |
A1 |
Ahn; Jin-Yong ; et
al. |
June 28, 2007 |
PRINTED CIRCUIT BOARD INCLUDING EMBEDDED CAPACITOR HAVING HIGH
DIELECTRIC CONSTANT AND METHOD OF FABRICATING SAME
Abstract
Disclosed is a PCB including embedded capacitors and a method of
fabricating the same. A dielectric layer is formed using a ceramic
material having a high capacitance, thereby assuring that the
capacitors each have a high dielectric constant corresponding to
the capacitance of a decoupling chip capacitor.
Inventors: |
Ahn; Jin-Yong; (Daejeon,
KR) ; Ryu; Chang-Sup; (Daejeon, KR) ; Cho;
Suk-Hyeon; (Daejeon, KR) ; Lee; Seok-Kyu;
(Chungcheongbuk-do, KR) ; Hong; Jong-Kuk;
(Chungcheongnam-do, KR) ; Jun; Ho-Sik;
(Chungcheongbuk-do, KR) |
Correspondence
Address: |
DARBY & DARBY P.C.
P. O. BOX 5257
NEW YORK
NY
10150-5257
US
|
Assignee: |
SAMSUNG ELECTRO-MECHANICS CO.,
LTD.
Gyeonggi-do
KR
|
Family ID: |
36093886 |
Appl. No.: |
11/681457 |
Filed: |
March 2, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10999442 |
Nov 29, 2004 |
|
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11681457 |
Mar 2, 2007 |
|
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Current U.S.
Class: |
361/762 ;
29/25.35; 438/106; 438/597 |
Current CPC
Class: |
H01G 4/1209 20130101;
H05K 2201/0195 20130101; H05K 2203/0568 20130101; Y10T 29/42
20150115; H05K 2201/0175 20130101; H05K 2201/09509 20130101; H01G
4/248 20130101; H05K 3/4652 20130101; H05K 2201/09881 20130101;
H01G 4/33 20130101; H05K 2201/0179 20130101; H05K 2203/1366
20130101; H05K 1/162 20130101; H01G 4/1218 20130101; H05K
2201/09763 20130101 |
Class at
Publication: |
361/681 ;
438/597; 438/106; 029/025.35 |
International
Class: |
H04R 17/00 20060101
H04R017/00 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 26, 2004 |
KR |
2004-67487 |
Claims
1. A printed circuit board including an embedded capacitor having a
high dielectric constant, comprising: a first insulating layer made
of an insulating material to electrically insulate upper and lower
parts from each other; a circuit layer made of a first conductive
material, which is laminated on one side of the first insulating
layer and in which circuit patterns including a plurality of lower
electrodes of the embedded capacitors are formed; a plurality of
second insulating layers laminated on the lower electrodes of the
circuit layer, and made of a ceramic material; a plurality of upper
electrodes laminated on the second insulating layers, and made of a
second conductive material; and a third insulating layer laminated
on the circuit layer and upper electrodes, and including through
holes for electrically connecting the upper electrodes to external
elements.
2. The printed circuit board as set forth in claim 1, further
comprising: a first adhesive metal layer made of a first adhesive
metal to improve interfacial adhesion between the circuit layer and
second insulating layers; and a second adhesive metal layer made of
a second adhesive metal to improve interfacial adhesion between the
second insulating layers and upper electrodes.
3. The printed circuit board as set forth in claim 1 or 2, wherein
each of the second insulating layers includes at least one selected
from the group consisting of SrTiO.sub.3, BaTiO.sub.3, (Ba,
Sr)TiO.sub.3, Pb(Zr, Ti)O.sub.3, (Pb, La)(Zr, Ti)O.sub.3,
Pb(Ti.sub.1/3Nb.sub.2/3)O.sub.3, Ta.sub.2O.sub.5, and
Al.sub.2O.sub.3.
4. A printed circuit board including an embedded capacitor having a
high dielectric constant, comprising: a first insulating layer made
of a first insulating material to electrically insulate upper and
lower parts from each other; a first circuit layer made of a first
conductive material, which is laminated on one side of the first
insulating layer, and in which first circuit patterns including a
plurality of lower electrodes of the embedded capacitors are formed
and a second insulating material is packed between the first
circuit patterns; a second insulating layer laminated on the first
circuit layer, and made of a ceramic material; a second circuit
layer made of a second conductive material, which is laminated on
the second insulating layer, and in which second circuit patterns,
including a plurality of upper electrodes corresponding to the
lower electrodes, are formed; and a third insulating layer
laminated on the second circuit layer, and including through holes
for electrically connecting the upper electrodes to external
elements.
5. The printed circuit board as set forth in claim 4, further
comprising: a first adhesive metal layer made of a first adhesive
metal between the lower electrodes of the first circuit layer and
second insulating layer, and provided to improve interfacial
adhesion therebetween; and a second adhesive metal layer made of a
second adhesive metal between the second insulating layer and upper
electrodes of the second circuit layer, and provided to improve
interfacial adhesion therebetween.
6. The printed circuit board as set forth in claim 4 or 5, wherein
the second insulating layer includes at least one selected from the
group consisting of SrTiO.sub.3, BaTiO.sub.3, (Ba, Sr)TiO.sub.3,
Pb(Zr, Ti)O.sub.3, (Pb, La)(Zr, Ti)O.sub.3,
Pb(Ti.sub.1/3Nb.sub.2/3)O.sub.3, Ta.sub.2O.sub.5, and
Al.sub.2O.sub.3.
7. A method of fabricating a printed circuit board including an
embedded capacitor having a high dielectric constant, comprising: a
first step of forming circuit patterns including a plurality of
lower electrodes of the embedded capacitors on a copper foil on one
side of a copper clad laminate; a second step of laminating a mask,
in which portions corresponding to the lower electrodes are opened,
on the copper clad laminate to form insulating layers of the
embedded capacitors, and spraying a ceramic dielectric through a
thermal spray process to form ceramic films; a third step of
forming upper electrodes on the ceramic films formed in the second
step and subsequently removing the mask; and a fourth step of
laminating the insulating layers on the copper clad laminate on
which the embedded capacitors are formed, and forming through holes
for electrically connecting the upper electrodes to external
elements.
8. The method as set forth in claim 7, further comprising a fifth
step of conducting a pretreatment to improve interfacial adhesion
after the first step.
9. The method as set forth in claim 7, wherein the spraying of the
ceramic dielectric through the thermal spray process in the second
step is conducted under conditions such that a distance between a
thermal spray gun and a mother material is 3-4 inches, a moving
speed of the thermal spray gun or mother material is 1-2 m/sec, an
air filter is used for a cleaning process, and a roughness is about
1/5 of a size of a nano-sized powder.
10. The method as set forth in claim 7, wherein a material of the
ceramic dielectric in the second step is at least one selected from
the group consisting of SrTiO.sub.3, BaTiO.sub.3, (Ba,
Sr)TiO.sub.3, Pb(Zr, Ti)O.sub.3, (Pb, La)(Zr, Ti)O.sub.3, Pb
(Ti.sub.1/3Nb.sub.2/3)O.sub.3, Ta.sub.2O.sub.5, and
Al.sub.2O.sub.3.
11. The method as set forth in claim 7, further comprising a sixth
step of conducting a pretreatment to improve interfacial adhesion
after the second step.
12. The method as set forth in claim 7, wherein the upper
electrodes are formed through the thermal spray process in the
third step.
13. The method as set forth in claim 7, wherein the upper
electrodes are formed through a copper plating process in the third
step.
14. The method as set forth in claim 7, further comprising a
seventh step of laminating the insulating layers to the same height
as the embedded capacitors after the third step.
15. A method of fabricating a printed circuit board including an
embedded capacitor having a high dielectric constant, comprising: a
first step of forming first circuit patterns including a plurality
of lower electrodes of the embedded capacitors on a copper foil on
one side of a copper clad laminate, and packing an insulating
material between the first circuit patterns; a second step of
spraying a ceramic dielectric on the copper clad laminate through a
thermal spray process to form ceramic films; a third step of
forming second circuit patterns including upper electrodes on a
portion of the ceramic films, which correspond to the lower
electrodes, formed in the second step; and a fourth step of
laminating insulating layers on the second circuit patterns formed
in the third step, and forming through holes for electrically
connecting the upper electrodes to external elements.
16. The method as set forth in claim 15, further comprising a fifth
step of conducting a pretreatment to improve interfacial adhesion
after the first step.
17. The method as set forth in claim 15, wherein the spraying of
the ceramic dielectric through the thermal spray process in the
second step is conducted under conditions such that a distance
between a thermal spray gun and a mother material is 3-4 inches, a
moving speed of the thermal spray gun or mother material is 1-2
.mu.m/sec, an air filter is used for a cleaning process, and a
roughness is about 1/5 of a size of a nano-sized powder.
18. The method as set forth in claim 15, wherein a material of the
ceramic dielectric in the second step is at least one selected from
the group consisting of SrTiO.sub.3, BaTiO.sub.3, (Ba,
Sr)TiO.sub.3, Pb(Zr, Ti)O.sub.3, (Pb, La)(Zr, Ti)O.sub.3,
Pb(Ti.sub.1/3Nb.sub.2/3)O.sub.3, Ta.sub.2O.sub.5, and
Al.sub.2O.sub.3.
19. The method as set forth in claim 15, further comprising a sixth
step of conducting a pretreatment to improve interfacial adhesion
after the second step.
Description
INCORPORATION BY REFERENCE
[0001] The present application claims priority under 35 U.S.C.
.sctn.119 to Korean Patent Application No. 2004-67487 filed on Aug.
26, 2004. The content of the application is incorporated herein by
reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates, in general, to a printed
circuit board (PCB) including embedded capacitors and a method of
fabricating the same and, more particularly, to a PCB including
embedded capacitors, in which a dielectric layer is formed using a
ceramic material having a high capacitance, thereby assuring that
the capacitors each have a high dielectric constant corresponding
to the capacitance of a decoupling chip capacitor, and a method of
fabricating the same.
[0004] 2. Description of the Prior Art
[0005] Typically, discrete chip resistors or discrete chip
capacitors have been frequently mounted on most printed circuit
boards (PCB), but, recently, PCBs are developing in which passive
components, such as resistors or capacitors, are embedded.
[0006] A technology for fabricating the PCBs including the passive
components embedded therein, achieves substitution of conventional
chip resistors or chip capacitors by mounting the passive
components, such as the resistors or capacitors, on an external
surface of a PCB or in an internal layer of the PCB according to a
novel process employing a novel material (substance). In other
words, the PCB including the passive component embedded therein has
a structure in which the passive component, for example, the
capacitor, is embedded in the internal layer of the PCB or mounted
on the external surface of the PCB, and if the capacitor as the
passive component is integrated with the PCB to act as one part of
the PCB regardless of the size of a substrate, the capacitor is
called an "embedded capacitor" and the resulting PCB is called "PCB
including embedded capacitor". One of the most important features
of the PCB including the capacitor embedded therein is that since
the capacitor is already mounted as part of the PCB in the PCB, it
is not necessary to mount the capacitor on a surface of the
PCB.
[0007] On the whole, the technology of fabricating a PCB including
a capacitor embedded therein may be classified into three methods,
and a description will be given of the three methods, below.
[0008] Firstly, there is a method of fabricating a polymer thick
film type of capacitor, in which application of a polymer capacitor
paste and thermal hardening, that is, drying, are conducted to
fabricate a capacitor. In the above method, after the polymer
capacitor paste is applied on an internal layer of a PCB and dried,
a copper paste is printed on the resulting PCB and dried so that
electrodes are formed, thereby making an embedded capacitor.
[0009] A second method is to apply a ceramic filled photosensitive
resin on a PCB to fabricate a discrete type of embedded capacitor,
and Motorola Inc. in USA holds a patent for related technologies.
In detail, the photosensitive resin containing ceramic powder is
applied on the PCB, a copper foil is laminated on the resulting PCB
to form upper and lower electrodes, a circuit pattern is formed,
and the photosensitive resin is etched to fabricate the discrete
type of capacitor.
[0010] A third method is to insert an additional dielectric layer
having a capacitance characteristic in an internal layer of a PCB
so as to substitute for a decoupling capacitor conventionally
mounted on a surface of a PCB, thereby fabricating a capacitor, and
Sanmina Corp. in USA holds a patent for related technologies.
According to the third method, the dielectric layer including a
power supply electrode and a grounded electrode is inserted into
the internal layer of the PCB to fabricate a power distribution
type of decoupling capacitor.
[0011] The above three methods have been achieved through various
processes, and each process is realized in a different manner.
However, a market for PCBs including embedded capacitors is not yet
activated. Accordingly, standardization of the above methods has
not been achieved yet, but commercialization of the methods is
under development.
[0012] Hereinafter, a detailed description will be given of a
conventional PCB including an embedded capacitor and a method of
fabricating the same, referring to the drawings.
[0013] Firstly, a conventional technology of FIGS. 1a to 1e will be
described, below.
[0014] FIGS. 1a to 1e illustrate the production of the conventional
PCB including the polymer thick film type of embedded capacitors. A
polymer capacitor paste is applied and heat-dried (or hardened) to
create the PCB including the polymer thick film type of embedded
capacitors.
[0015] In a first step, a dry film is applied on copper foils of an
internal layer 42, made of FR-4, of the PCB, exposed and developed,
and the resulting copper foils are etched to form copper foils 44a,
44b for a positive electrode (+), copper foils 43a, 43b for a
negative electrode (-), and clearances (refer to FIG. 1a).
[0016] In a second step, capacitor pastes 45a, 45b, which are made
of a polymer containing ceramic powder having a high dielectric
constant, are applied on the copper foils 43a, 43b for the negative
electrode (-) using a screen printing technology, and then dried or
hardened (refer to FIG. 1b). In this regard, the screen printing
technology is a method of passing a medium, such as an ink, through
a stencil screen using a squeeze to transcribe a pattern to the
surface of a substrate.
[0017] At this time, the capacitor pastes 45a, 45b are packed into
the clearances between the copper foils 44a, 44b for the positive
electrode (+) and the copper foils 43a, 43b for the negative
electrode (-).
[0018] In a third step, positive electrodes (+) 46a, 46b are formed
using a conductive paste, such as silver or copper, according to a
screen printing technology, dried and hardened (refer to FIG.
1c).
[0019] In a fourth step, capacitor layers formed on the internal
layer 42 of the PCB according to the first to third steps are
interposed between insulating layers 47a, 47b, and subjected to a
lamination process (refer to FIG. 1d).
[0020] In a fifth step, capacitors on the internal layer of the PCB
are connected to positive terminals (+) 51a, 51b and negative
terminals (-) 50a, 50b of integrated circuit chips (IC chip) 52a,
52b, mounted on an external side of the substrate, through THs
(through holes) and LBVHs (laser blind via holes) 49a, 49b, thereby
acting as the embedded capacitors (refer to FIG. 1e).
[0021] A description will be given of a conventional second
technology, referring to FIGS. 2a to 2f.
[0022] FIGS. 2a to 2f illustrate the production of a conventional
PCB including a discrete type of embedded capacitors which are
formed by application of a photosensitive resin. The discrete type
of embedded capacitors are formed by applying a ceramic filled
photosensitive resin on the PCB as disclosed in U.S. Pat. No.
6,349,456 which is granted to Motorola Inc.
[0023] In a first step, a photosensitive dielectric resin 14
containing ceramic powder is applied on a PCB 10, on which a
conductive layer 12 is already formed, exposed and heat-dried
(refer to FIG. 2a).
[0024] In a second step, a copper foil 16 is laminated on the dried
photosensitive dielectric resin 14 (refer to FIG. 2b). In this
respect, reference numeral 18 denotes a sacrificial layer which is
formed by plating tin on an upper side of the copper foil 16 to be
used as a copper etching resist.
[0025] In a third step, the dry film is laminated on an upper side
of the sacrificial layer 18, exposed and developed to etch a
portion of the sacrificial layer 18 and the copper foil 16, thereby
forming upper electrodes 20 (refer to FIG. 2c).
[0026] In a fourth step, the photosensitive dielectric resin 14
positioned below the upper electrodes 20 is exposed and then
etched. At this time, the upper copper electrodes 20 are used as a
photomask of the photosensitive dielectric resin 14 (refer to FIG.
2d).
[0027] In a fifth step, the conductive layer 12 below the etched
photosensitive dielectric resin 22 is etched to form lower
electrodes 24 (refer to FIG. 2e).
[0028] In a sixth step, capacitor layers 32 of an internal layer of
the PCB 10 formed through the first to fifth steps are interposed
between insulating layers 26, and metal layers 30 are laminated on
the resulting structure (refer to FIG. 2f).
[0029] Capacitors 32 in an internal layer of the PCB are connected
to power supply terminals and grounded terminals of integrated
circuit chips, mounted on an external side of the PCB through THs
(through holes) and LBVHs (laser blind via holes), thereby creating
the PCB including the discrete type of embedded capacitors.
[0030] A third conventional technology will be described, referring
to FIGS. 3a to 3c.
[0031] FIGS. 3a to 3c illustrate the production of a conventional
PCB including embedded capacitors which are formed by insertion of
an additional dielectric layer having a capacitance characteristic.
The additional dielectric layer having the capacitance
characteristic is inserted into an internal layer of the PCB to
create an embedded capacitor as a substitute of a decoupling
capacitor mounted on a surface of the PCB as disclosed in U.S. Pat.
Nos. 5,079,069, 5,261,153, and 5,800,575 which are granted to
Sanmina Corp in the USA.
[0032] In a first step, a copper coated laminate 61, which has a
high dielectric constant and is interposed between copper foils
63a, 63b, is coated with a dry film, exposed and developed to etch
the copper foils 63a, 63b, thereby forming power supply electrodes
of capacitors and clearances (refer to FIG. 3a).
[0033] In a second step, an internal layer 61 of the PCB subjected
to the first step is interposed between insulating layers 64a, 64b
and subjected to a lamination process, and external copper foils
65a, 65b are laminated on the resulting PCB (refer to FIG. 3b).
[0034] In a third step, the capacitors in the internal layer of the
PCB are connected to power supply terminals and grounded terminals
of integrated circuit chips 68a, 68b, mounted on an external side
of the PCB, through THs (through holes) and LBVHs (laser blind via
holes), thereby acting as a power distribution type of decoupling
capacitor (refer to FIG. 3c). In this regard, reference numerals
67a, 67b denote clearances between the grounded and power supply
electrodes. The clearances each have a predetermined width so that
the copper foils do not meet with the through holes or the via
holes when the through holes or the via holes are formed through
the PCB.
[0035] Meanwhile, since the embedded capacitors have a structure in
which the capacitors are embedded in the PCB, an area which is
occupied by the chip capacitors may be reduced. Thus, the embedded
capacitors are advantageous in that a mounting density of chips may
increase and it is unnecessary to mount the chip capacitors on a
surface of the PCB.
[0036] In conventional technologies, a long connection length
between devices at a high frequency brings about occurrence of an
electric parasitic load, thereby reducing the electric performances
of goods. Additionally, the number of connections increases due to
a solder, causing poor reliability of goods. However, a
conventional embedded capacitor is advantageous in that the
connection length between the devices is reduced, resulting in
suppressed occurrence of the electric parasitic element. Thus, the
electric performance is improved.
[0037] However, a material of the conventional embedded capacitor
is, for example, a polymer or a photosensitive resin filled with
ceramic. Thus, it is usefully applied to a PCB process, but has a
dielectric constant too low to be used as a substitute for a chip
capacitor.
[0038] Generally, capacitance depends on the area and thickness of
a capacitor, and is calculated according to the following Equation
1. C = r .times. 0 ( A D ) Equation .times. .times. 1 ##EQU1##
[0039] Wherein, .di-elect cons..sub.r is the dielectric constant of
a dielectric, .di-elect cons..sub.0 is a constant having a value of
8.855.times.10.sup.-8, A is the surface area of the dielectric, and
D is the thickness of the dielectric. The dielectric constant of
the dielectric must be high in order to assure a capacitor having a
high capacitance, and a smaller thickness and a larger surface area
of the dielectric bring about higher capacitance of the
capacitor.
[0040] A conventional bimodal polymer ceramic complex has a
capacitance of 5-7 nF/cm.sup.2 if the thickness is 10 .mu.m.
[0041] For example, U.S. Pat. No. 6,274,224 granted to 3M Co.
employs a thin film type composite having a thickness of 8-10 .mu.m
which includes BaTiO.sub.3 ceramic powder and a thermosetting
plastic epoxy or polyimide mixed with each other between copper
foils used as power supply and grounded electrodes. At this time,
capacitance per unit area is 10 nF/in.sup.2.
[0042] Furthermore, in the third conventional technology,
capacitance is low due to a low dielectric constant of an embedded
capacitor layer. For instance, in a thin film type capacitor having
a thickness of 10-50 .mu.m as shown in FIG. 3a, a material employed
by Sanmina Corp. is made of an FR-4 dielectric substance having a
thickness of 25 .mu.m or 50 .mu.m between copper foils used as
power supply and grounded electrodes. At this time, since the
dielectric constant of FR-4 is 4-5, the capacitance per unit area
is 0.5-1 nF/in.sup.2 in practice.
[0043] As described above, the capacitance per unit area of the
conventional embedded capacitor is 0.5-1 nF/in.sup.2 or 10
nF/in.sup.2, which is significantly lower than that of a
traditional decoupling discrete chip capacitor, that is, 100
nF/in.sup.2. Accordingly, there are many limits to the realization
of the conventional embedded capacitor.
[0044] Furthermore, in the conventional technologies, a dielectric
layer is laminated on a whole side of a substrate and electrodes
are formed during a circuit forming process, or patterning is
conducted using a photosensitive insulating layer through an
exposure process. However, these procedures result in increased
production costs because the formation of upper and lower
electrodes, and exposure and etching processes for patterning the
insulating layer are additionally carried out.
SUMMARY OF THE INVENTION
[0045] Therefore, the present invention has been made keeping in
mind the above disadvantages occurring in the prior arts, and an
object of the present invention is to provide a PCB including
embedded capacitors, in which a dielectric layer is formed using a
ceramic material having a high capacitance, thereby providing
capacitors each having a high dielectric constant corresponding to
the capacitance of a decoupling chip capacitor, and a method of
fabricating the same.
[0046] Another object of the present invention is to provide a PCB
including embedded capacitors each having a high dielectric
constant and a method of fabricating the same, in which only a
desired part is made of a ceramic material to form a dielectric
thin film (or thick film), thereby creating the embedded
capacitors. Accordingly, a loss of costly raw materials is reduced
and unnecessary processes, such as a process of etching a
dielectric, may be omitted, consequently, material costs are
reduced and ease of production is assured.
[0047] The above objects can be accomplished by providing a PCB
including embedded capacitors each having a high dielectric
constant, which comprises a first insulating layer made of an
insulating material to electrically insulate upper and lower parts
from each other. The PCB also comprises a circuit layer made of a
first conductive material, which is laminated on one side of the
first insulating layer and in which circuit patterns including a
plurality of lower electrodes of the embedded capacitors are
formed. A plurality of second insulating layers are laminated on
the lower electrodes of the circuit layer, and made of a ceramic
material. A plurality of upper electrodes are laminated on the
second insulating layers, and made of a second conductive material.
A third insulating layer is laminated on the circuit layer and
upper electrodes, and includes through holes for electrically
connecting the upper electrodes to external elements.
[0048] Furthermore, the present invention provides a PCB including
embedded capacitors each having a high dielectric constant, which
comprises a first insulating layer made of a first insulating
material to electrically insulate upper and lower parts from each
other. The PCB also comprises a first circuit layer made of a first
conductive material, which is laminated on one side of the first
insulating layer, and in which first circuit patterns including a
plurality of lower electrodes of the embedded capacitors are formed
and a second insulating material is packed between the first
circuit patterns. A second insulating layer is laminated on the
first circuit layer, and made of a ceramic material. A second
circuit layer made of a second conductive material is laminated on
the second insulating layer. At this time, second circuit patterns,
including a plurality of upper electrodes corresponding to the
lower electrodes, are formed on the second circuit layer. A third
insulating layer is laminated on the second circuit layer, and
includes through holes for electrically connecting the upper
electrodes to external elements.
[0049] Furthermore, the present invention provides a method of
fabricating a PCB including embedded capacitors each having a high
dielectric constant, which comprises a first step of forming
circuit patterns including a plurality of lower electrodes of the
embedded capacitors on a copper foil on one side of a copper clad
laminate; a second step of laminating a mask, in which portions
corresponding to the lower electrodes are opened, on the copper
clad laminate to form insulating layers of the embedded capacitors,
and spraying a ceramic dielectric through a thermal spray process
to form ceramic films; a third step of forming upper electrodes on
the ceramic films formed in the second step and subsequently
removing the mask; and a fourth step of laminating the insulating
layers on the copper clad laminate, on which the embedded
capacitors are formed, and forming through holes for electrically
connecting the upper electrodes to external elements.
[0050] Additionally, the present invention provides a method of
fabricating a PCB including embedded capacitors each having a high
dielectric constant, which comprises a first step of forming first
circuit patterns including a plurality of lower electrodes of the
embedded capacitors on a copper foil on one side of a copper clad
laminate, and packing an insulating material between the first
circuit patterns; a second step of spraying a ceramic dielectric on
the copper clad laminate through a thermal spray process to form
ceramic films; a third step of forming second circuit patterns
including upper electrodes on a portion of the ceramic films, which
correspond to the lower electrodes, formed in the second step; and
a fourth step of laminating insulating layers on the second circuit
patterns formed in the third step, and forming through holes for
electrically connecting the upper electrodes to external
elements.
BRIEF DESCRIPTION OF THE DRAWINGS
[0051] The above and other objects, features and other advantages
of the present invention will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0052] FIGS. 1a to 1e illustrate the production of a conventional
PCB including the polymer thick film type of embedded
capacitors;
[0053] FIGS. 2a to 2f illustrate the production of a conventional
PCB including the discrete type of embedded capacitors which are
formed by application of a photosensitive resin;
[0054] FIGS. 3a to 3c illustrate the production of a conventional
PCB including embedded capacitors, which are formed by insertion of
an additional dielectric layer having a capacitance
characteristic;
[0055] FIGS. 4a and 4b are sectional views of PCBs including
embedded capacitors having high dielectric constants according to
the first and second embodiments of the present invention,
respectively;
[0056] FIGS. 5a to 5e illustrate the production of a PCB including
embedded capacitors each having a high dielectric constant
according to the first embodiment of the present invention;
[0057] FIGS. 6a and 6b illustrate a thermal spray process adopted
in the present invention;
[0058] FIGS. 7a to 7f illustrate the production of a PCB including
embedded capacitors each having a high dielectric constant
according to the second embodiment of the present invention;
and
[0059] FIGS. 8a to 8f illustrate the production of a PCB including
embedded capacitors each having a high dielectric constant
according to the third embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0060] Hereinafter, a description will be given of a PCB including
embedded capacitors each having a high dielectric constant and a
method of fabricating the same according to the present invention,
referring to the drawings.
[0061] FIG. 4a is a sectional view of a PCB including embedded
capacitors each having a high dielectric constant according to the
first embodiment of the present invention.
[0062] Referring to FIG. 4a, circuit layers 112a, 112b including
patterned copper foils are formed on both sides of an insulating
layer 111 constituting a core layer 110.
[0063] At this time, lower electrodes 121a, 121b, 121c, 121d of the
embedded capacitors 120a, 120b, 120c, 120d are formed in the
circuit layers 112a, 112b.
[0064] The embedded capacitors 120a, 120b, 120c, 120d include the
lower electrodes 121a, 121b, 121c, 121d formed in the circuit
layers 112a, 112b, insulating layers 122a, 122b, 122c, 122d made of
ceramic materials and laminated on the lower electrodes 121a, 121b,
121c, 121d, and upper electrodes 123a, 123b, 123c, 123d laminated
on the insulating layers 122a, 122b, 122c, 122d.
[0065] The embedded capacitors 120a, 120b, 120c, 120d may also
include an adhesive metal layer, which consists of an adhesive
metal such as Cr, Pt, or Ta, between the lower electrodes 121a,
121b, 121c, 121d, formed in the circuit layers 112a, 112b, and the
insulating layers 122a, 122b, 122c, 122d so as to increase
interfacial adhesion between the lower electrodes and the
insulating layers. Furthermore, the embedded capacitors 120a, 120b,
120c, 120d may also include an adhesive metal layer, which consists
of an adhesive metal such as Cr, Pt, Ta, between the insulating
layers 122a, 122b, 122c, 122d and the upper electrodes 123a, 123b,
123c, 123d so as to increase interfacial adhesion between the
insulating layers and the upper electrodes.
[0066] Insulating layers 131a, 131b are formed on the circuit
layers 112a, 112b and the embedded capacitors 120a, 120b, 120c,
120d, and blind via holes 134a, 134b, 134c, 134d, for providing
electrical connection between the upper electrodes 123a, 123b,
123c, 123d and external elements, are formed through the insulating
layers 131a, 131b.
[0067] Resins 133a, 133b, 133c, 133d are packed into the blind via
holes 134a, 134b, 134c, 134d, and nickel-gold plating layers 136a,
136b, 136c, 136d and photoresists 135a, 135b are formed outside the
blind via holes 134a, 134b, 134c, 134d.
[0068] FIG. 4b is a sectional view of a PCB including embedded
capacitors each having a high dielectric constant according to the
second embodiment of the present invention.
[0069] Referring to FIG. 4b, circuit layers 112a, 112b including
patterned copper foils are formed on both sides of an insulating
layer 111 constituting a core layer 110. Insulators 113a, 113b such
as resins are packed into a portion of the circuit layers 112a,
112b on which circuit patterns are not formed.
[0070] At this time, lower electrodes 121a, 121b, 121c, 121d of the
embedded capacitors 120a, 120b, 120c, 120d are formed in the
circuit layers 112a, 112b.
[0071] Insulating layers 122a, 122b made of ceramic materials are
laminated on the circuit layers 112a, 112b.
[0072] Circuit layers 125a, 125b on which circuit patterns are
formed are formed on the insulating layers 122a, 122b, and upper
electrodes 123a, 123b, 123c, 123d that correspond to the lower
electrodes 121a, 121b, 121c, 121d are formed on the circuit layers
125a, 125b.
[0073] Embedded capacitors 120a, 120b, 120c, 120d comprise the
lower electrodes 121a, 121b, 121c, 121d formed in the circuit
layers 112a, 112b, the insulating layers 122a, 122b made of ceramic
materials and laminated on the circuit layers 112a, 112b, and the
upper electrodes 123a, 123b, 123c, 123d formed in the circuit
layers 125a, 125b laminated on the insulating layers 122a, 122b.
Additionally, the embedded capacitors may also include an adhesive
metal layer consisting of an adhesive metal between the lower
electrodes and insulating layers, and between the insulating layers
and upper electrodes so as to increase interfacial adhesion between
the lower electrodes and insulating layers, and between the
insulating layers and upper electrodes.
[0074] Insulating layers 131a, 131b are formed on the circuit
layers 112a, 112b and embedded capacitors 120a, 120b, 120c, 120d,
and blind via holes 134a, 134b, 134c, 134d, for providing
electrical connection between the upper electrodes 123a, 123b,
123c, 123d and external elements, are formed through the insulating
layers 131a, 131b.
[0075] Resins 133a, 133b, 133c, 133d are packed into the blind via
holes 134a, 134b, 134c, 134d, and nickel-gold plating layers 136a,
136b, 136c, 136d and photoresists 135a, 135b are formed outside the
blind via holes 134a, 134b, 134c, 134d.
[0076] FIGS. 5a to 5e illustrate the production of a PCB including
embedded capacitors each having a high dielectric constant
according to the first embodiment of the present invention.
[0077] As shown in FIG. 5a, a copper clad laminate 210, which
includes an insulating layer 211 and copper foils 212a, 212b formed
on both sides of the insulating layer 211, is provided to fabricate
a PCB including embedded capacitors each having a high dielectric
constant according to the first embodiment of the present
invention.
[0078] The insulating layer 211 of the copper clad laminate 210 is
made of a resin. Even though the resin has excellent electrical
properties, it has poor mechanical strength and its dimensional
variation depending on temperature is undesirably ten times as
great as metal. To avoid the disadvantages, papers, glass fibers,
glass non-woven fabrics and the like are used as a reinforcing
material. Use of the reinforcing material serves to increase
longitudinal and transversal strengths of the resin and to reduce
the dimensional variation depending on the temperature.
[0079] Generally, an electrolytic copper foil is used for the
copper foils 212a, 212b. The copper foils 212a, 212b are formed in
such a way that the copper foils 212a, 212b chemically react with
the resin to partially penetrate into the resin in order to
increase interfacial adhesion to the resin.
[0080] As shown in FIG. 5b, a wiring pattern is formed on the
copper foils 212a, 212b according to a photolithography process. At
this time, lower electrodes 221a-221d of embedded capacitors
220a-220d are formed simultaneously.
[0081] The photolithography process is conducted in the order of
lamination for application of a photosensitive material, exposure,
and development. The photolithography process may be classified
into a photograph process and a screen printing process.
[0082] The wiring pattern is transferred onto the copper foils
212a, 212b using a photosensitizer such as D/F according to the
photolithography process, and the copper foils 212a, 212b are
patterned using the wiring pattern employing the photosensitizer as
an etching resist. In other words, the photolithography process is
conducted to form the pattern of the etching resist employing the
photosensitizer on a substrate, and an etchant is sprayed on the
resulting substrate to remove the copper foils other than a portion
of the copper foils which is protected by the etching resist (i.e.
a portion which forms the wiring pattern). The used etching resist
is then stripped, thereby creating the patterned copper foils 212a,
212b.
[0083] As shown in FIG. 5c, capacitor patterning masks 215a, 215b
are laminated on both sides of the copper clad laminate 210 (it is
possible to conduct the lamination on one side as well as on both
sides) to pattern the capacitors 220a-220d. At this time, the
capacitor patterning masks 215a, 215b may be made of metals,
glasses, plastics or the like.
[0084] Additionally, dielectric ceramic powder is melted and
sprayed onto the capacitor patterning masks 215a, 215b through a
thermal spray process to form dielectric thin films (or thick
films) 222a-222d of the embedded capacitors 220a-220d.
[0085] The thermal spray process is a process which includes
melting nano-sized spraying material powder using a high
temperature heat source, and subsequently spraying the molten
powder onto a mother material in a high speed to form a thin film
on the mother material.
[0086] FIGS. 6a and 6b illustrate the thermal spray process adopted
in the present invention.
[0087] With reference to FIG. 6a, molten nano-sized powder is
sprayed using a thermal spray gun 310 to a mother material 320, in
which capacitor patterning masks 322a, 322b are applied on a copper
clad laminate 321, to form a thin film.
[0088] At this time, cleaning, blasting, and bond coating processes
are conducted as a pretreatment process. In this regard, an
adhesive metal such as Cr, Pt, or Ta may be used as a raw material
in the bond coating process.
[0089] Furthermore, the spray process is conducted using the
thermal spray gun 310. At this time, a distance between the gun 310
and mother material 320, and a moving speed of the gun or mother
material are controlled in the spray process so as to adjust a
thickness of the film. Particularly, the distance between the
nozzle of the gun 310 and the mother material 320 is very important
during the spray process, and depends on the type of device, the
level of power, the type of spraying material, and the like.
[0090] As well, interfacial adhesion between the mother material
320 and dielectric thin film depends on the cleaning process,
roughness, and chemical affinity between a surface of the mother
material 320 and fused thin film.
[0091] For example, it is preferable that the distance between the
gun 310 and mother material 320 be 3-4 inches, the moving speed of
the gun 310 or mother material 320 be 1-2 m/sec, an air filter be
used for the cleaning process, and the roughness be about 1/5 of a
size of the nano-sized powder.
[0092] A description will be given of transformation of the
nano-sized powder (ceramic powder having a high dielectric constant
in the present invention) caused by the spraying of molten
nano-sized powder onto the mother material 320 using the thermal
spray gun 310, referring to FIG. 6b.
[0093] Dielectric particles from a few nm to a few .mu.m (ceramic
powder) are melted in the thermal spray gun 310, and then sprayed
onto the mother material 320 at high temperature and pressure.
[0094] The molten dielectric particles adhere to the mother
material 320, and are exposed to room temperature, resulting in
sintered crystalline dielectric thin films 222a-222d.
[0095] At this time, examples of material for the dielectric
ceramic powder include SrTiO.sub.3, BaTiO.sub.3, (Ba, Sr)TiO.sub.3,
Pb(Zr, Ti)O.sub.3, (Pb, La) (Zr, Ti)O.sub.3,
Pb(Ti.sub.1/3Nb.sub.2/3)O.sub.3, Ta.sub.2O.sub.5, and
Al.sub.2O.sub.3.
[0096] Meanwhile, after the dielectric thin films 222a-222d are
formed on the lower electrodes 221a-221d according to the thermal
spray process, upper electrodes 223a-223d are formed according to
the thermal spray process.
[0097] At this time, the cleaning, blasting, and bond coating
processes are conducted as a pretreatment process so as to improve
an interfacial adhesion between the dielectric thin films 222a-222d
and upper electrodes 223a-223d. In this regard, an adhesive metal
such as Cr, Pt, and Ta may be used as a raw material in the bond
coating process.
[0098] At this time, the upper electrodes 223a-223d may be formed
through electroless and electrolytic copper plating processes
instead of the thermal spray process.
[0099] An electroless plating process is the only plating process
that provides conductivity to the surface of an insulator such as
resins, ceramics, and glasses.
[0100] Since the electroless copper plating process is a process of
plating an insulator, it is difficult to expect a reaction caused
by ions with electricity. The electroless copper plating process is
achieved by a deposition reaction, and the deposition reaction is
promoted by a catalyst.
[0101] After the electroless copper plating process is conducted to
provide the conductivity, the electrolytic copper plating process
is carried out using electrolysis. The electrolytic copper plating
process is advantageous in that it is easy to form a thick plating
film and physical properties of an electrolytic copper-plating
layer are superior to those of an electroless copper-plating
layer.
[0102] Referring to FIG. 5d, after the embedded capacitors
220a-220d are formed on the copper clad laminate 210, the masks
215a, 215b are removed.
[0103] Furthermore, RCCs 230a, 230b, in which copper foils 232a,
232b are each formed on one side of each insulating layer 231a,
231b, are laminated on both sides of the resulting copper clad
laminate.
[0104] Referring to FIG. 5e, via holes 233a-233d and copper plating
layers 234a-234d are formed to provide conductivity to the upper
electrodes 223a-223d.
[0105] Additionally, circuit patterns are formed on the copper
foils 232a, 232b, solder resists 235a, 235b are formed, and
nickel-gold plating layers 236a-236d are formed to increase the
conductivity of the via holes 233a-233d.
[0106] FIGS. 7a to 7f illustrate the production of a PCB including
embedded capacitors each having a high dielectric constant
according to the second embodiment of the present invention.
[0107] As shown in FIG. 7a, a copper clad laminate 410, which
includes an insulating layer 411 and copper foils 412a, 412b formed
on both sides of the insulating layer 411, is provided to fabricate
the PCB including embedded capacitors each having a high dielectric
constant according to the second embodiment of the present
invention.
[0108] As shown in FIG. 7b, a wiring pattern is formed on the
copper foils 412a, 412b according to a photolithography process. At
this time, lower electrodes 421a-421d of embedded capacitors
420a-420d are formed simultaneously.
[0109] As shown in FIG. 7c, capacitor patterning masks 415a, 415b
are laminated on both sides of the copper clad laminate 410 (it is
possible to conduct the lamination on one side as well as on both
sides) to pattern the capacitors 420a-420d. At this time, the
capacitor patterning masks 415a, 415b may be made of metals,
glasses, plastics or the like.
[0110] Additionally, dielectric ceramic powder is melted and
sprayed onto the capacitor patterning masks 415a, 415b through a
thermal spray process to form dielectric thin films (or thick
films) 422a-422d of the embedded capacitors 420a-420d.
[0111] At this time, cleaning, blasting, and bond coating processes
are conducted as pretreatment processes. In this regard, an
adhesive metal such as Cr, Pt, and Ta may be used as a raw material
in the bond coating process.
[0112] Furthermore, examples of material for the dielectric ceramic
powder include SrTiO.sub.3, BaTiO.sub.3, (Ba, Sr)TiO.sub.3, Pb(Zr,
Ti)O.sub.3, (Pb, La) (Zr, Ti)O.sub.3,
Pb(Ti.sub.1/3Nb.sub.2/3)O.sub.3, Ta.sub.2O.sub.5, and
Al.sub.2O.sub.3.
[0113] Meanwhile, after the dielectric thin films 422a-422d are
formed on the lower electrodes 421a-421d by the thermal spray
process, upper electrodes 423a-423d are formed according to the
thermal spray process.
[0114] At this time, the cleaning, blasting, and bond coating
processes are conducted as a pretreatment process so as to improve
an interfacial adhesion between the dielectric thin films 422a-422d
and upper electrodes 423a-423d. In this regard, an adhesive metal
such as Cr, Pt, or Ta may be used as a raw material in the bond
coating process.
[0115] At this time, the upper electrodes 423a-423d may be formed
through electroless and electrolytic copper plating processes
instead of the thermal spray process.
[0116] Referring to FIG. 7d, after the embedded capacitors
420a-420d are formed on the copper clad laminate 410, the masks
415a, 415b are removed.
[0117] Furthermore, resins 425a, 425b are uniformly applied on the
copper clad laminate using a vacuum printing process unlike the
first embodiment. This functions to prevent some problems that
occur in the first embodiment, that is to say, generation of cracks
caused by a bias of forces applied to the embedded capacitors
420a-420d due to a stress partially occurring in the lamination of
the RCCs, or generation of pore defects or voids caused by the
lamination of the B-stage RCCs disturbing the packing of the resin
into edge portions of corners of the embedded capacitors
420a-420d.
[0118] Referring to FIG. 7e, RCCs 430a, 430b, in which copper foils
432a, 432b are each formed on one side of each insulating layer
431a, 431b, are laminated on both sides of the resulting copper
clad laminate.
[0119] Referring to FIG. 7f, via holes 433a-433d and copper plating
layers 434a-434d are formed to provide conductivity to the upper
electrodes 423a-423d.
[0120] Additionally, circuit patterns are formed on the copper
foils 432a, 432b, solder resists 435a, 435b are formed, and
nickel-gold plating layers 436a-436d are formed to increase the
conductivity of the via holes 433a-433d.
[0121] FIGS. 8a to 8f illustrate the production of a PCB including
embedded capacitors each having a high dielectric constant
according to the third embodiment of the present invention.
[0122] As shown in FIG. 8a, a copper clad laminate 510, which
includes an insulating layer 511 and copper foils 512a, 512b formed
on both sides of the insulating layer 511, is provided to fabricate
a PCB including embedded capacitors each having a high dielectric
constant according to the third embodiment of the present
invention.
[0123] As shown in FIG. 8b, a wiring pattern is formed on the
copper foils 512a, 512b according to a photolithography process. At
this time, lower electrodes 521a-521d of embedded capacitors
520a-520d are formed simultaneously.
[0124] As shown in FIG. 8c, resins 515a, 515b are formed on the
copper clad laminate 510, on which circuits are formed, according
to a vacuum printing process. Flattening the resins 515a, 515b
increases their interfacial adhesion to a ceramic material.
[0125] Referring to FIG. 8d, dielectric ceramic powder is melted
and sprayed onto the copper clad laminate 510 as a mother material
through a thermal spray process without using a mask to form
dielectric thin films (or thick films) 522a, 522b of the embedded
capacitors 520a-520d, unlike the first and second embodiments of
the present invention.
[0126] At this time, cleaning, blasting, and bond coating processes
are conducted as pretreatment processes. In this regard, an
adhesive metal such as Cr, Pt, or Ta may be used as a raw material
in the bond coating process.
[0127] Furthermore, examples of material for the dielectric ceramic
powder include SrTiO.sub.3, BaTiO.sub.3, (Ba, Sr)TiO.sub.3, Pb(Zr,
Ti)O.sub.3, (Pb, La) (Zr, Ti)O.sub.3,
Pb(Ti.sub.1/3Nb.sub.2/3)O.sub.3, Ta.sub.2O.sub.5, and
Al.sub.2O.sub.3.
[0128] Meanwhile, after the dielectric thin films 522a, 522b are
formed on the lower electrodes 521a-521d according to the thermal
spray process, circuit layers 525a, 525b are formed using the
thermal spray process and then patterned to form upper electrodes
523a-523d.
[0129] At this time, the cleaning, blasting, and bond coating
processes are conducted as a pretreatment process so as to improve
interfacial adhesion between the dielectric thin films 522a, 522b
and upper electrodes 523a-523d. In this regard, an adhesive metal
such as Cr, Pt, and Ta may be used as a raw material in the bond
coating process.
[0130] At this time, the upper electrodes 523a-523d may be formed
through electroless and electrolytic copper plating processes
instead of the thermal spray process.
[0131] Referring to FIG. 8f, RCCs 530a, 530b, in which copper foils
532a, 532b are each formed on one side of each insulating layer
531a, 531b, are laminated on both sides of the resulting copper
clad laminate.
[0132] Furthermore, via holes 533a-533d and copper plating layers
534a-534d are formed to provide conductivity to the upper
electrodes 523a-523d.
[0133] Additionally, circuit patterns are formed on the copper
foils 532a, 532b, solder resists 535a, 535b are formed, and
nickel-gold plating layers 536a-536d are formed to increase the
conductivity of the via holes 533a-533d.
[0134] As described above, the present invention provides a PCB
including embedded capacitors and a method of fabricating the same,
in which a paste is packed only in a desired part to create the
embedded capacitors. Accordingly, a loss of costly raw materials is
reduced and unnecessary processes, such as an etching process of a
dielectric, may be omitted, and thus, material costs are reduced
and ease of production is assured.
[0135] Furthermore, the present invention provides a PCB including
embedded capacitors and a method of fabricating the same, in which
precise capacitances of capacitors having a consistent height and
area are assured by use of via holes formed through a FR-4 copper
clad laminate.
[0136] Additionally, the present invention provides a PCB including
embedded capacitors and a method of fabricating the same, in which
the circuits and embedded capacitors can be simultaneously formed
in a commonly used PCB layer without the use of additional PCB
layers for forming capacitors.
* * * * *