U.S. patent application number 11/358715 was filed with the patent office on 2007-05-31 for method of manufacturing semiconductor device.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Shunn-ichi Fukuyama, Yoshiyuki Ohkura, Tamotsu Owada, Ken Sugimoto, Hirofumi Watatani.
Application Number | 20070123035 11/358715 |
Document ID | / |
Family ID | 38088084 |
Filed Date | 2007-05-31 |
United States Patent
Application |
20070123035 |
Kind Code |
A1 |
Sugimoto; Ken ; et
al. |
May 31, 2007 |
Method of manufacturing semiconductor device
Abstract
A method of manufacturing a semiconductor device comprising a
wiring structure that includes a vertical wiring section is
disclosed. The method comprises a step of forming an interlayer
insulation film made of a low dielectric constant material on a
wiring layer, a step of forming a silicon oxide film by CVD using
SiH.sub.4 gas and CO.sub.2 gas on the interlayer insulation film, a
step of forming a chemically amplified resist film to cover the
silicon oxide film, and a step of forming a first opening in a
position on the chemically amplified resist film where the vertical
wiring section is to be formed.
Inventors: |
Sugimoto; Ken; (Kawasaki,
JP) ; Ohkura; Yoshiyuki; (Kawasaki, JP) ;
Watatani; Hirofumi; (Kawasaki, JP) ; Owada;
Tamotsu; (Kawasaki, JP) ; Fukuyama; Shunn-ichi;
(Kawasaki, JP) |
Correspondence
Address: |
WESTERMAN, HATTORI, DANIELS & ADRIAN, LLP
1250 CONNECTICUT AVENUE, NW
SUITE 700
WASHINGTON
DC
20036
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki
JP
|
Family ID: |
38088084 |
Appl. No.: |
11/358715 |
Filed: |
February 22, 2006 |
Current U.S.
Class: |
438/636 ;
438/638; 438/675; 438/787 |
Current CPC
Class: |
H01L 21/76808 20130101;
H01L 21/76829 20130101 |
Class at
Publication: |
438/636 ;
438/787; 438/675; 438/638 |
International
Class: |
H01L 21/4763 20060101
H01L021/4763; H01L 21/473 20060101 H01L021/473 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 29, 2005 |
JP |
2005-344263 |
Claims
1. A method of manufacturing a semiconductor device comprising a
wiring structure that includes a vertical wiring section,
comprising: forming an interlayer insulation film made of a low
dielectric constant material over a wiring layer; forming a silicon
oxide film by CVD using SiH.sub.4 gas and CO.sub.2 gas over the
interlayer insulation film; forming a chemically amplified resist
film to cover the silicon oxide film; and forming a first opening
in a position over the chemically amplified resist film where the
vertical wiring section is to be formed.
2. A method of manufacturing a semiconductor device comprising a
wiring structure that includes a vertical wiring section,
comprising: forming an interlayer insulation film made of a low
dielectric constant material over a wiring layer; forming a silicon
oxide film by CVD using SiH.sub.4 gas and CO.sub.2 gas over the
interlayer insulation film; forming a chemically amplified resist
film to cover the silicon oxide film; forming a first opening in a
position over the chemically amplified resist film where the
vertical wiring section is to be formed; forming a second opening
by etching the silicon oxide film and the interlayer insulation
film while using the chemically amplified resist film as a mask;
and forming the vertical wiring section by filling the second
opening with a conductive material.
3. The method of manufacturing a semiconductor device according to
claim 1, wherein a flow rate of the SiH.sub.4 gas: a flow rate of
the CO.sub.2 gas in a standard condition is in a range of
1:100-1:400 in forming the silicon oxide film.
4. The method of manufacturing a semiconductor device according to
claim 1, wherein a heating temperature is in a range of 350.degree.
C.-500.degree. C. in forming the silicon oxide film.
5. The method of manufacturing a semiconductor device according to
claim 1, wherein a pressure is in a range of 400 Pa-666 Pa in
forming the silicon oxide film.
6. The method of manufacturing a semiconductor device according to
claim 1, wherein an input power is in a range of 400 W-600 W in
forming the silicon oxide film.
7. The method of manufacturing a semiconductor device according to
claim 1, further comprising: forming an antireflection film
containing nitrogen by CVD between forming the silicon oxide film
and forming the chemically amplified resist film.
8. The method of manufacturing a semiconductor device according to
claim 7, wherein the antireflection film includes a silicon nitride
film.
9. The method of manufacturing a semiconductor device according to
claim 8, wherein the antireflection film is formed by plasma CVD
using SiH.sub.4 gas, NH.sub.3 gas, and N.sub.2 gas in forming the
antireflection film.
10. The method of manufacturing a semiconductor device according to
claim 8, wherein the silicon oxide film and the antireflection film
are formed in the same processing chamber.
11. A method of manufacturing a semiconductor device comprising a
wiring structure formed using a dual damascene process, comprising;
sequentially forming a first interlayer insulation film and a
second interlayer insulation film, at least one of the first and
second interlayer insulation films being made of a low dielectric
constant material; forming a silicon oxide film by CVD using
SiH.sub.4 gas and CO.sub.2 gas over the second interlayer
insulation film; forming a first chemically amplified resist film
to cover the silicon oxide film; forming a pattern of an opening
over the first chemically amplified resist film; forming a via hole
to extend through the silicon oxide film, the first interlayer
insulation film, and the second interlayer insulation film, while
using the pattern formed over the first chemically amplified resist
film as a mask; filling the via hole with a filler; forming a
second chemically amplified resist film to cover the second
interlayer insulation film and the filler; forming a pattern of a
wiring groove in an area of the second chemically amplified resist
film including the via hole; forming the wiring groove by etching
the second interlayer insulation film while using the second
chemically amplified resist film as a mask; and filling the via
hole and the wiring groove with a conductive material.
12. The method of manufacturing a semiconductor device according to
claim 11, further comprising: forming an antireflection film
containing nitrogen by CVD between forming the silicon oxide film
and forming the first chemically amplified resist film.
13. The method of manufacturing a semiconductor device according to
claim 1, wherein the low dielectric constant material is any one of
a SiOC film, a SiOF film, a SiO.sub.2-B.sub.2O.sub.3 film, a porous
silica film, and an organosiloxane film.
14. The method of manufacturing a semiconductor device according to
claim 2, wherein the low dielectric constant material is any one of
a SiOC film, a SiOF film, a SiO.sub.2-B.sub.2O.sub.3 film, a porous
silica film, and an organosiloxane film.
15. The method of manufacturing a semiconductor device according to
claim 11, wherein the low dielectric constant material is any one
of a SiOC film, a SiOF film, a SiO.sub.2-B.sub.2O.sub.3 film, a
porous silica film, and an organosiloxane film.
Description
CROSS-REFERENCE TO RELATED ART APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2005-344263, filed on Nov. 29, 2005, the entire contents of which
are hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a method of manufacturing a
semiconductor device having a laminated wiring structure.
[0004] 2. Description of the Related Art
[0005] In recent years, along with expansion of functions and
improvement of performance of semiconductor devices, the number of
transistors mounted on a chip has been significantly increased
while reducing the chip size. As such highly-integrated
semiconductor devices with the reduced chip size require more
wirings, wiring structures having higher density have been
developed.
[0006] However, increasing wiring structure density results in an
increase of wiring capacity C due to reduction of the distance
between wirings, an increase of wiring resistance R due to
reduction of the wiring width, and a consequent increase of RC
wiring delay.
[0007] One solution for these problems is to form wiring structures
using a dual damascene process, where Cu wiring is used in order to
reduce the wiring resistance R and eventually reduce wiring delay.
The dual damascene process is for forming vias as vertical wiring
and wiring of wiring layers at the same time. More specifically,
the dual damascene process is for forming via holes and wiring
grooves, filling the via holes and the wiring grooves with Cu, and
flattening the surface of Cu by chemical mechanical polishing
(CMP).
[0008] For the purpose of reducing wiring capacity, films made of a
low dielectric constant material (so-called "low-k films") are used
as interlayer insulation films. The low-k films have a lower
dielectric constant than silicon oxide films (SiO.sub.2, relative
dielectric constant: 4.3) that have been conventionally used as
interlayer insulation films. Examples of low-k films include
inorganic insulation films of SiOC, porous silica, etc., and
organic insulation films of polyimide series and Teflon.TM.
series.
[0009] The low-k films not only have a lower relative dielectric
constant but also have a lower density than the silicon oxide
films. Accordingly, the low-k films easily absorb process gases,
etching gases, water, and the like used during film formation, and
hold a much larger amount of gas than the silicon oxide films. The
gas held in the low-k films expand during the later heat treatment.
The expanded gas exerts a very high stress on the low-k films and
the wiring layers, and might cause breakage.
[0010] TEOS silicon oxide films (hereinafter referred to as "TEOS
films") are used to cover the surface of the low-k films in order
to prevent absorption of gases, etc., into the low-k films. The
TEOS films are denser than the low-k films, and thus prevent the
process gases, etc., from entering the low-k films from the
outside.
[0011] In the process of forming fine wiring structures in the
low-k films, resist films made of chemically amplified photoresist
materials are used. For example, in the case of the positive type,
when the chemically amplified photoresist materials are exposed to
light, acid substances are produced to form latent images. Then,
when the acid substances are subjected to heat treatment, the acid
substances act on and degrade a dissolution preventing agent so as
to render the latent images soluble by an alkaline developer. If
low-k films are used as interlayer insulation film, gas contained
in the low-k films produces basic substances, which neutralize acid
substances present in the latent image area of the resist films.
The amount of the acid substances thus becomes too small to act on
the dissolution preventing agent, resulting in poor development of
the photoresist film, i.e., so-called "resist poisoning" (or simply
"poisoning").
[0012] Patent Document 1 discloses a laminated structure having a
TEOS film for preventing diffusion of basic substances. According
to Patent Document 1, as shown in FIG. 1, a laminated structure 100
includes TEOS films 103 disposed between low-k films 104 and
silicon nitride films 102 so as to prevent the low-k films 104 from
coming in contact with nitrogen and ammonia gas used for forming
the silicon nitride films 102, thereby preventing resist
poisoning.
[0013] <Patent Document 1> Japanese Patent Laid-Open
Publication No. 2004-6627
[0014] Generally, TEOS films are formed by vaporizing liquid TEOS
as a raw material, and mixing the vaporized TEOS with oxygen
(O.sub.2) gas serving as an oxidizer, with use of plasma chemical
vapor deposition (CVD) devices. In a processing chamber of a
typical plasma CVD device, mixed gas of TEOS and O.sub.2 gas is
ionized by plasma so as to cause a reaction on the surface of a
heated wafer. As a result of the reaction, a TEOS film is formed.
That is, plasma CVD devices used for forming TEOS films need to
have vaporization mechanisms to vaporize liquid TEOS, and therefore
have more complex mechanisms than plasma CVD devices that only use
gas as a raw material. This means that production of semiconductor
devices including such TEOS films requires higher device costs and
higher manufacturing costs.
SUMMARY OF THE INVENTION
[0015] The present invention may solve at least one problem
described above. Specifically, the present invention is directed to
a method of manufacturing a semiconductor device with low
manufacturing cost while forming a fine wiring structure.
[0016] According to an aspect of the present invention, there is
provided a manufacturing method of a semiconductor device
comprising a wiring structure that includes a vertical wiring
section. This method comprises a step of forming an interlayer
insulation film made of a low dielectric constant material on a
wiring layer, a step of forming a silicon oxide film by CVD using
SiH.sub.4 gas and CO.sub.2 gas on the interlayer insulation film, a
step of forming a chemically amplified resist film to cover the
silicon oxide film, and a step of forming a first opening in a
position on the chemically amplified resist film where the vertical
wiring section is to be formed.
[0017] According to this method, the silicon oxide film is formed
on the interlayer insulation film by CVD using SiH.sub.4 gas and
CO.sub.2 gas. Since gases containing nitrogen, such as NH.sub.3 gas
and N.sub.2 gas, are not used as raw materials for the silicon
oxide film, the interlayer insulation film is prevented from being
penetrated by the gases containing nitrogen and ions therein during
formation of the silicon oxide film. The silicon oxide film itself
contains substantially no nitrogen, and therefore prevents NH.sub.3
gas, N.sub.2 gas, and ions ionized from these gases from passing
therethrough. That is, the silicon oxide film prevents generation
of basic substances derived from nitrogen inside the interlayer
insulation film. Thus, resist poisoning in the resist film is
prevented, and a fine wiring structure is formed.
[0018] Moreover, since the silicon oxide film is formed using
SiH.sub.4 gas and CO.sub.2 gas, a CVD device used for forming the
silicon oxide film does not need to have a vaporizing mechanism,
unlike CVD devices used for forming TEOS films, which need to have
vaporizing mechanisms for vaporizing liquid TEOS as a raw material
for the TEOS films. Therefore, the CVD device used for forming the
silicon oxide film can also be used for forming other films such as
antireflection films. In other words, the versatility of the CVD
device used for forming the silicon oxide film is expanded. As a
result, manufacturing costs are reduced.
[0019] According to another aspect of the present invention, there
is provided a method of manufacturing a semiconductor device
comprising a wiring structure formed using a dual damascene
process. This method comprises a step of sequentially forming a
first interlayer insulation film and a second interlayer insulation
film, at least one of the first and second interlayer insulation
films being made of a low dielectric constant material, a step of
forming a silicon oxide film by CVD using SiH.sub.4 gas and
CO.sub.2 gas on the second interlayer insulation film, a step of
forming a first chemically amplified resist film to cover the
silicon oxide film, a step of forming a pattern of an opening on
the first chemically amplified resist film, a step of forming a via
hole to extend through the silicon oxide film, the first interlayer
insulation film, and the second interlayer insulation film, while
using the pattern formed on the first chemically amplified resist
film as a mask, a step of filling the via hole with a filler, a
step of forming a second chemically amplified resist film to cover
the second interlayer insulation film and the filler, a step of
forming a pattern of a wiring groove in an area of the second
chemically amplified resist film including the via hole, a step of
forming the wiring groove by etching the second interlayer
insulation film while using the second chemically amplified resist
film as a mask, and a step of filling the via hole and the wiring
groove with a conductive material.
[0020] According to this method, the silicon oxide film is formed
on the second interlayer insulation film made of the low dielectric
material by CVD using SiH.sub.4 gas and CO.sub.2 gas. As with the
above-described method, this method can prevent resist poisoning
and can form a fine wiring structure. Moreover, since the silicon
oxide film is formed using SiH.sub.4 gas and CO.sub.2 gas, a CVD
device used for forming the silicon oxide film does not need to
have a vaporizing mechanism, unlike CVD devices used for forming
TEOS films, which need to have vaporizing mechanisms for vaporizing
liquid TEOS as a raw material for the TEOS films. Therefore, the
CVD device used for forming the silicon oxide film can also be used
for forming other films such as antireflection films. In other
words, the versatility of the CVD device used for forming the
silicon oxide film is expanded. As a result, manufacturing costs
are reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 illustrates a part of a manufacturing process of a
related-art semiconductor device;
[0022] FIGS. 2-7 illustrate a manufacturing process of a
semiconductor device according to a first embodiment of the present
invention;
[0023] FIG. 8 is a chart showing infrared spectroscopy of silicon
oxide films of Example 1 and Comparative Examples 1 and 2;
[0024] FIG. 9 is a table showing composition of the silicon oxide
films of Example 1 and Comparative Examples 1 and 2;
[0025] FIG. 10 is a table showing properties of the silicon oxide
films of Example 1 and Comparative Examples 1 and 2;
[0026] FIG. 11 is a graph showing a relationship between relative
dielectric constant of a silicon oxide film of Example 2 and film
forming pressure;
[0027] FIG. 12 is a graph showing a relationship between relative
dielectric constant of the silicon oxide film of Example 3 and
plasma input power; and
[0028] FIG. 13 illustrates a part of a manufacturing process of a
semiconductor device according to a second embodiment of the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0029] The following description provides exemplary embodiments of
the present invention with reference to the accompanying drawings.
It is to be noted that a silicon oxide film formed by using
SiH.sub.4 gas and CO.sub.2 gas is referred to as "SiO film" in the
following description.
First Embodiment
[0030] FIGS. 2-7 illustrate a manufacturing process of a
semiconductor device according to a first embodiment of the present
invention. The following describes a manufacturing method of a
semiconductor device of the first embodiment with reference to
FIGS. 2-7.
[0031] In the step shown in FIG. 2, a cap layer 12, a first
interlayer insulation film 13, an SiO film 14, a second interlayer
insulation film 15, an SiO film 16, and an antireflection film 18
are formed on a wiring layer 11 in this order. In this embodiment,
the cap layer 12 is an SiC film (having a thickness of, e.g., 70
nm), and the first and second interlayer insulation films 13 and 15
are SiOC films (having a thickness of, e.g., 550 nm and a thickness
of, e.g., 370 nm, respectively) as low-k films (the low-k films as
used herein are defined as films made of a dielectric material
having a relative dielectric constant lower than 4.3). These layers
are formed with use of CVD devices and sputtering devices.
[0032] The first and second interlayer insulation films 13 and 15
may be any low-k films that are well known in the art.
Non-exclusive examples of low-k films include inorganic insulation
films, such as SiOF and BSG (SiO.sub.2-B.sub.2O.sub.3) films
(relative dielectric constant: 3.5-3.7), films made of porous
silica (relative dielectric constant: 2.4), such as Nano Clustering
Silica (NCS) (Catalysts & Chemicals Industries Co., Ltd.) and
Porous SILK.TM. Y (Dow Chemical Company), and films made of
organosiloxane, such as porous Black Diamond.TM. (Applied
Materials, Inc.,), CORAL.TM. (Novellus Systems, Inc.) (relative
dielectric constant: 3.2), and HOSP.TM. (Honeywell Electronic
Materials Inc) (relative dielectric constant: 2.5).
[0033] The SiO films 14 and 16 are formed using a plasma CVD device
while being supplied with mixed gas of SiH.sub.4 and CO.sub.2 as a
raw material. More specifically, SiO films 14 and 16 are formed
under a condition where SiH.sub.4 gas flow rate is 30 sccm-100
sccm, CO.sub.2 gas flow rate is 5000 sccm-20000 sccm, pressure
inside a processing chamber is 400 Pa-933 Pa (3 Torr-7 Torr),
plasma input power is 100 W-1000 W, and wafer heating temperature
is 350.degree. C.-500.degree. C. By supplying SiH.sub.4 gas mixed
with CO.sub.2 gas at a flow rate much higher than SiH.sub.4 gas,
the SiO films 14 and 16 containing substantially no nitrogen can be
obtained.
[0034] The ratio between the flow rate of SiH.sub.4 gas and
CO.sub.2 gas, i.e.; SiH.sub.4 gas flow rate:CO.sub.2 gas flow rate,
in a standard condition is preferably in a range of 1:100-1:400 in
view of the quality of the SiO films 14 and 16. The reasons why
SiH.sub.4 gas flow rate:CO.sub.2 gas flow rate in the above range
is preferable are as follows: When SiH.sub.4 gas flow rate:CO.sub.2
gas flow rate in a standard condition is 1:100 or greater, Si of
SiH.sub.4 gas is fully oxidized by CO.sub.2 gas to improve the
quality of the SiO films 14 and 16. SiH.sub.4 gas flow
rate:CO.sub.2 gas flow rate in a standard condition may be
1:greater than 400, although the quality of the SiO films 14 and 16
is not improved. Accordingly, considering saving of CO.sub.2 gas
and capacity of the CVD device for supplying CO.sub.2 gas as well,
the ratio between the two gas flow rates is preferably 1:400 or
less. Moreover, when SiH.sub.4 gas flow rate:CO.sub.2 gas flow rate
is in the above range, each of the SiO films 14 and 16 has a growth
rate in an appropriate range and also has a distribution width of
the film thickness inside the wafer in a desired small range.
[0035] When the wafer heating temperature is lower than 350.degree.
C., the quality of the SiO films 14 and 16 tends to decrease. When
the wafer heating temperature is higher than 500.degree. C., since
the thermal expansion rate of a Cu film of the wiring layer 11 is
much higher than the thermal expansion rate of the first and second
interlayer insulation films 13 and 15, a stress is exerted on the
first and second interlayer insulation films 13 and 15, which
increases risk of breakage. For preventing breakage of the low-k
films, the wafer heating temperature is preferably in a range of
350.degree. C.-450.degree. C. The individual thickness of the SiO
films 14 and 16 is in a range of, e.g., 10 nm-100 nm.
[0036] In the case of the related-art technique where TEOS films
are used in place of the SiO films 14 and 16, the CVD devices used
for forming the TEOS films are provided with vaporizing mechanisms
for vaporizing liquid TEOS, and therefore can be used only for
forming the TEOS films. On the other hand, the CVD device used in
this embodiment does not need a vaporizing mechanism because the
raw material used for forming the SiO films 14 and 16 is gas, i.e.,
SiH.sub.4 gas and CO.sub.2 gas. That is, the versatility of the CVD
device used for forming the SiO films 14 and 16 in this embodiment
is expanded. Accordingly, device costs and manufacturing costs can
be reduced.
[0037] The thus obtained SiO films 14 and 16 do not contain
nitrogen of nitrogen gas or nitrogen of ammonia gas because neither
nitrogen gas nor ammonia gas is used. Accordingly, absorption of
nitrogen-derived basic substances into the first and second
interlayer insulation films 13 and 15 during formation of the SiO
films 14 and 16 is avoided. Moreover, as described below in greater
detail, the SiO films 14 and 16 themselves contain substantially no
nitrogen or N--H containing basic substances. Therefore, the SiO
films 14 and 16 do not allow basic substances to pass therethrough,
and can prevent the basic substances from entering and diffusing in
a resist film 20 (described later) even if the basic substances are
contained in the first interlayer insulation film 13 or the second
interlayer insulation film 15. Thus, poisoning is prevented.
[0038] The SiO films 14 and 16 have denser structures than the
low-k films. However, by selecting SiOC films as the low-k films
used as the first and second interlayer insulation films 13 and 15,
tight contact is made between the SiO films 14 and 16 and the first
and second interlayer insulation films 13 and 15, and the
reliability of the semiconductor device is increased. This tight
contact occurs because the SiO films 14 and 16 contain
substantially the same elements as the SiOC films.
[0039] The antireflection film 18 may be made of an inorganic
insulation film containing nitrogen such as a silicon nitride film.
The antireflection film 18 is formed using a plasma CVD device
while being supplied with mixed gas of SiH.sub.4, NH.sub.3 gas, and
N.sub.2 gas as a raw material. The antireflection film 18 is formed
under conditions where, for example, the SiH.sub.4 gas flow rate is
260 sccm, NH.sub.3 gas flow rate is 240 sccm, N.sub.2 gas flow rate
is 900 sccm, pressure inside a processing chamber is 333 Pa (2.5
Torr), plasma input power is 120 W, and wafer heating temperature
is 400.degree. C. The silicon nitride film formed under these
conditions has an attenuation coefficient of about 1.4 at the KrF
excimer laser wavelength. As the coefficient of the silicon nitride
film can be easily controlled by changing the ratio of the flow
rates of the above gases, the antireflection film 18 may be formed
to have a double layer structure of silicon nitride films having
different attenuation coefficients. In that event, the attenuation
coefficients of the lower layer and the upper layer at the KrF
excimer laser wavelength are about 1.4 and about 0.6, respectively.
The lower layer is formed under the above-described conditions,
whereas the upper layer is formed under conditions where the
SiH.sub.4 gas flow rate is 155 sccm, NH.sub.3 gas flow rate is 940
sccm, N.sub.2 gas flow rate is 900 sccm, pressure inside the
processing chamber is 400 Pa (3.0 Torr), plasma input power is 105
W, and wafer heating temperature is 400.degree. C. Although the
antireflection film 18 contains nitrogen, the SiO film 16 prevents
NH.sub.3 gas and N.sub.2 gas from diffusing into the second
interlayer insulation film 15 made of low-k film.
[0040] The SiO film 16 and the antireflection film 18 may be
sequentially formed in the same processing chamber of the same
plasma CVD device under the respective conditions. Since the raw
materials for the SiO film 16 and the antireflection film 18 are
gases only, the SiO film 16 and the antireflection film 18 can be
easily formed by changing the gases used as raw materials.
Moreover, since the SiO film 16 and the antireflection film 18 can
be formed by the same plasma CVD device, device costs and
manufacturing costs can be reduced.
[0041] Further, in the step shown in FIG. 2, a chemically amplified
resist material is applied to the surface of the antireflection
film 18 so as to form the resist film 20. The chemically amplified
material used herein may be a resist material that is exposed by,
e.g., far-ultraviolet rays, such as produced by a KrF excimer laser
and an ArF excimer-laser. Examples of such a chemically amplified
resist material (positive type) include p-hydroxystyrene polymer
esterified to t-butoxycarbonyl group as a photoreaction initiator,
and p-hydroxystyrene polymer esterified with tetrahydropyranyl
group as a photoreaction initiator. When the chemically amplified
resist material is exposed to light, the photoreaction initiator is
desorbed by acid generated by an acid generating agent. Thus, the
remaining polymer becomes soluble in an alkaline developer.
[0042] Further, in the step shown in FIG. 2, a via hole pattern is
exposed on the resist film 20 using, e.g., a KrF excimer laser
(wavelength: 249 nm) producing far-ultraviolet rays. A latent image
is thus formed on the resist film 20, and acid substances are
formed. Since the SiO film 16 serving as an etching stopper layer
is disposed between the resist film 20 and the second interlayer
insulation film 15, the SiO film 16 prevents the basic substances
from transferring from the second interlayer insulation film 15 to
the resist film 20, thereby preventing poisoning.
[0043] Then, in the step shown in FIG. 3, the resist film 20 is
developed to form an opening in a position where a via hole 19a is
to be formed. Then, dry etching is performed to form the via hole
19a using, e.g., CF.sub.4 gas and O.sub.2 gas while masking with
the resist film 20. The thus formed via hole 19a extends through
the antireflection film 18, the SiO film 16, the second interlayer
insulation film 15, the SiO film 14, and the first interlayer
insulation film 13 such that the surface of the cap layer 12 is
exposed. After that, the resist film 20 is removed.
[0044] Then, in the step shown in FIG. 4, a filler 21 is added to
cover the structure of FIG. 3 as well as to fill the via hole 19a.
The filler 21 is made of a resin material such as a resist
material. For example, the filler 21 may be made of a chemically
amplified resist material. The chemically amplified resist material
may be either positive type or negative type. Then, the structure
is heated so as to cure the filler 21. There is no need to heat the
structure if the filler 21 is fully cured without being heated.
[0045] Further, in the step shown in FIG. 4, the filler 21 on the
antireflection film 18 is removed by dry etching. The filler 21
filling in the via hole 19a preferably has the surface at a level
higher than the surface level of the second interlayer insulation
film 15 and at a level lower than the surface level of the
antireflection film 18 so as to prevent the side wall of the second
interlayer insulation film 15 from being etched. The via hole 19a
is therefore prevented from being enlarged in the lateral
direction, so that fine vertical wiring is formed.
[0046] Then, in the step shown in FIG. 5, a resist film 23 is
formed on the surface of the antireflection film 18. A pattern of a
wiring groove 15a is exposed so as to form a latent image of the
pattern on the resist film 23. After that, the structure is baked,
e.g., at 130.degree. C. for 90 seconds.
[0047] Further, in the step shown in FIG. 5, the resist film 23 is
developed by a developer, such as tetramethylammonium hydroxide
(TMAH), so that an opening 23a corresponding to the wiring groove
15a is formed.
[0048] Further, in the step shown in FIG. 5, the wiring groove 15a
is formed by dry etching. More specifically, while being masked
with the resist film 23, the antireflection film 18, the SiO film
16, and the second interlayer insulation film 15 are etched by
using, e.g., CF.sub.4 gas and O.sub.2 so as to expose the surface
of the SiO film 14. During the etching, the filler 21 is partly
etched such that the surface level of the filler 21 is lowered to
about the surface level of the SiO film 14.
[0049] Then, in the step shown in FIG. 6, the resist film 23 and
the filler 21 are removed by ashing. The cap layer 12 at the bottom
of the via hole 19a, the SiO film 14 at the bottom of the wiring
groove 15a, and the antireflection film 18 are then removed by dry
etching, so that the surface of the wiring layer 11 is exposed.
[0050] Then, in the step shown in FIG. 7, a barrier metal layer
(not shown) made of, e.g., TiN film and a seed metal layer (not
shown) made of, e.g., Cu film are sequentially formed on the side
surfaces and the bottom surfaces of the via hole 19a and the wiring
groove 15a by sputtering. Then, a Cu film 25 (or a CuAl film) is
formed by plating to fill the wiring groove 15a and the via hole
19a as well as to cover the structure of FIG. 6. The surface of the
Cu film 25 is polished by CMP. The polishing is stopped on the
surface of the SiO film 16 which reduces the polishing speed
compared to the Cu film 25. It is to be noted that the SiO film 16
may be removed by polishing as shown in FIG. 7 or may not be
removed. With the steps described above, the wiring structure is
formed using the dual damascene process.
[0051] According to the first embodiment, the surfaces of the first
and second interlayer insulation films 13 and 15 made of low-k film
are covered with the corresponding SiO films 14 and 16 formed by
CVD using SiH.sub.4 gas and CO.sub.2 gas. Since neither NH.sub.3
gas nor N.sub.2 gas is used for forming the SiO films 14 and 16,
the first and second interlayer insulation films 13 and 15 are
prevented from being penetrated by these gases and ions therein
during formation of the SiO films 14 and 16.
[0052] The SiO film 16 itself contains substantially no nitrogen,
and therefore does not allow NH.sub.3 gas, N.sub.2 gas, and ions
ionized from these gases to pass therethrough. That is, the SiO
film 16 prevents NH.sub.3 gas, N.sub.2 gas, and ions ionized from
these gases from entering the second interlayer insulation film 15
while the antireflection film 18 made of silicon nitride film is
formed on the SiO film 16.
[0053] Accordingly, production of nitrogen-derived or N--H-derived
basic substances in the second interlayer insulation film 15 is
prevented, thereby preventing resist poisoning. As a result, the
fine wiring structure is formed.
[0054] Since the SiO films 14 and 16 are formed using SiH.sub.4 gas
and CO.sub.2 gas, there is no need to use a vaporizing mechanism,
unlike the case of forming TEOS films where vaporizing mechanisms
are used for vaporizing liquid TEOS used as a raw material for the
TEOS films. Therefore, the plasma CVD device used for forming the
SiO films 14 and 16 can also be used for forming other films such
as the antireflection film 18. In other words, the versatility of
the plasma CVD device used for forming the SiO films 14 and 16 is
expanded. Moreover, the SiO film 16 and the antireflection film 18
can be sequentially formed in the same processing chamber by the
same plasma CVD device. This simplification of production process
can reduce manufacturing costs.
[0055] In the related-art technique, since O.sub.2 gas used as an
oxidizer for forming the TEOS films has high oxidizing power,
reaction of mixed gas of vaporized TEOS and O.sub.2 gas often
causes dust in a pipe through which the mixed gas passes. The dust
contaminates the processing chamber of the plasma CVD device, and
consequently lowers production yield of semiconductor devices. In
this embodiment, on the other hand, since CO.sub.2 gas, which has a
lower oxidizing power than O.sub.2 gas, is used as an oxidizer for
forming the SiO films 14 and 16, generation of dust can be
reduced.
[0056] While both the first and second interlayer insulation films
13 and 15 are low-k films in the first embodiment, one of the first
and second interlayer insulation films 13 and 15 may be made of
low-k film and the other one may be a silicon oxide film, such as a
TEOS film.
[0057] While the SiO films 14 and 16 also serve as etching stopper
layers in the first embodiment, etching stopper layers may be
separately provided on or under the corresponding SiO films 14 and
16. The etching stopper layers may be made of, for example, SiC
films. The etching stopper layer may also be made of silicon
nitride films. In that event, each of the SiO films 14 and 16 is
formed to sandwich the corresponding silicon nitride film such that
the silicon nitride films are kept out of direct contact with the
first and the second interlayer insulation films 13 and 15. Thus,
the SiO film 16 can prevent NH.sub.3 gas, N.sub.2 gas, and ions
ionized from these gases from entering the first or second
interlayer insulation film 13 or 15.
[0058] The following are specific examples of the first embodiment
and comparative examples. In Example 1, composition analysis and
measurements of properties, such as relative dielectric constant,
were performed on the SiO film. In Comparative Examples 1 and 2,
composition analysis and property measurements were performed on a
TEOS film and a silicon oxide film containing nitrogen in the same
manner as in Example 1 for comparison purpose.
Example 1
[0059] In Example 1, the SiO film was formed using the plasma CVD
device. The thickness of the SiO film was set to 400 nm for the
purpose of facilitating the analysis. The thickness of each of the
TEOS film of Comparative Example 1 and the silicon oxide film of
Comparative Example 2 was also set to 400 nm. The SiO film of
Example 1 was formed under the following conditions. [0060]
SiH.sub.4 gas flow rate: 50 sccm [0061] CO.sub.2 gas flow rate:
10000 sccm [0062] Pressure inside the processing chamber: 666 Pa (5
Torr) [0063] Plasma input power: 500 W [0064] Heating temperature:
400.degree. C.
Comparative Example 1
[0065] In Comparative Example 1, which is not according to the
present invention, the TEOS film having a thickness of 400 nm was
formed. The composition analysis and the property measurements were
performed in the same manner as in Example 1. The TEOS film of
Comparative Example 1 was formed under the following conditions.
[0066] TEOS liquid flow rate: 2 slm [0067] CO.sub.2 gas flow rate:
10000 sccm [0068] Pressure inside the processing chamber: 666 Pa (5
Torr) [0069] Heating temperature: 350.degree. C. [0070] Plasma
input power: 1000 W
Comparative Example 2
[0071] In Comparative Example 2, which is not according to the
present invention, the silicon oxide film containing nitrogen and
having a thickness of 400 nm was formed. The composition analysis
and the property measurements were performed in the same manner as
in Example 1. The silicon oxide film of Comparative Example 2 was
formed under the following conditions. [0072] SiH.sub.4 gas flow
rate: 150 sccm [0073] N.sub.2O gas flow rate: 700 sccm [0074]
N.sub.2 gas flow rate: 2000 sccm [0075] Pressure inside the
processing chamber: 666 Pa (5 Torr) [0076] Heating temperature:
400.degree. C. [0077] Plasma input power: 500 W
[0078] FIG. 8 is a chart showing infrared spectroscopy of Example 1
and Comparative Examples 1 and 2. Referring to FIG. 8, in the case
of silicon oxide film of Comparative Example 2 using SiH.sub.4 gas
and N.sub.2O gas, absorption due to N--H stretching vibration was
observed at about 3400 cm.sup.-1. It is deduced from this result
that the silicon oxide film of Comparative Example 2 allows
absorption of N--H containing basic substances into the low-k film,
and there is therefore a risk of resist poisoning. On the other
hand, in the case of the SiO film of Example 1 and the TEOS film of
Comparative Example 1, almost no absorption due to N--H stretching
vibration was found. It is deduced from this result that each of
the films of Example 1 and Comparative Example 1 contains fewer
N--H groups than the film of Comparative Example 2, and the risk of
resist poisoning in Example 1 and Comparative Example 1 is lower
than Comparative Example 2.
[0079] FIG. 9 is a table showing composition of the silicon oxide
films of Example 1 and Comparative Examples 1 and 2. Referring to
FIG. 9, the result of composition analysis using X-ray
photoelectron spectroscopy shows that the proportion of nitrogen
contained in the film of Comparative Example 2 was 3.39%, whereas
the proportions of nitrogen contained in the film of Example 1 and
the film of Comparative Example 1 were much lower than in
Comparative Example 2, which are 0.70% and 0.76%, respectively. It
is found from this result as well that the risk of resist poisoning
in Example 1 and Comparative Example 1 is low.
[0080] It is to be noted that the nitrogen in
[0081] Example 1 and Comparative Example 1 is not derived from
contamination in the processing chamber of the plasma CVD device.
AXIS-His (Kratos Analytical Inc.,) was used for the composition
analysis, and the proportion (%) shown in FIG. 9 is expressed in
atomic %.
[0082] FIG. 10 is a table showing properties of the silicon oxide
films of Example 1 and Comparative Examples 1 and 2. As shown in
FIG. 10, while the relative dielectric constant of the TEOS film of
Comparative Example 1 was 4.33, the relative dielectric constant of
the SiO film of Example 1 was 4.04, which is lower than that of
Comparative Example 1. It is found from this result that the RC
wiring delay in Example 1 is less than in the RC wiring delay in
Comparative Example 1.
[0083] The density of the film of Example 1 was substantially the
same as the density of the film of Comparative Example 1. In other
words, there was no big density difference between the film of
Example 1 and the film of Comparative Example 1. It is therefore
deduced that capabilities of the films of Example 1 and Comparative
Example 1 for preventing the passage of NH3 gas, N2 gas, ions
ionized from these gases are almost at the same level.
Example 2
[0084] In Examples 2-1, 2-2, and 2-3, the SiO films were formed
using the plasma CVD device while setting the pressure inside the
processing chamber at different levels from 533 Pa to 800 Pa (4
Torr to 6 Torr). The pressures inside the processing chamber in
Examples 2-1, 2-2, and 2-3 were 533 Pa (4 Torr), 666 Pa (5 Torr),
and 800 Pa (6 Torr), respectively. Conditions applied to film
formation in Examples 2-1-2-3 other than the pressure inside the
processing chamber are as follows. [0085] SiH.sub.4 gas flow rate:
50 sccm [0086] CO.sub.2 gas flow rate: 10000 sccm [0087] Heating
temperature: 400.degree. C. [0088] Plasma input power: 500 W
[0089] FIG. 11 is a graph showing a relationship between relative
dielectric constant of the silicon oxide film and film forming
pressure in Examples 2-1-2-3. The graph of FIG. 11 also shows the
relative dielectric constants of the films of Comparative Examples
1 and 2 of FIG. 10 for explanation purposes.
[0090] As shown in FIG. 11, the relative dielectric constants of
all the SiO films of Examples 2-1-2-3 were lower than the relative
dielectric constant of the TEOS film of Comparative Example 1. That
is, the relative dielectric constants of the SiO films formed at a
film forming pressure in the range of 533 Pa-800 Pa (4 Torr-6 Torr)
were lower than the TEOS film of Comparative Example 1.
Accordingly, it is found that the SiO films of Examples 2-1-2-3 are
more effective than the TEOS film of Comparative Example 1 in
reducing wiring delay.
Example 3
[0091] In Examples 3-1, 3-2, 3-3, and 3-4, the SiO films were
formed using the plasma CVD device while setting the plasma input
power at different levels from 300 W to 600 W. The plasma input
powers in Examples 3-1, 3-2, 3-3, and 3-4 were 300 W, 400 W, 500 W,
and 600 W, respectively. Conditions applied to film formation in
Examples 3-1-3-4 other than the plasma input power are as follows.
[0092] SiH.sub.4 gas flow rate: 50 sccm [0093] CO.sub.2 gas flow
rate: 10000 sccm [0094] Pressure inside the processing chamber: 666
Pa (5 Torr) [0095] Heating temperature: 400.degree. C.
[0096] FIG. 12 is a graph showing a relationship between relative
dielectric constant of the SiO film and plasma input power in
Examples 3-1-3-4. The graph of FIG. 12 also shows the relative
dielectric constants of the films of Comparative Examples 1 and 2
of FIG. 10 for explanation purposes.
[0097] As shown in FIG. 12, the relative dielectric constants of
all the SiO films of Examples 3-2-3-4 were lower than the relative
dielectric constant of the TEOS film of Comparative Example 1. That
is, the relative dielectric constants of the SiO films formed with
a plasma input power in the range of 400 W-600 W are lower than the
TEOS film of Comparative Example 1. Accordingly, it is found that
the SiO films of Examples 3-2-3-4 are more effective than the TEOS
film of Comparative Example 1 in reducing wiring delay.
Second Embodiment
[0098] A method of manufacturing a semiconductor device of a second
embodiment of the present invention is almost the same as the
method of manufacturing a semiconductor device of the first
embodiment except that an SiO film 22 is formed under a resist film
23 for forming a wiring groove pattern.
[0099] FIG. 13 illustrates a part of a manufacturing process of the
semiconductor device according to the second embodiment of the
present invention. The following describes the method of
manufacturing the semiconductor device of the second embodiment
with reference to FIGS. 2-4, 6, and 7 of the first embodiment, and
FIG. 13.
[0100] According to the manufacturing process of the semiconductor
device of the second embodiment, the steps shown in FIGS. 2-4 are
first performed.
[0101] Then, in the step shown in FIG. 13, the SiO film 22 having a
thickness of, e.g., 50 nm is formed on the surface of the structure
of FIG. 4. The SiO film 22 is formed using the same method of
forming the SiO films 14 and 16 of the first embodiment shown in
FIG. 2. More specifically, the SiO film 22 is formed using a plasma
CVD device while being supplied with mixed gas of SiH.sub.4 and
CO.sub.2 as a raw material. The condition for forming the SiO film
22 is the same as the condition for forming the SiO films 14 and 16
of the first embodiment shown in FIG. 2.
[0102] Further, in the step shown in FIG. 13, an antireflection
film 24 is formed to cover the SiO film 22. The antireflection film
24 is formed using the same method of forming the antireflection
film 18 of the first embodiment shown in FIG. 2.
[0103] Further, in the step shown in FIG. 13, the resist film 23 is
formed on the antireflection film, and a latent image corresponding
to the pattern of the wiring groove is formed on the resist film
23. Then, the resist film 23 is developed to form the opening 23a.
After that, the antireflection film 24, the SiO film 22, the
antireflection film 18, the SiO film 16, and the second insulation
layer 15 are etched while being masked with the resist film 23 with
the opening 23a, so that the wiring groove is formed. Then, the
same steps of FIGS. 5-7 are taken to form a wiring structure using
the dual damascene process.
[0104] According to the second embodiment, since the SiO film 22 is
formed on the surface of the filler 21, the basic substances
absorbed in the first or the second interlayer insulation films 13
or 15 during formation and cleaning of the via hole 19a are
prevented from reaching the resist film 23 through the filler 21.
As the resist poisoning is thus prevented, a fine wiring structure
is formed. Moreover, since the antireflection film 24 is formed on
the surface of the SiO film 22, the reflection light returning to
the resist film 23 upon the exposure of the wiring groove pattern
is reduced, thereby making the wiring structure finer. Although it
is preferable to provide the antireflection film 24, the
antireflection film 24 may be unnecessary if the width of the
wiring groove is wide enough.
[0105] While the present invention has been described in terms of
preferred embodiments, it will be apparent to those skilled in the
art that variations and modifications may be made without departing
from the scope of the invention as set forth in the accompanying
claims.
[0106] For instance, the dual damascene process used when forming
the SiO films in the first and second embodiments includes forming
wiring grooves after forming via holes, but other dual damascene
processes may be used. The SiO films of the present invention are
not limited to SiO films formed using the dual damascene process,
and may be widely used as protective films for interlayer
insulation films, especially for interlayer insulation films made
of low-k materials.
* * * * *