U.S. patent application number 11/248176 was filed with the patent office on 2007-04-19 for plating apparatuses and processes.
This patent application is currently assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.. Invention is credited to Kei-Wei Chen, Shih-Ho Lin, Yu-Ku Lin, Ying-Lang Wang.
Application Number | 20070084730 11/248176 |
Document ID | / |
Family ID | 37947146 |
Filed Date | 2007-04-19 |
United States Patent
Application |
20070084730 |
Kind Code |
A1 |
Chen; Kei-Wei ; et
al. |
April 19, 2007 |
Plating apparatuses and processes
Abstract
Plating apparatuses and plating processes. Plating apparatuses
includes a plating station and a post plating treatment station
adjacent to the plating station. The plating station comprises at
least one plating cell and provides a first environment therein
with a first relative humidity (RH) higher than that of a clean
room where the plating apparatus is disposed. The post plating
treatment station provides a second environment therein with a
second RH lower than the first RH.
Inventors: |
Chen; Kei-Wei; (Taipei,
TW) ; Lin; Shih-Ho; (Hsinchu, TW) ; Lin;
Yu-Ku; (Hsinchu, TW) ; Wang; Ying-Lang;
(Tai-Chung, TW) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Assignee: |
TAIWAN SEMICONDUCTOR MANUFACTURING
CO., LTD.
|
Family ID: |
37947146 |
Appl. No.: |
11/248176 |
Filed: |
October 13, 2005 |
Current U.S.
Class: |
205/220 ;
148/518; 257/E21.175; 257/E21.585 |
Current CPC
Class: |
H05K 3/423 20130101;
C25D 21/12 20130101; H01L 21/76877 20130101; C25D 21/00 20130101;
C25D 5/00 20130101; C25D 7/123 20130101; H01L 21/2885 20130101 |
Class at
Publication: |
205/220 ;
148/518 |
International
Class: |
C25D 5/48 20060101
C25D005/48 |
Claims
1. A plating apparatus, comprising: a plating station, comprising
at least one plating cell, providing a first environment therein
with a first relative humidity (RH) higher than that of a clean
room where the plating apparatus is disposed; and a post plating
treatment station adjacent to the plating station, providing a
second environment therein with a second RH lower than the first
RH.
2. The apparatus as claimed in claim 1, further comprising: a
loading station adjacent to the plating station; and an unloading
station adjacent to the post plating treatment station.
3. The apparatus as claimed in claim 1, wherein the first RH is
higher than 40%.
4. The apparatus as claimed in claim 1, wherein the first RH is
higher than 60%.
5. The apparatus as claimed in claim 1, wherein the second RH is
between 30% and 40%.
6. The apparatus as claimed in claim 1, wherein the first RH is
controlled by introduction of deionized vapor or wet nitrogen into
the plating station.
7. A plating process, comprising: providing a wafer comprising a
recess thereon; plating a metal layer in the recess under a first
relative humidity (RH) higher than that of a clean room for wafer
fabrication; and performing a post plating treatment procedure on
the wafer under a second RH lower than the first RH.
8. The method as claimed in claim 7, wherein the post plating
treatment procedure further comprises: Cleaning and drying the
wafer; and annealing the metal layer.
9. The method as claimed in claim 7, wherein the first RH is higher
than 40%.
10. The method as claimed in claim 7, wherein the first RH is
higher than 60%.
11. The method as claimed in claim 7, wherein the second RH is
between 30% and 40%.
12. The method as claimed in claim 7, wherein the first RH is
controlled by introduction of deionized vapor or wet nitrogen.
13. The method as claimed in claim 7, wherein the metal layer is
substantially copper.
14. The method as claimed in claim 7, wherein the metal layer is
formed by electroplating.
Description
BACKGROUND
[0001] The invention relates to semiconductor technology, and more
specifically to plating apparatuses and processes.
[0002] In the back end of a semiconductor chip fabricating process,
the metal systems necessary to connect the devices and different
layers are added to a chip by a process called metallization,
comprising forming a dielectric layer over a semiconductor wafer,
planarizing and patterning the dielectric layer to form trenches
and/or vias, and filling the trenches and/or vias to form
conductive wires and/or via plugs. A chemical mechanical polishing
process is then performed to planarize the surface of the
wafer.
[0003] When the wires and plugs are metal such as copper or copper
alloys, they are typically formed by electroplating or electroless
plating. The wires and plugs, however, cannot be completely adhered
to the dielectric layer, forming gaps therebetween. Metal peel-off
may occur at the gaps resulting from stress exertion in subsequent
processes, negatively affecting the yield of the wafer production
process and reliability of a product using a device from the
wafer.
[0004] JP2002129385, Ito et al., discloses a plating method
comprising a pre-treatment step, a plating step, and a
post-treatment step, wherein the pre-treatment step comprises
spraying water or a liquid comprising plating bath to wet a
predetermined plating surface of a wafer, and the post-treatment
step is to rinse the wafer. The pre-treatment and post-treatment
steps can be performed in the same post-treatment station of a
plating apparatus used by the method. Further, a pre-treatment
station may be added in the plating apparatus for the pre-treatment
step. When the pre-treatment and post-treatment steps are performed
in the same station, the processing wafer is transferred to the
post-treatment stations, followed by transfer to a plating station
and transfer back to the post-treatment stations, thus, the
operational flow of the plating apparatus is complicated and
processing is prolonged. When the pre-treatment station is added to
the plating apparatus, the apparatus must be modified, prolonging
the process period, and negatively affecting process cost and
throughput.
SUMMARY
[0005] The invention provide plating apparatuses and processes
utilizing the same, substantially preventing metal peel-off from
dielectric layers without affecting process duration and
operational flow of the apparatus, improving yield and reliability
of the semiconductor device.
[0006] The invention provides a plating apparatus. The apparatus
comprises a plating station and a post plating treatment station
adjacent to the plating station. The plating station comprises at
least one plating cell and provides a first environment therein
with a first relative humidity (RH) higher than that of a clean
room where the plating apparatus is disposed. The post plating
treatment station provides a second environment therein with a
second RH lower than the first RH.
[0007] The invention further provides a plating process utilizing
the plating apparatus. First, a wafer comprising a recess thereon
is provided. A metal layer is then plated in the recess under a
first relative humidity (RH) higher than that of a clean room for
wafer fabrication. Finally, a post plating treatment procedure is
performed on the wafer under a second RH lower than the first
RH.
[0008] Further scope of the applicability of the invention will
become apparent from the detailed description given hereinafter. It
should be understood, however, that the detailed description and
specific examples, while indicating preferred embodiments of the
invention, are given by way of illustration only, since various
changes and modifications within the spirit and scope of the
invention will become apparent to those skilled in the art from
this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The invention can be more fully understood by reading the
subsequent detailed description in conjunction with the examples
and references made to the accompanying drawings, which are given
by way of illustration only, and thus are not limitative of the
invention, and wherein:
[0010] FIG. 1 is a schematic diagram of a plating apparatus of the
invention.
[0011] FIGS. 2A through 2C are schematic diagrams of a plating
process of the invention.
DESCRIPTION
[0012] The following embodiments are intended to illustrate the
invention more fully without limiting the scope of the claims,
since numerous modifications and variations will be apparent to
those skilled in this art.
[0013] The inventors discover that a plating bath tends to be
hydrophobic resulting from macromolecular additions therein. Thus,
contact angle between the plating bath and a processing wafer is
too large (typically between 20 and 70 degrees) to completely wet a
predetermined plating surface of the wafer, resulting in gaps
formed between the wafer and a metal layer subsequently formed by
plating. The subsequent plating apparatus and process can
effectively decrease the contact angle between wafer and plating
bath, substantially preventing gaps from forming between the wafer
and a metal layer subsequently formed by plating.
[0014] FIG. 1 shows a schematic diagram of an embodiment of a
plating apparatus. The apparatus comprises a plating station 120
and post plating treatment station 130 adjacent to the plating
station 120.
[0015] The plating station 120 typically comprises at least one
plating cell 125. The plating cell 125 comprises a plating bath
therein. The bath compositions depend on materials predetermined
for plating of processed wafers. When plating copper on the wafer,
for example, the main composition of the plating bath is copper
sulphate and two or more macromolecular additives. The plating
station 120 may further comprise a robot arm for holding and
transferring the processing wafers. The plating station 120
provides a first environment with a first relative humidity (RH)
higher than a clean room where the plating apparatus is disposed.
The first RH is preferably higher than 40%, and more preferably
higher than 60%. The first RH is preferably controlled by
introduction of deionized vapor or wet nitrogen along an original
atmosphere control system of the apparatus into the plating station
120.
[0016] The post plating treatment station 130 typically comprises
systems 131 and 132. The system 131, typically comprising
spin/rinse/dry (SRD) and/or integrated bevel clean (IBC)
sub-systems, is utilized following the metal plating to remove
undesirable deposits from the backside and edges of the processing
wafers. The system 132 typically comprises a heating device to
anneal the metal layer on the processing wafer. The post plating
treatment station 130 provides a second environment with a second
RH lower than the first RH. In this embodiment, the second RH is
between 30% and 40%.
[0017] The plating apparatus may further comprise a loading station
110 adjacent to the plating station 120, and an unloading station
140 adjacent to the post plating treatment station 130 respectively
for automatic wafer loading and unloading.
[0018] Subsequently, a plating process utilizing the plating
apparatus is disclosed.
[0019] In FIG. 2A, a wafer 200 comprising a recess 221 thereon is
provided. Specifically, the wafer 200 comprises a substrate 210 and
a dielectric layer on the substrate 210, and the recess 221 exposes
parts of the substrate 210. In this embodiment, the recess 221 is a
single damascene structure. In an alternative embodiment, the
recess 221 is a dual damascene structure.
[0020] In FIG. 2B, and further referring to FIG. 1, the wafer 200
can be loaded in the plating station 120 via the loading station
110, followed by plating a metal layer 230 in the recess 221 using
a method such as electroplating under the first RH. In this
embodiment, the metal layer 230 is copper.
[0021] The first RH is preferably higher than 40% for wetting the
wafer 200 to decrease the contact angle between the plating bath
and the wafer 200 to less than 20 degrees, and thus, adhesion
between the wafer 200 and the metal layer 120 is improved,
improving the process yield and product reliability. The first RH
is more preferably higher than 60%. In this embodiment, the.
contact angle between the plating bath and the wafer 200 is reduced
to approximately 12 degrees, substantially preventing gaps between
the plating bath and wafer 200, and thus, process yield and product
reliability is further improved. Thus, wetting of the wafer 200 is
achieved without additional steps or stations, further reducing
process cost and increasing throughput compared to Ito et al.
[0022] In FIG. 2C, and further referring to FIG. 1, the wafer 200
is transferred to the post plating treatment station 130 to perform
a post plating treatment procedure thereon under the second RH. The
post plating treatment procedure typically comprises cleaning and
drying the wafer 200 utilizing the system 131, and annealing the
metal layer 230 for improving electrical property utilizing the
system 131. Finally, the processed wafer 200 can be unloaded
utilizing the unloading station 130.
[0023] Conventional process data of electroplating a copper layer
on a wafer show the plating yield is approximately 67.10%. In an
embodiment of the invention, the plating yield is approximately
82.62%, effectively improving the process yield, and thus, product
reliability can be effectively improved.
[0024] Further, the inventors discover an additional advantage. The
conventional copper plating apparatus suffers copper sulphate
particle contamination from the plating cell thereof. The control
of the first RH of the invention tends to decrease particle
contamination, and thus, the preliminary maintenance (PM) frequency
for the plating apparatus can be decreased, further decreasing
process cost.
[0025] Thus, the results show the efficacy of the inventive plating
apparatuses and methods in reducing contact angle between plating
bath and a processing wafer, and preventing metal peel-off from the
wafer, thus improving process yield and product reliability.
[0026] While the invention has been described by way of example and
in terms of preferred embodiment, it is to be understood that the
invention is not limited thereto. It is therefore intended that the
following claims be interpreted as covering all such alteration and
modifications as fall within the true spirit and scope of the
invention.
* * * * *