U.S. patent application number 11/595361 was filed with the patent office on 2007-03-15 for multi-part lead frame with dissimilar materials.
Invention is credited to Jerry M. Brooks, David J. Corisis, S. Derek Hinkle.
Application Number | 20070057354 11/595361 |
Document ID | / |
Family ID | 24967457 |
Filed Date | 2007-03-15 |
United States Patent
Application |
20070057354 |
Kind Code |
A1 |
Hinkle; S. Derek ; et
al. |
March 15, 2007 |
Multi-part lead frame with dissimilar materials
Abstract
A multi-part lead frame semiconductor device assembly is
disclosed including a die bonded to a die paddle. A second lead
frame including leads is superimposed and bonded onto the first
lead frame. Also disclosed is a method for fabricating the
multi-part lead frame semiconductor device assembly which utilizes
equipment designed for single lead frame processing. If desired,
the materials for the multi-part lead frame may be dissimilar.
Inventors: |
Hinkle; S. Derek; (Boise,
ID) ; Brooks; Jerry M.; (Caldwell, ID) ;
Corisis; David J.; (Meridian, ID) |
Correspondence
Address: |
TRASK BRITT, P.C./ MICRON TECHNOLOGY
P.O. BOX 2550
SALT LAKE CITY
UT
84110
US
|
Family ID: |
24967457 |
Appl. No.: |
11/595361 |
Filed: |
November 9, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11351165 |
Feb 9, 2006 |
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11595361 |
Nov 9, 2006 |
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11137034 |
May 25, 2005 |
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11351165 |
Feb 9, 2006 |
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10443468 |
May 22, 2003 |
6946722 |
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11137034 |
May 25, 2005 |
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09441524 |
Nov 16, 1999 |
6570244 |
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10443468 |
May 22, 2003 |
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08738308 |
Oct 25, 1996 |
6072228 |
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09441524 |
Nov 16, 1999 |
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Current U.S.
Class: |
257/676 ;
257/E23.038; 257/E23.042; 257/E23.043; 257/E23.053; 257/E23.054;
438/123 |
Current CPC
Class: |
H01L 2924/01047
20130101; H01L 2924/12044 20130101; H01L 24/45 20130101; H01L
2924/01027 20130101; H01L 2924/01042 20130101; H01L 2224/48247
20130101; H01L 2224/04042 20130101; H01L 2224/49171 20130101; H01L
2924/01078 20130101; H01L 2224/05554 20130101; H01L 2224/05599
20130101; H01L 23/49579 20130101; H01L 24/48 20130101; H01L
23/49565 20130101; H01L 24/49 20130101; H01L 2224/45144 20130101;
H01L 2224/4826 20130101; H01L 2224/85399 20130101; H01L 2924/01033
20130101; H01L 2924/00014 20130101; H01L 2224/48091 20130101; H01L
2224/85399 20130101; H01L 2224/48599 20130101; H01L 2924/01082
20130101; H01L 2224/48247 20130101; H01L 2924/01029 20130101; H01L
2924/181 20130101; H01L 23/49537 20130101; H01L 23/49582 20130101;
H01L 2924/01079 20130101; H01L 2924/09701 20130101; H01L 2224/49171
20130101; H01L 2924/01005 20130101; H01L 23/4951 20130101; H01L
2224/06136 20130101; H01L 2924/01013 20130101; H01L 2224/48599
20130101; H01L 2924/00014 20130101; H01L 2924/181 20130101; H01L
23/49503 20130101; H01L 24/06 20130101; H01L 2924/01014 20130101;
H01L 2924/01006 20130101; H01L 23/49506 20130101; H01L 2224/48091
20130101; H01L 2924/00014 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2924/00012 20130101; H01L 2924/00 20130101;
H01L 2224/05599 20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
257/676 ;
438/123; 257/E23.043 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 21/00 20060101 H01L021/00 |
Claims
1. A semiconductor device assembly comprising: a semiconductor
device including an active surface having at least one bond pad
formed thereon; a die paddle having the semiconductor device
attached thereto, the die paddle substantially formed of a first
material, the die paddle formed on a first level; a lead frame
including at least two carriers and a plurality of leads, each
carrier of the at least two carriers having an attachment
tab-receiving portion, the lead frame substantially formed of a
second material different than the first material of the die
paddle, wherein at least one lead of the plurality of leads extends
over a semiconductor device attached to the die paddle, does not
extend over a semiconductor device attached to the die paddle,
overlaps the die paddle, or terminates adjacent the die paddle, the
lead frame formed on a second level; and at least one
interconnection between at least one lead of the plurality of leads
of the lead frame and the at least one bond pad of the
semiconductor device.
2. The semiconductor device assembly according to claim 1, wherein
a heat conductivity of the first material of the die paddle is
different than that of the second material of the lead frame.
3. The semiconductor device assembly according to claim 1, wherein
an electrical conductivity of the second material of the lead frame
is different than that of the first material of the die paddle.
4. The semiconductor device assembly according to claim 1, wherein
an electrical conductivity of the second material of the lead frame
is greater than an electrical conductivity of the die paddle.
5. The semiconductor device assembly according to claim 1, further
including an insulating film, the insulating film covering a
portion of the active surface of the semiconductor device.
6. The semiconductor device assembly according to claim 1, wherein
the first material of the die paddle is selected from the group
comprising alloy 42, copper alloy, aluminum alloy, silver alloy,
copper-clad Invar, copper-clad molybdenum, ceramic compounds,
plastic compounds, glass epoxy-based compounds, and reinforced
organic compounds.
7. The semiconductor device assembly according to claim 1, wherein
the second material of the lead frame is selected from the group
comprising alloy 42, copper alloy, aluminum alloy, and silver
alloy.
8. The semiconductor device assembly according to claim 1, wherein
the at least one interconnection includes a wire bond.
9. A semiconductor device assembly having a semiconductor die
assembly comprising: a semiconductor die including an active
surface having at least one bond pad formed thereon; a separately
formed die paddle onto which said semiconductor die is attached; a
separately formed lead frame including at least two carriers, each
carrier having an attachment tab receiving portion, said lead frame
having plurality of leads, the plurality of leads each having a
length terminating adjacent said semiconductor device; and at least
one interconnection between at least one lead of said plurality of
leads of said separately formed lead frame and said at least one
bond pad of said semiconductor die attached to said separately
formed die paddle.
10. A semiconductor device assembly according to claim 9, wherein
the heat conductivity of said die paddle is different than that of
said lead frame.
11. A semiconductor device assembly according to claim 9, wherein
the material of said die paddle is different than the material of
said lead frame.
12. A semiconductor device assembly according to claim 9, wherein
the electrical conductivity of the material of said lead frame is
different than that of the material of said die paddle.
13. A semiconductor device assembly according to claim 9, wherein
the electrical conductivity of the material of said lead frame is
greater than that of the material of said tie bars.
14. A semiconductor device assembly according to claim 9, wherein
the material of said die paddle is selected from the group
comprising alloy 42, copper alloy, aluminum alloy, silver alloy,
copper-clad Invar, copper-clad molybdenum, ceramic compounds,
plastic compounds, glass epoxy based compounds, and reinforced
organic compounds.
15. A semiconductor device assembly according to claim 9, wherein
the material of said lead frame is selected from the group of alloy
42, copper alloy, aluminum alloy, and silver alloy.
16. A semiconductor device assembly according to claim 9, wherein
the interconnection includes a wire bond.
17. A semiconductor die assembly comprising: a semiconductor die
including an active surface having at least one bond pad formed
thereon; a die paddle of a first material onto which said
semiconductor die is attached; at least one tie bar connected to
said die paddle, the tie bar including an attachment tab thereon; a
lead frame of a second material including carriers, each carrier
having an attachment tab receiving portion attached to a portion of
said attachment tab of a tie bar, and a plurality of leads, each
lead including an inner lead portion and an outer lead portion; and
at least one interconnection between at least one said inner lead
portion of said lead frame and said at least one bond pad of said
semiconductor die.
18. A semiconductor die assembly according to claim 17, wherein
said inner lead portion of at least one of the leads extends over
said active surface of said semiconductor die.
19. A semiconductor die assembly according to claim 17, wherein
said inner lead portion of at least one of the leads does not
extend over said active surface of said semiconductor die.
20. A semiconductor die assembly according to claim 17, wherein
said inner lead portion of at least one of the leads overlaps said
die paddle.
21. A semiconductor die assembly according to claim 17, wherein
said lead frame and said tie bar are made of different
materials.
22. A semiconductor die assembly according to claim 17, wherein the
heat conductivity of the first material of said die paddle is
different than that of the second material of said lead frame.
23. A semiconductor die assembly according to claim 17, wherein the
first material of said die paddle is different than the second
material of said lead frame.
24. A semiconductor die assembly according to claim 17, wherein the
electrical conductivity of the second material of said lead frame
is different than that of the first material of said die
paddle.
25. A semiconductor die assembly according to claim 17, wherein the
electrical conductivity of the second material of said lead frame
is different than that of the material of said tie bar.
26. A semiconductor die assembly according to claim 17, further
including an insulating film, said insulating film covering a
portion of said active surface of said semiconductor die.
27. A semiconductor die assembly according to claim 17, wherein
said interconnection includes a wire bond.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No.
11/351,165, filed Feb. 9, 2006, pending, which is a divisional of
application Ser. No. 11/137,034, filed May 25, 2005, pending, which
is a continuation of application Ser. No. 10/443,468, filed May 22,
2003, now U.S. Pat. No. 6,946,722, issued Sep. 20, 2005, which is a
continuation of application Ser. No. 09/441,524, filed Nov. 16,
1999, now U.S. Pat. No. 6,570,244, issued May 27, 2003, which is a
continuation of application Ser. No. 08/738,308, filed Oct. 25,
1996, now U.S. Pat. No. 6,072,228, issued Jun. 6, 2000.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a molded semiconductor
device and a method for fabricating the same. More particularly,
the present invention relates to a semiconductor device assembly
utilizing a multi-part lead frame having dissimilar materials and
the method for fabricating the same. The multi-part lead frame can
be used for a wide variety of types of lead frames, such as
modified conventional lead frames, leads-over-chip (LOC) lead
frames, hybrid lead frames, etc.
[0004] 2. State of the Art
[0005] Conventional, well-known molded semiconductor devices are
constructed by assembling and interconnecting a semiconductor
device to a lead frame and molding the structure in plastic. In a
"conventional" or "traditional" type of lead frame construction, a
lead frame is made from a metal ribbon, with each lead frame
including a paddle (also known as a die paddle, die-attach tab, or
island) for attaching a semiconductor device thereto and a
plurality of leads arranged such that the leads do not overlap the
paddle on which the semiconductor device is to be mounted.
[0006] In order to overcome inherent limitations created by the
size and bond pad arrangement of semiconductor device assemblies
using conventional types of lead frames, leads-over-chip (LOC)
semiconductor device assemblies have been employed. The LOC lead
frame configuration for a semiconductor device replaces the
conventional lead frame configuration with a lead frame
configuration having no die paddle and having lead fingers or leads
that extend over the active surface of the semiconductor device.
The semiconductor device is supported by being adhesively secured
to the lead fingers by means of a dielectric film disposed between
the undersides of a portion of the lead fingers and the
semiconductor device. Examples of assemblies implementing LOC lead
frame technology are disclosed in U.S. Pat. Nos. 5,184,208;
5,252,853; 5,286,679; 5,304,842; and 5,461,255. In some instances,
LOC lead frame assemblies employ additional quantities of adhesive
to enhance physical support of the semiconductor device for
handling.
[0007] Traditional lead frame semiconductor device assemblies have
a semiconductor device attached to a die paddle of the lead frame.
The die paddle having a semiconductor device attached thereto is
located adjacent the inner ends of the lead fingers of the lead
frame so that the inner ends of the lead fingers are in close
lateral proximity to the bond pads located at the periphery of the
active surface of the semiconductor device. Wire bonds are formed
between the inner ends of the lead fingers and the bond pads on the
periphery of the semiconductor device.
[0008] In contrast, LOC lead frame assemblies have lead fingers of
the lead frame extending over the active surface of the
semiconductor device and adhesively attached thereto. This permits
physical support of the semiconductor device from the lead fingers
themselves, permits more diverse placement of the bond pads on the
active surface of the semiconductor device, and permits the use of
the lead fingers for heat transfer from the semiconductor device.
However, use of LOC lead frame assemblies in combination with
plastic packaging of the LOC lead frame assembly has demonstrated
some shortcomings of LOC technology and economics.
[0009] After wire bonding the semiconductor device to the lead
fingers of the lead frame forming an assembly, the most common
manner of forming a plastic package about a semiconductor device
assembly is transfer molding. In the transfer molding of a LOC type
lead frame and semiconductor device assembly, a semiconductor
device, which is adhesively suspended by its active surface from
the lead fingers of a LOC lead frame and has the bond pads of the
semiconductor device and the inner ends of lead fingers of the lead
frame connected by wire bonds, is placed in a mold cavity and
molded in a thermosetting polymer to form a highly cross-linked
matrix.
[0010] One of the technological shortcomings of the prior art LOC
semiconductor device assemblies is that the adhesive tape used to
bond to the lead fingers of the lead frame does not adequately lock
the lead fingers in position. In some instances, the adhesive on
the tape is not strong enough to lock the lead fingers in position
for wire bonding, as the lead fingers may pull away from the tape
before wire bonding. Alternately, the lead fingers may pull away
from the tape after wire bonding of the semiconductor device but
before molding of the semiconductor device and LOC lead frame,
thereby either causing shorts between adjacent wire bonds or the
wire bonds to pull loose from either the bond pads of the
semiconductor device or the lead fingers of the lead frame. With
respect to economic considerations, a cost reduction can be
realized by replacing the more expensive adhesives and tapes used
in the LOC lead frame and semiconductor device assembly with a
lower cost lead frame having characteristics of both a conventional
type lead frame configuration and a LOC type lead frame
configuration.
[0011] An alternative type lead frame to a LOC lead frame and
semiconductor device assembly is disclosed in U.S. Pat. No.
4,984,059 to Kubota et al. In this alternative type lead frame and
semiconductor device assembly, two metal lead frames are used. A
die paddle, onto which a semiconductor device is subsequently
attached, is formed between the longitudinal sides of a first lead
frame. A second lead frame is formed having lead fingers extending
between the longitudinal sides thereof. An assembly is formed by
welding the first lead frame having a semiconductor device attached
to the die paddle to the second lead frame having the lead fingers
thereof extending over the active surface of the semiconductor
device. The welding is accomplished by welding cradles running
along the two longitudinal sides of each lead frame. Alignment of
the two lead frames is accomplished by matching alignment holes
found on the cradles with alignment holes in the longitudinal sides
of each lead frame. The double lead frame assembly thus eliminates
the need for tapes or adhesives as a means to support the die from
the lead fingers themselves, as the semiconductor device is
supported by the die paddle of the first lead frame. In an
alternative arrangement, the '059 Patent discloses a semiconductor
device that is attached to a die paddle having arms extending
therefrom with the arms of the die paddle being attached to
receiving portions of a lead frame having a plurality of leads
formed therewith. However, use of either double lead frame
assemblies or separately formed die paddles subsequently attached
to receiving portions of a lead frame in combination with a molded
packaging lead frame assembly so formed has demonstrated
shortcomings in terms of technology and economics.
[0012] One such shortcoming involves the manufacturing area. In the
molding process, the double lead frame process requires molds
specifically adapted for receiving two lead frames. Thus, in order
to practice the double lead frame process, existing "single lead
frame" equipment must be replaced.
[0013] Another shortcoming affects the design and reliability of
the packaged semiconductor device. The double lead frame assemblies
disclosed in the prior art are limited to use of metal ribbons of
the same material to form both lead frame structures.
[0014] A shortcoming of the separately formed die paddle
subsequently attached to receiving portions of a lead frame is that
the separately formed die paddle is difficult to handle and to
accurately attach to the lead frame, thereby creating wire bonding
problems between the leads of the lead frame and the bond pads of
the semiconductor device.
[0015] However, designing double lead frame assemblies that utilize
different metallic and/or non-metallic materials to fabricate the
two lead frames allows packaging and operational advantages.
Materials can be selected which closely match either the mold
compound properties, the semiconductor device properties, or both,
in order to capitalize on a desired effect or characteristic (e.g.,
fabricating a die paddle with A-42 type alloy material to deal with
thermal expansion and fabricating the lead frame with copper
material to increase speed of transmission). Additionally,
packaging advantages can be realized by using materials of
different thicknesses to obtain desired effects, such as
conservation of space, to form smaller packages or increased heat
dissipation from the package. Furthermore, desirable
characteristics of different types of lead frames may be combined
into double lead frame assemblies, particularly where the
semiconductor device is accurately located with respect to the lead
frame.
[0016] From the foregoing, the prior art has neither provided a
multilayer molded semiconductor device package that is fabricated
through conventional single lead frame assembly and molding
processes, nor has it provided for use of dissimilar lead frame
materials to fabricate a multilayer molded plastic semiconductor
device package.
BRIEF SUMMARY OF THE INVENTION
[0017] The present invention provides a multi-part lead frame and
semiconductor device assembly which includes a die paddle, the
multi-part lead frame being separately formed and assembled from
dissimilar or separate materials, if desired. The use of separate
or different materials for the lead fingers of the lead frame and
die paddle provides packaging and operational advantages through
the availability of a variety of materials which can be selected to
closely match the mold compound and semiconductor device
properties. Another advantage of the present invention is to
provide a semiconductor device assembly fabricated from less
expensive materials than those currently being used.
[0018] These and other advantages of the present invention are
accomplished by a semiconductor device or die assembly that
includes a semiconductor device having an active surface having, in
turn, a plurality of bond pads formed thereon and a lead frame
assembly including a first lead frame and a second lead frame. The
first lead frame includes a die paddle onto which the semiconductor
device is attached, first carriers and tie bars connecting the die
paddle to the carriers of the lead frame. The first carriers are
usually vertically spaced from the die paddle, such that the die
paddle is located in a horizontal plane below the first carriers,
so that when the semiconductor device or die is mounted on the die
paddle, the active surface of the semiconductor die is located in
substantially the same horizontal plane as the first carriers. The
second lead frame of the lead frame assembly includes a plurality
of lead fingers extending inwardly from second carriers having
second alignment holes therein, each lead finger of the plurality
of lead fingers including an inner lead portion and an outer lead
portion secured to a carrier. The inner lead portion of each lead
finger is located in a predetermined location with respect to the
bonds pads on the active surface of a semiconductor device attached
to the die paddle of the first lead frame after portions of the
first and second lead frames have been joined. The inner lead
portion of each lead finger is also horizontally spaced at a
predetermined location from the bond pads located on the active
surface of the semiconductor device attached to the die paddle of
the first lead frame after portions of the first and second lead
frames have been joined. Wire bonds interconnect the inner lead
portion of each lead finger and the bond pads of the semiconductor
device or die. The second lead frame further includes tab receiving
portions for securing or attaching portions of tie bars of the
first lead frame to the second lead frame.
[0019] The present invention further includes a method of
fabricating a semiconductor device. In accordance with the method
of the present invention, a semiconductor device having an active
surface having, in turn, bond pads formed thereon is used. Also
used in the method of the present invention is a first lead frame
including a die paddle, first carriers having alignment holes
therein, and tie bars having cut zones and tabs therein. The tie
bar interconnects the die paddle and first carriers. The
semiconductor device is attached to the die paddle. Next, a second
lead frame having second carriers and a plurality of lead fingers
is used in the method of the present invention. The second carriers
of the second lead frame include tab receiving portions affixed
thereto and second alignment members. The first and second lead
frames are aligned by aligning the plurality of first alignment
members and second alignment members together. The first and second
lead frames are then joined by securing the tabs of the first lead
frame to the tab receiving portions of the second lead frame. The
tie bars are then cut at a point between the tabs and the first
carriers and the first carriers are discarded. Finally, the inner
lead ends of the lead fingers and the bond pads of the
semiconductor device are interconnected with wire bonds.
[0020] The semiconductor device assembly of the present invention
permits the use of "single lead frame" equipment through all
existing manufacturing steps instead of replacing existing
equipment for a so called "double lead frame" process.
[0021] The semiconductor device assembly may be molded into the
desired package using conventional apparatus and methods.
[0022] Securing of the first and second lead frames (or portions
thereof) may be accomplished by welding, adhesive bonding, or any
other suitable method of bonding.
[0023] The lead frame configuration of the present invention may be
a conventional type, a LOC type, a hybrid type, etc.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0024] While the specification concludes with claims particularly
pointing out and distinctly claiming that which is regarded as the
present invention, the advantages of this invention can be more
readily ascertained from the following description of the invention
when read in conjunction with the accompanying drawings in
which:
[0025] FIG. 1a is a plan view of a prior art assembly of a
semiconductor device before molding;
[0026] FIG. 1b is a sectional view along lines IB-IB in FIG.
1a;
[0027] FIG. 1c is a plan view of a prior art assembly semiconductor
device before molding;
[0028] FIG. 2 is a cross-sectional view of a mold used in
encapsulating a prior art assembly;
[0029] FIG. 3 is a plan view of a first lead frame and die
paddle;
[0030] FIG. 4 is a sectional view of the first lead frame and die
paddle of FIG. 3;
[0031] FIG. 5 is a plan view of a semiconductor device;
[0032] FIG. 6 is a plan view of a second lead frame;
[0033] FIGS. 7a to 7f are diagrams for explaining a manufacturing
process of a semiconductor device according to a first embodiment
of the present invention;
[0034] FIG. 8 is a cross-sectional view of a mold including the
assembly according to a first embodiment of the present
invention;
[0035] FIG. 9 is a cross-sectional view of a further semiconductor
device according to the present invention;
[0036] FIG. 10 is a plan view of another semiconductor device;
[0037] FIG. 11 is a plan view of a second embodiment of the first
lead frame of the present invention;
[0038] FIG. 12 is a plan view of a second embodiment of the second
lead frame of the present invention; and
[0039] FIG. 13 is a plan view of the semiconductor device assembled
with the first and second lead frames of the second embodiment of
the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0040] For a better understanding of the present invention, the
prior art is described with reference to drawing FIGS. 1a, 1b, 1c
and 2. FIGS. 1a, 1b, and 1c illustrate a prior art device in which
two metal lead frames are used for fabricating a semiconductor
device. FIGS. 1a and 1b (taken along line IB-IB of FIG. 1a)
illustrate a die paddle 4 that is formed as part of a first lead
frame 2 and that is tied to carriers 6 with tie bars 8. The first
lead frame 2 comprises carriers 6 running along two longitudinal
sides of the first lead frame itself. The second lead frame 12 is
provided with alignment holes 10. The carriers 6 are bent to
differentiate the levels of the die paddle 4 in relation to the
ends of the carriers 6.
[0041] FIG. 1c illustrates a second lead frame 12 comprising
carriers 16 running along two longitudinal sides of the second lead
frame itself. The second lead frame 12 is provided with alignment
holes 14, a plurality of leads 18 consisting of an inner lead
portion 18a and an outer lead portion 18b, and dam bars 20 tying
the leads 18 to each other and to the carriers 16.
[0042] In the fabrication of a semiconductor device, referring to
drawing FIGS. 1a, 1b, 1c, and 2 (which illustrate a mold used in
the double lead frame assembly process), a semiconductor device 22
is bonded onto the die paddle 4. An insulating film 24 may be
bonded onto the top surface of the die paddle 4 to insulate the
semiconductor device 22. The inner lead portions 18a of second lead
frame 12 are connected to an active surface of semiconductor device
22 by means of wire bonding 28. First lead frame 2 is then fixed to
second lead frame 12 by welding a portion of the carrier 6 of first
lead frame 2 to a portion of the carrier 16 of second lead frame
12. This particular assembly requires a particular mold adopted for
receiving two lead frames, as illustrated in FIG. 2. As can be seen
from FIG. 2, a mold 26 comprising an upper half 26a and a lower
half 26b holds carriers 6 and 16 of lead frames 2 and 12,
respectively.
[0043] An alternative embodiment of the prior art device shown in
drawing FIGS. 1a, 1b, 1c, and 2 comprises the same assembly steps
described before, except that die paddle 4 is not formed as part of
a first lead frame 2. Instead, die paddle 4 and tie bars 8 are
welded directly onto a tie-receiving portion formed on the second
lead frame 12. Due to the exclusion of the carrier 6 and alignment
holes 10 of first lead frame 2, this alternative embodiment
requires specialized equipment to locate, align and weld the tie
bars 8 to the tie-receiving portion of the alternative second lead
frame 12.
[0044] In contrast to the prior art, FIGS. 3 and 4 illustrate a
first embodiment of a first lead frame 30 according to the present
invention. The first lead frame 30 is made from any metallic
material, non-metallic material, or any combinations thereof, which
exhibit desirable properties with respect to, for example, thermal
conductivity, coefficient of thermal expansion, heat dissipation,
strength, and formability. Well known examples of such materials
(used alone or in combination) include A-42 type alloy, copper,
aluminum, silver, ceramic compounds, organic and inorganic silicone
based compounds, plastic compounds, and glass-epoxy based organic
materials, reinforced organic materials, etc.
[0045] Referring to FIG. 3, the first lead frame 30 comprises first
carriers 32 running along the two longitudinal sides of the first
lead frame and further is provided with alignment holes 34 thereon.
A die paddle 36 is connected to first carriers 32 by means of tie
bars 38. The die paddle 36 has sufficient length and width to
easily accommodate semiconductor chips or dice of varying sizes and
shapes. Tie bar cut zones 40 and attachment tabs 42 are provided on
tie bars 38 for use in assembling the semiconductor device, as more
fully set forth below (see FIGS. 7a to 7f). Attachment tabs 42
consist of co-planar extensions emanating from the tie bars, each
attachment tab 42 being substantially larger and/or wider than the
tie bar 38 to which the attachment tab 42 is connected, although
the attachment tab 42 may be any desired size and/or configuration
suitable for use. Tie bar cut zones 40 consist of preweakened,
cutaway or recessed portions located between the attachment tabs 42
and the first carriers 32 on the tie bars 38. As can be seen from
FIG. 4, the tie bars 38 are bent downwardly, so as to position the
die paddle 36 in a substantially horizontal arrangement with and at
a lower level in relation to the first carriers 32 and first lead
frame 30. Because the degree of pitch in the bend, as well as the
length and width of the tie bars 38, is dependent on the height of
the semiconductor chip or die to be placed on the die paddle 36,
the tie bars 38 will correspondingly vary with regard to shape and
angle of bend in order to accommodate a wide variety of
semiconductor device shapes and sizes. Inclusion of first carriers
32 and alignment holes 34 permit the use of existing equipment used
in single lead frame processes to accomplish the attachment of the
semiconductor device 44 (FIG. 5) onto the die paddle 36.
[0046] FIG. 5 illustrates a semiconductor device 44 having bond
pads 46 placed in a linear arrangement on an active surface of the
semiconductor device 44. It is understood that any semiconductor
device having various arrangements of bond pads known in the art
can be used. It will also be understood that the semiconductor
device 44 is not limited with respect to length, width, thickness,
or material composition.
[0047] FIG. 6 illustrates a second lead frame 48 according to the
present invention. The second lead frame 48 comprises second
carriers 50 running along the two longitudinal sides of the second
lead frame 48, alignment holes 52, a plurality of leads 54
consisting of an inner lead portion 54a and an outer lead portion
54b, dam bars 56 tying the leads 54 to each other and to second
carriers 50, and attachment tab receiving portions 58 having
apertures 58' therein. Each attachment tab receiving portion 58 is
formed being of substantially the same size and shape as the
attachment tab 42, or at least as large and substantially the same
shape with which it is to be attached, although the attachment tab
42 and attachment tab receiving portion 58 to which it is attached
may have any suitable desired size and shape depending upon the
geometry and size of the semiconductor device, the die paddle, and
the lead frame. The second lead frame 48 can be made from any
metallic material, non-metallic material, or any combinations
thereof which exhibit desirable properties with respect to, for
example, electrical conductivity, coefficient of thermal expansion,
strength, and formability which are compatible with, although
preferably a different or separate material from, the first lead
frame 30, but yet compatible therewith and with the semiconductor
device 44. Well known examples of such materials (used alone or in
combination) include, but are not limited to, A-42 type alloy,
copper, aluminum, and silver. Attachment tab receiving portions 58,
having apertures 58' therein, preferably consist of co-planar, flat
extensions of the second carriers 50.
[0048] Alignment holes 34 and 52 can be formed in a variety of
shapes and positions with the purpose of accommodating particular
types of equipment used both to align and weld the first lead frame
30 to the second lead frame 48, as further described below.
Alignment holes 34 and 52 preferably consist of uniformly shaped,
extruded sections of first and second carriers 32 and 50.
[0049] FIGS. 7a to 7f illustrate a method of fabricating a
semiconductor device according to the present invention. Referring
to FIG. 7a, the semiconductor device 44 is attached or bonded onto
the die paddle 36 of the first lead frame 30 using a conventional
single lead frame process and equipment. As previously described,
the first lead frame will comprise a die paddle 36 of sufficient
size and sufficient depth (in relation to the first carriers 32) to
accommodate a preselected semiconductor chip of a particular
length, height, and width. The semiconductor device 44 can be
bonded onto the die paddle 36 with, for example, silver paste,
polyamide, or any other means of bonding known in the art. An
insulating film (e.g., silicon tape or polyamide) can be applied to
the top or active surface of the semiconductor device 44, excluding
the electrodes or bond pads 46, to electrically and physically
insulate the semiconductor device 44 against damage resulting from
direct contact with leads 54 during a subsequently described wire
bonding process. Referring to FIGS. 7b and 7c, once the
semiconductor device 44 has been bonded to the die paddle 36, the
first and second lead frames are aligned by superimposing a bottom
surface of the second lead frame 48 onto a top surface of the first
lead frame 30 and by aligning alignment holes 34 of first lead
frame 30 with the corresponding alignment holes 52 of the second
lead frame 48. In the resulting alignment, the inner lead portions
54a of the second lead frame 48 overlap the semiconductor device
44. The attachment tabs 42 of the first lead frame 30 are then
attached or welded or bonded to the attachment tab receiving
portions 58 of the second lead frame 48. It is understood that any
suitable adhering or welding processes known in the art, such as
spot welding, heat pressure welding, adhesive taping, polyamide
bonding, etc. can be used. A cross-sectional view of the assembled
and interconnected dual lead frame structure is illustrated in FIG.
7c.
[0050] Referring to FIGS. 7d and 7e, once the alignment and
adhering steps are completed, the first carriers 32 of the first
lead frame 30 are removed from the die paddle 36, tie bars 38, and
attachment tabs 42 by severing or cutting the tie bar cut zones 40
(shown in FIGS. 3 and 7b) of the first lead frame 30, using any
suitable severing or cutting tool that can extend through apertures
58N of attachment tab receiving portion 58 in the second lead frame
48. The first carriers 32 of the first lead frame 30 are discarded,
leaving an intact second lead frame 48 including a die paddle 36
which is connected to the attachment tab receiving portion 58 of
the second lead frame 48 by means of the tie bars 38 and attachment
tabs 42. Thus, the present step in the method converts the double
lead frame assembly of the prior "align and weld" step into a
single lead frame assembly in order to facilitate the use of
conventional single lead frame equipment in conducting the
subsequent wire bonding step of the assembly process. A
cross-sectional view of the assembled and interconnected single
lead frame structure with attached die paddle 36 is illustrated in
FIG. 7e.
[0051] As illustrated in FIG. 7f, the bond pads 46 of the
semiconductor device 44 and the inner lead portions 54a of the
leads 54 are then interconnected by any suitable means of wire
bonds 60 (e.g., gold wire bonding).
[0052] FIG. 8 illustrates a cross-sectional view of a conventional
mold, adapted for receiving a single lead frame, and the single
lead frame assembly of FIG. 7f. Upon completion of the wire bonding
stage, the assembled and interconnected single lead frame structure
including: the second lead frame 48, the die paddle 36, the
semiconductor device 44, and the wire bonds 60 are set in a
transfer mold 66, which comprises an upper half 66a and a lower
half 66b. The mold 66 includes a mold space having a portion
thereof running along the dam bars 56 (not shown in FIG. 8) and
near the second carriers 50 of the second lead frame 48, as
illustrated by dotted line 62 in FIG. 7f. Thus, the mold space
containing the portion of the assembly comprising the die paddle
36, the semiconductor device 44, the inner lead portions 54a of the
leads 54, and the wire bonds 60, is then filled with a
thermosetting polymer such as, for example, an epoxy resin. Upon
completion of the molding process, the second carriers 50 and
sections of the dam bars 56 located between leads 54 of the second
lead frame 48 are removed, so as to separate the molded body and
the outer lead portions 54b and form a molded semiconductor device
assembly. Such removal can be accomplished with a press or other
known suitable means. Subsequent steps may include bending of the
outer lead portions 54b, metal plating, and any other desired
conventional steps.
[0053] FIG. 9 illustrates a further embodiment of the present
invention in which die paddles of differing thicknesses are
employed to assist in dissipation of heat via heat conduction.
Usually, heat generated in operation of the semiconductor device is
dissipated via heat conduction through leads to a circuit board and
into portions of the molded package itself. Heat dissipation can be
improved by diffusing the generated heat in a direction away from
the semiconductor device and toward one or more external surfaces
of the package. As previously discussed, one method of improving
heat dissipation is through the selection of die paddle materials
having an optimum quality for heat conduction. However, such
limitations are avoided in the lead frame assembly of the present
invention through the use of dissimilar materials in the
manufacture of the first and second lead frames.
[0054] The embodiment illustrated in FIG. 9 also differs from the
embodiment of FIG. 8 in that the inner lead portions 54a of the
leads 54 do not overlap or extend over the active surface of the
semiconductor device 44. It is understood that the inner lead
portions 54a of the leads 54 can be of varying lengths, so as to
permit any desired overlap of the die paddle 36, semiconductor
device 44, or neither, i.e., no overlap of the active surface of
the semiconductor device at all (as demonstrated in the present
examples).
[0055] As previously stated, FIG. 9 illustrates another embodiment
of the present invention in which a die paddle 36 is used as a heat
sink, the die paddle 36 having a thickness sufficient that the
bottom surface thereof contacts, if desired, a portion of the mold
die forming the mold space. In operation, heat generated in a
semiconductor device 44 is dissipated through the leads connected
thereto, the thermosetting polymer forming the semiconductor die
package, and the semiconductor die paddle.
[0056] The preferred heat sinks for use in the present invention
comprise laminated metal sandwiches commonly referred to as
copper-clad Invar and copper-clad molybdenum.
[0057] FIG. 10 illustrates a semiconductor device 144 having bond
pads 146 placed in a linear arrangement on two opposing sides on
the active surface of the semiconductor device 144. It is
understood that any semiconductor device having various
arrangements of bond pads known in the art can be used. It will
also be understood that the semiconductor device 144 is not limited
with respect to length, width, thickness, or material
composition.
[0058] Referring to FIG. 11, the first lead frame 130 of a second
embodiment of the present invention comprises first carriers 132
running along the two longitudinal sides of the first lead frame
and further is provided with alignment holes 134 thereon. A die
paddle 136 is connected to first carriers 132 by means of tie bars
138. The die paddle 136 has sufficient length and width to easily
accommodate semiconductor chips or dice of varying sizes and
shapes. Tie bar cut zones 140 and attachment tabs 142 are provided
on tie bars 138 for use in assembling the semiconductor device as
described hereinbelow. Attachment tabs 142 consist of co-planar
extensions emanating from the tie bars, each attachment tab 142
being substantially larger and/or wider than the tie bar 138 to
which the attachment tab 142 is connected, although the attachment
tab 142 may be any desired size and/or configuration suitable for
use. Tie bar cut zones 140 consist of preweakened, cutaway or
recessed portions located between the attachment tabs 142 and the
first carriers 132 on the tie bars 138. As previously described
hereinbefore, the tie bars 138 are bent downwardly, so as to
position the die paddle 136 in a substantially horizontal
arrangement with and at a lower level in relation to the first
carriers 132 and first lead frame 130. Because the degree of pitch
in the bend, as well as the length and width of the tie bars 138,
are dependent on the height of the semiconductor chip or die to be
placed on the die paddle 136, the tie bars 138 will correspondingly
vary with regard to shape and angle of bend in order to accommodate
a wide variety of semiconductor device shapes and sizes. Inclusion
of first carriers 132 and alignment holes 134 permit the use of
existing equipment used in single lead frame processes to
accomplish the attachment of the semiconductor device 144 onto the
die paddle 136.
[0059] FIG. 12 illustrates a second lead frame 148 according to a
second embodiment of the present invention. The second lead frame
148 comprises second carriers 150 running along the two
longitudinal sides of the second lead frame 148, alignment holes
152, a plurality of leads 154 consisting of an inner lead portion
154a, which does not overlap the die paddle or the active surface
of a semiconductor device, and an outer lead portion 154b, dam bars
156 tying the leads 154 to each other and to second carriers 150,
and attachment tab receiving portions 158 having apertures 158N
therein. Each attachment tab receiving portion 158 is formed being
of substantially the same size and shape as the attachment tab 142,
or at least as large and substantially the same shape with which it
is to be attached although the attachment tab 142 and attachment
tab receiving portion 158 to which it is attached may have any
suitable desired size and shape, depending upon the geometry and
size of the semiconductor device, the die paddle, and the lead
frame. The second lead frame 148 can be made from any metallic
material, non-metallic material, or any combinations thereof, which
exhibit desirable properties with respect to, for example,
electrical conductivity, coefficient of thermal expansion,
strength, and formability which are compatible with, although
preferably a different or separate material from, the first lead
frame 130, but yet compatible therewith and with the semiconductor
device 144. Well known examples of such materials (used alone or in
combination) include, but are not limited to, A-42 type alloy,
copper, aluminum, and silver. Attachment tab receiving portions 158
having apertures 158' therein preferably consist of co-planar, flat
extensions of the second carriers 150.
[0060] Alignment holes 134 and 152 can be formed in a variety of
shapes and positions with the purpose of accommodating particular
types of equipment used both to align and weld the first lead frame
130 to the second lead frame 148, as further described below.
Alignment holes 134 and 152 preferably consist of uniformly shaped
extruded sections of first and second carriers 132 and 150.
[0061] FIG. 13 illustrates the assembled first lead frame 130 and
second lead frame 148 according to the second embodiment of the
present invention. The semiconductor device 144 is attached or
bonded onto the die paddle 136 of the first lead frame 130 using a
conventional single lead frame process and equipment. As previously
described, the first lead frame will comprise a die paddle 136 of
sufficient size and sufficient depth (in relation to the first
carriers 132) to accommodate a preselected semiconductor chip of a
particular length, height, and width. The semiconductor device 144
can be bonded onto the die paddle 136 with, for example, silver
paste, polyamide, or any other means of bonding known in the art.
Once the semiconductor device 144 has been bonded to the die paddle
136, the first and second lead frames 130, 148 are aligned by
superimposing a bottom surface of the second lead frame 148 onto a
top surface of the first lead frame 130 and by aligning alignment
holes 134 of lead frame 130 with the corresponding alignment holes
152 of the second lead frame 148. In the resulting alignment, the
inner lead portions 154a of the second lead frame 148 extend
adjacent two of the edges of the semiconductor device 144. The
attachment tabs 142 of the first lead frame 130 are then attached
or welded or bonded to the attachment tab receiving portions 158 of
the second lead frame 148. It is understood that any suitable
adhering or welding processes known in the art, such as spot
welding, heat pressure welding, adhesive taping, polyamide bonding,
etc., can be used. Once the alignment and adhering steps are
completed, the first carriers 132 of the first lead frame 130 are
removed from the die paddle 136, tie bars 138, and attachment tabs
142 by severing or cutting the tie bar cut zones 140 using any
suitable severing or cutting tool which can extend through
apertures 158N of attachment tab receiving portion 158 in the
second lead frame 148. The first carriers 132 of the first lead
frame 130 are discarded, leaving an intact second lead frame 148
including a die paddle 136 which is connected to the attachment tab
receiving portion 158 of the second lead frame 148 by means of the
tie bars 138 and attachment tabs 142. Thus, the present step in the
method converts the double lead frame assembly of the prior "align
and weld" step into a single lead frame assembly in order to
facilitate the use of conventional single lead frame equipment in
conducting the subsequent wire bonding step of the assembly
process. Next, the inner lead portions 154a are subsequently
connected by wires 200 to the appropriate bond pads 146 on the
active surface of the semiconductor device 144. The wires 200 may
be bonded to the inner lead portions 154a and bond pads 146 by any
suitable means, such as wire bonding.
[0062] It will be understood that changes, additions, deletions,
and modifications as described hereinbefore may be made to the
present invention which fall within the scope thereof.
* * * * *