U.S. patent application number 11/486596 was filed with the patent office on 2006-11-16 for nand memory arrays.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Todd R. Abbott, Garo Derderian, Michael Violette.
Application Number | 20060258093 11/486596 |
Document ID | / |
Family ID | 35910134 |
Filed Date | 2006-11-16 |
United States Patent
Application |
20060258093 |
Kind Code |
A1 |
Violette; Michael ; et
al. |
November 16, 2006 |
NAND memory arrays
Abstract
A NAND memory array has a first dielectric layer formed on a
first portion of a semiconductor substrate and a second dielectric
layer formed on a second portion of the semiconductor substrate and
adjoining the first dielectric layer. The first dielectric layer is
thicker than the second dielectric layer. A first gate stack is
formed on the first dielectric layer to form a drain select gate. A
string of second gate stacks is formed on the second dielectric
layer to form a NAND string of floating-gate memory cells. A first
end of the NAND string is coupled in series with the drain select
gate. A third gate stack is formed on the second dielectric layer
to form a source select gate. A second end of the NAND string is
coupled in series with the source select gate.
Inventors: |
Violette; Michael; (Boise,
ID) ; Derderian; Garo; (Boise, ID) ; Abbott;
Todd R.; (Boise, ID) |
Correspondence
Address: |
LEFFERT JAY & POLGLAZE, P.A.
P.O. BOX 581009
MINNEAPOLIS
MN
55458-1009
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
35910134 |
Appl. No.: |
11/486596 |
Filed: |
July 14, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10920561 |
Aug 18, 2004 |
|
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11486596 |
Jul 14, 2006 |
|
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Current U.S.
Class: |
438/257 ;
257/E21.691; 257/E27.103 |
Current CPC
Class: |
H01L 27/115 20130101;
Y10S 438/981 20130101; H01L 27/11529 20130101; G11C 16/0483
20130101; H01L 27/11526 20130101 |
Class at
Publication: |
438/257 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Claims
1. A NAND memory array, comprising: at least one NAND string of
floating gate memory cells comprising: a first dielectric layer
formed on a first portion of a semiconductor substrate; a second
dielectric layer formed on a second portion of the semiconductor
substrate and adjoining the first dielectric layer, wherein the
first dielectric layer is thicker than the second dielectric layer;
a first gate stack formed on the first dielectric layer to form a
drain select gate; a string of second gate stacks formed on the
second dielectric layer to form the at least one NAND string of
floating-gate memory cells, a first end of the at least one NAND
string coupled in series with the drain select gate; and a third
gate stack formed on the second dielectric layer to form a source
select gate, a second end of the at least one NAND string coupled
in series with the source select gate.
2. The NAND memory array of claim 1, wherein the source and drain
select gates and the at least one NAND string form a column of the
memory array.
3. The NAND memory array of claim 1, wherein the drain select gate
and a first memory cell at the first end of the at least one NAND
string share a first source/drain region formed in the substrate
and the source select gate and a second memory cell at the second
end of the at least one NAND string share a second source/drain
region formed in the substrate.
4. The NAND memory array of claim 1, wherein the drain select gate
further comprises a drain select line formed on the first
dielectric layer, the source select gate further comprises a source
select line formed on the second dielectric layer, and each of the
memory cells further comprises a floating gate formed on the second
dielectric layer, an intergate dielectric layer formed on the
floating gate, and a word line formed on the intergate dielectric
layer.
5. The NAND memory array of claim 1, wherein each of the memory
cells and the select gate further comprise a first conductive layer
formed on the second dielectric layer, a third dielectric layer
formed on the first conductive layer, and a second conductive layer
formed on the third dielectric layer, and wherein the drain select
gate comprises the first conductive layer formed on the first
dielectric layer, the third dielectric layer formed on the first
conductive layer, and the second conductive layer formed on the
third dielectric layer.
6. The NAND memory array of claim 5, wherein the first conductive
layer is a polysilicon layer.
7. The NAND memory array of claim 6, wherein the polysilicon layer
is conductively doped.
8. The NAND memory array of claim 5, wherein the second conductive
layer is selected from the group consisting of a polysilicon layer,
a metal layer, a metal-containing layer, a layer containing one or
more conductive materials, and one or more conductive layers.
9. The NAND memory array of claim 5, wherein the third dielectric
layer comprises one or more layers of dielectric material.
10. The NAND memory array of claim 1, wherein each of the first and
second dielectric layers are oxide layers.
11. The NAND memory array of claim 1, wherein the second dielectric
layer is nitrided.
12. A NAND memory array comprising: a plurality of rows of memory
cells; and a plurality of columns of NAND strings of memory cells,
each NAND string selectively connected to a bit line through a
drain select gate of the respective column; wherein each of the
drain select gates comprises a first dielectric layer formed on a
semiconductor substrate of the memory array and a control gate
formed on the first dielectric layer; and wherein each of the
memory cells of each of the NAND strings comprises a second
dielectric layer formed on the substrate laterally of the first
dielectric layer and adjoining the first dielectric layer, a
floating gate formed on the second dielectric layer, a third
dielectric layer formed on the floating gate, and a control gate
formed on the third dielectric layer, wherein the first dielectric
layer is thicker than the second dielectric layer.
13. The NAND memory array of claim 12, wherein the first and second
dielectric layers are thermal oxide layers.
14. The NAND memory array of claim 12, wherein the second
dielectric layer is a nitride-containing thermal oxide layer.
15. A memory device, comprising: a memory array, comprising: a
plurality of rows of memory cells, the rows respectively connected
to corresponding word lines; and a plurality of columns, the
respective columns comprising a NAND string of memory cells
connected between a source select gate and a drain select gate,
each drain select gate selectively coupling the NAND string
connected thereto to a bit line; wherein each drain select gate
comprises a first gate stack formed on a first dielectric layer
formed on a substrate; wherein each of the memory cells of each of
the NAND strings comprises a second gate stack formed on a second
dielectric layer formed on the substrate laterally of the first
dielectric layer and adjoining the first dielectric layer; and
wherein each source select gate comprises a third gate stack formed
on the second dielectric layer; and column access circuitry
connected to the bit lines; and row access circuitry connected to
the word lines.
16. The memory device of claim 15, wherein the first gate stack
comprises a drain select line formed on the first dielectric layer,
the third gate stack comprises a source select line formed on the
second dielectric layer, and the second gate stack comprises a
floating gate formed on the second dielectric layer, an intergate
dielectric layer formed on the floating gate, and a control gate
formed on the intergate dielectric layer and connected to a word
line.
17. The memory device of claim 15, wherein the first and second
dielectric layers are thermal oxide layers.
18. The memory device of claim 15, wherein the second dielectric
layer is a nitride-containing thermal oxide layer.
19. An electronic system, comprising: a processor; and at least one
memory device coupled to the processor, the at least one memory
device comprising: a memory array, comprising: a plurality of rows
of memory cells, the rows respectively connected to corresponding
word lines; and a plurality of columns, the respective columns
comprising a NAND string of memory cells connected between a source
select gate and a drain select gate, each drain select gate
selectively coupling the NAND string connected thereto to a bit
line; wherein each drain select gate comprises a first gate stack
formed on a first dielectric layer formed on a substrate; wherein
each of the memory cells of each of the NAND strings comprises a
second gate stack formed on a second dielectric layer formed on the
substrate laterally of the first dielectric layer and adjoining the
first dielectric layer; and wherein each source select gate
comprises a third gate stack formed on the second dielectric layer;
and column access circuitry connected to the bit lines; and row
access circuitry connected to the word lines.
20. An electronic system, comprising: a processor; and at least one
memory device coupled to the processor, the at least one memory
device comprising: a memory array, comprising: a plurality of rows
of memory cells; and a plurality of columns of NAND strings of
memory cells, each NAND string selectively connected to a bit line
through a drain select gate of the respective column; wherein each
of the drain select gates comprises a first dielectric layer formed
on a semiconductor substrate of the memory array and a control gate
formed on the first dielectric layer; and wherein each of the
memory cells of each of the NAND strings comprises a second
dielectric layer formed on the substrate laterally of the first
dielectric layer and adjoining the first dielectric layer, a
floating gate formed on the second dielectric layer, a third
dielectric layer formed on the floating gate, and a control gate
formed on the third dielectric layer, wherein the first dielectric
layer is thicker than the second dielectric layer.
Description
RELATED APPLICATION
[0001] This Application is a Continuation of U.S. application Ser.
No. 10/920,561, titled "NAND MEMORY ARRAY AND METHODS," filed Aug.
18, 2004 (pending), which application is commonly assigned and
incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
[0002] The present invention relates generally to memory devices
and in particular the present invention relates to NAND memory
arrays and methods.
BACKGROUND OF THE INVENTION
[0003] Memory devices are typically provided as internal storage
areas in computers. The term memory identifies data storage that
comes in the form of integrated circuit chips. In general, memory
devices contain an array of memory cells for storing data, and row
and column decoder circuits coupled to the array of memory cells
for accessing the array of memory cells in response to an external
address.
[0004] One type of memory is a non-volatile memory known as flash
memory. A flash memory is a type of EEPROM (electrically-erasable
programmable read-only memory) that can be erased and reprogrammed
in blocks. Many modern personal computers (PCs) have their BIOS
stored on a flash memory chip so that it can easily be updated if
necessary. Such a BIOS is sometimes called a flash BIOS. Flash
memory is also popular in wireless electronic devices because it
enables the manufacturer to support new communication protocols as
they become standardized and to provide the ability to remotely
upgrade the device for enhanced features.
[0005] A typical flash memory comprises a memory array that
includes a large number of memory cells arranged in row and column
fashion. Each of the memory cells includes a floating-gate
field-effect transistor capable of holding a charge. The cells are
usually grouped into blocks. Each of the cells within a block can
be electrically programmed on an individual basis by charging the
floating gate. The charge can be removed from the floating gate by
a block erase operation. The data in a cell is determined by the
presence or absence of the charge on the floating gate.
[0006] A NAND flash memory device is a common type of flash memory
device, so called for the logical form in which the basic memory
cell configuration is arranged. Typically, the array of memory
cells for NAND flash memory devices is arranged such that the
control gate of each memory cell of a row of the array is connected
to a word-select line. Columns of the array include strings (often
termed NAND strings) of memory cells connected together in series,
source to drain, between a pair of select lines, a source select
line and a drain select line. The source select line includes a
source select gate at each intersection between a NAND string and
the source select line, and the drain select line includes a drain
select gate at each intersection between a NAND string and the
drain select line. The select gates are typically field-effect
transistors. Each source select gate is connected to a source line,
while each drain select gate is connected to a column bit line.
[0007] The memory array is accessed by a row decoder activating a
row of memory cells by selecting the word-select line connected to
a control gate of a memory cell. In addition, the word-select lines
connected to the control gates of unselected memory cells of each
string are driven to operate the unselected memory cells of each
string as pass transistors, so that they pass current in a manner
that is unrestricted by their stored data values. Current then
flows from the source line to the column bit line through each NAND
string via the corresponding select gates, restricted only by the
selected memory cells of each string. This places the
current-encoded data values of the row of selected memory cells on
the column bit lines.
[0008] To prevent programming of unselected strings while selected
strings are being programmed, the voltage level of the unselected
strings is increased. However, current leakage (often referred to
as gate-induced drain leakage or GIDL) through the drain select
gates acts to reduce the increased voltage level of the unselected
strings that can cause inadvertent programming of these strings and
can reduce programming speeds.
[0009] For the reasons stated above, and for other reasons stated
below which will become apparent to those skilled in the art upon
reading and understanding the present specification, there is a
need in the art for reducing current leakage from drain select
gates of unselected NAND strings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 is a simplified block diagram of a memory system,
according to an embodiment of the invention.
[0011] FIG. 2 is a schematic of a NAND memory array in accordance
with another embodiment of the invention.
[0012] FIGS. 3A-3F are cross-sectional views of a portion of a
memory array during various stages of fabrication, according to
another embodiment of the invention.
DETAILED DESCRIPTION
[0013] In the following detailed description of the invention,
reference is made to the accompanying drawings that form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention. The term wafer or substrate
used in the following description includes any base semiconductor
structure. Both are to be understood as including
silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)
technology, thin film transistor (TFT) technology, doped and
undoped semiconductors, epitaxial layers of a silicon supported by
a base semiconductor structure, as well as other semiconductor
structures well known to one skilled in the art. Furthermore, when
reference is made to a wafer or substrate in the following
description, previous process steps may have been utilized to form
regions/junctions in the base semiconductor structure, and terms
wafer or substrate include the underlying layers containing such
regions/junctions. The following detailed description is,
therefore, not to be taken in a limiting sense, and the scope of
the present invention is defined only by the appended claims and
equivalents thereof.
[0014] FIG. 1 is a simplified block diagram of a memory system 100,
according to an embodiment of the invention. Memory system 100
includes an integrated circuit flash memory device 102, e.g., a
NAND memory device, that includes an array of flash memory cells
104, an address decoder 106, row access circuitry 108, column
access circuitry 110, control circuitry 112, Input/Output (I/O)
circuitry 114, and an address buffer 116. Memory system 100
includes an external microprocessor 120, or memory controller,
electrically connected to memory device 102 for memory accessing as
part of an electronic system.
[0015] The memory device 102 receives control signals from the
processor 120 over a control link 122. The memory cells are used to
store data that are accessed via a data (DQ) link 124. Address
signals are received via an address link 126 that are decoded at
address decoder 106 to access the memory array 104. Address buffer
circuit 116 latches the address signals. The memory cells are
accessed in response to the control signals and the address
signals. It will be appreciated by those skilled in the art that
additional circuitry and control signals can be provided, and that
the memory device of FIG. 1 has been simplified to help focus on
the invention.
[0016] FIG. 2 is a schematic of a NAND memory array 200 as a
portion of memory array 104 in accordance with another embodiment
of the invention. As shown in FIG. 2, the memory array 200 includes
word lines 202.sub.1 to 202.sub.N and intersecting local bit lines
204.sub.1 to 204.sub.M. For ease of addressing in the digital
environment, the number of word lines 202 and the number of bit
lines 204 are each some power of two, e.g., 256 word lines 202 by
4,096 bit lines 204. The local bit lines 204 are coupled to global
bit lines (not shown) in a many-to-one relationship.
[0017] Memory array 200 includes NAND strings 206.sub.1 to
206.sub.M. Each NAND string includes floating-gate transistors
208.sub.1 to 208.sub.N, each located at an intersection of a word
line 202 and a local bit line 204. The floating-gate transistors
208 represent non-volatile memory cells for storage of data. The
floating-gate transistors 208 of each NAND string 206 are connected
in series source to drain between a source select line 214 and a
drain select line 215. Source select line 214 includes a source
select gate 210, e.g., a field-effect transistor (FET), at each
intersection between a NAND string 206 and source select line 214,
and drain select line 215 includes a drain select gate 212, e.g., a
field-effect transistor (FET), at each intersection between a NAND
string 206 and drain select line 215. In this way, the
floating-gate transistors 208 of each NAND string 206 are connected
between a source select gate 210 and a drain select gate 212.
[0018] A source of each source select gate 210 is connected to a
common source line 216. The drain of each source select gate 210 is
connected to the source of the first floating-gate transistor 208
of the corresponding NAND string 206. For example, the drain of
source select gate 210.sub.1 is connected to the source of
floating-gate transistor 208.sub.1 of the corresponding NAND string
206.sub.1. Each source select gate 210 includes a control gate
220.
[0019] The drain of each drain select gate 212 is connected to the
local bit line 204 for the corresponding NAND string at a drain
contact 228. For example, the drain of drain select gate 212.sub.1
is connected to the local bit line 204.sub.1 for the corresponding
NAND string 206.sub.1 at drain contact 228.sub.1. The source of
each drain select gate 212 is connected to the drain of the last
floating-gate transistor 208.sub.N of the corresponding NAND string
206. For example, the source of drain select gate 212.sub.1 is
connected to the drain of floating-gate transistor 208.sub.N of the
corresponding NAND string 206.sub.1.
[0020] Typical construction of floating-gate transistors 208
includes a source 230 and a drain 232, a floating gate 234, and a
control gate 236, as shown in FIG. 2. Floating-gate transistors 208
have their control gates 236 coupled to a word line 202. A column
of memory array 200 includes a NAND string 206 and the source and
drain select gates connected thereto. A row of the floating-gate
transistors 208 are those transistors commonly coupled to a given
word line 202.
[0021] FIGS. 3A-3F are cross-sectional views of a portion of a
memory array, such as a portion of the memory array 200 of FIG. 2,
during various stages of fabrication, according to another
embodiment of the invention. In FIG. 3A a first dielectric layer
302, e.g., an oxide layer, is formed, e.g., blanket deposited or
thermally grown, on a semiconductor substrate 300 that is of
monocrystalline silicon or the like. A hard mask layer 304 is
formed on the first dielectric layer 302. The hard mask layer 304
can be a second dielectric layer, such as a nitride layer, e.g., a
silicon nitride (Si.sub.3N.sub.4) layer, that is blanket deposited
on the first dielectric layer 302. Hard mask layer 304 is patterned
and portions thereof are removed, e.g., by dry etching, in regions
310 where NAND strings of memory cells, such as floating gate
memory cells, e.g., floating-gate transistors, will be formed, as
shown in FIG. 3B. For one embodiment, the first dielectric layer
302 is removed from regions 310 to expose portions 312 of substrate
300 in regions 310, as shown in FIG. 3B. For one embodiment, a
selective dry etch that stops at substrate 300 accomplishes
this.
[0022] A third dielectric layer 314, e.g., an oxide layer, is
formed, e.g., thermally grown, on the exposed portions 312 of
substrate 300 in FIG. 3C. The third dielectric layer 314 is
subsequently nitridized. For one embodiment, nitridation is
performed by exposing the third dielectric layer 314 to a
nitrogen-containing environment, e.g., an environment containing
NO, N.sub.2O, NH.sub.3, etc. at an elevated temperature, in FIG.
3D. The remaining portion of hard mask layer 304 is removed in FIG.
3E.
[0023] The resulting structure of FIG. 3E includes the first
dielectric layer (or gate dielectric layer) 302 in a region 320
where drain select gates will be formed and the third dielectric
layer (or tunnel dielectric layer) 314 in the regions 310 where the
NAND strings will be formed. Note that the first dielectric layer
302 in region 320 can be thicker than the third dielectric layer
314 in the regions 310. The thicker first dielectric layer 302 acts
to reduce gate-induced drain leakage or GIDL through the drain
select gates. Note further that hard mask layer 304 prevents
nitridation of first dielectric layer 302, where nitridation may
negatively affect performance of the drain select gates and is not
desired, but allows nitridation of third dielectric layer 314,
where the nitridation acts to improve reliability of the memory
cells.
[0024] FIG. 3F illustrates gate stacks 322 and 324 formed on the
first dielectric layer 302 and gate stacks 326 and 328 formed on
the third dielectric layer 314. Note that FIG. 3F has been enlarged
for clarity. Gate stacks 322 and 324 and the first dielectric layer
302 form drain select gates 323 and 325, e.g., field effect
transistors (FETs), where the first dielectric layer 302 acts as a
gate dielectric layer of drain select gates 323 and 325. Gate
stacks 326 and the third dielectric layer 314 form floating-gate
memory cells 327, such as floating-gate transistors, and gate
stacks 328 and the third dielectric layer 314 form floating-gate
memory cells 329, such as floating-gate transistors, where the
third dielectric layer 314 acts as a tunnel dielectric layer for
memory cells 327 and 329. Gate stacks 330 and 332 are also formed
on the third dielectric layer 314. Gate stacks 330 and 332 and the
third dielectric layer 314 form source select gates 331 and 333,
e.g., field effect transistors (FETs), where the third dielectric
layer 314 acts as a gate dielectric layer of source select gates
331 and 333. It will be apparent that the process could be readily
modified to form a source select gates 331 and 333 on portions of
the first dielectric layer 302 similar to drain select gates 323
and 325 if desired.
[0025] Memory cells 327 are connected in series, source to drain,
between drain select gate 323 and source select gate 331 to form a
NAND string 334 between drain select gate 323 and source select
gate 331. Memory cells 329 are connected in series, source to
drain, between drain select gate 325 and source select gate 333 to
form a NAND string 335 between drain select gate 325 and source
select gate 333. For one embodiment, source/drain regions 336 are
formed in substrate 300. For another embodiment, successive memory
cells of the respective NAND strings share a source/drain region
336, drain select gate 323 and memory cell 327.sub.1 of NAND string
334 share a source/drain region 336, source select gate 331 and
memory cell 327.sub.K of NAND string 334 of NAND string 334 share a
source/drain region 336, drain select gate 325 and memory cell
329.sub.1 of NAND string 335 share a source/drain region 336, and
source select gate 333 and memory cell 329.sub.L of NAND string 335
share a source/drain region 336.
[0026] Each of gate stacks 323 and 325 include a first conductive
layer 338, such as a conductively doped polysilicon layer, formed
on the first dielectric layer 302, a fourth dielectric layer 340
formed on the first conductive layer 338, and a second conductive
layer 350 formed on the fourth dielectric layer 340. Each of gate
stacks 326, 328, 330, and 332 include the first conductive layer
338 formed on the third dielectric layer 314, the fourth dielectric
layer 340 formed on the first conductive layer 338, and the second
conductive layer 350 formed on the fourth dielectric layer 340.
[0027] For one embodiment, the second conductive layer 350 is a
conductively doped polysilicon layer or a metal or metal-containing
layer, such as a refractory metal or refractory metal silicide
layer. The metals of chromium (Cr), cobalt (Co), hafnium (Hf),
molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti),
tungsten (W), vanadium(V) and zirconium (Zr) are generally
recognized as refractory metals. For another embodiment, the second
conductive layer 350 may be a single conductive layer of one or
more conductive materials, e.g., metal or metal-containing
materials, or two or more conductive layers, such as a metal or
metal-containing layer formed on a conductively doped polysilicon
layer. For one embodiment, the fourth dielectric layer 340 may be
an oxide layer, a nitride layer, an oxide-nitride-oxide (ONO)
layer, etc.
[0028] For each of the memory cells 327 and 329, the second
conductive layer 350 is a control gate (or a word line, such as a
word line 202 of FIG. 2), the first conductive layer 338 is a
floating gate, and the fourth dielectric layer interposed between
the first conductive layer 338 and the second conductive layer 350
is an intergate dielectric layer. For each of the drain select
gates 323 and 325 and the source select gates 331 and 333, for some
embodiments, the first conductive layer 338 and the second
conductive layer 350 may be strapped (or shorted) together so that
the shorted together first conductive layer 338 and second
conductive layer 350 form a control gate of the respective select
gates, where the control gate of each of the source select gates
331 and 333 is a source select line, such as a source select line
214 of FIG. 2, and the control gate of each of the drain select
gates 323 and 325 is a drain select line, such as a drain select
line 215 of FIG. 2. For another embodiment, the first conductive
layer 338 and the second conductive layer 350 are not shorted
together, and first conductive layer 338 forms the control gate of
the respective select gates.
[0029] Formation of gate stacks 322, 324, 326, 328, 330, and 332 is
well known and will not be detailed herein. Generally, the first
conductive layer 338 is formed on the first dielectric layer 302
and the third dielectric layer 314. After the first conductive
layer 338 is formed, it is patterned parallel to the plane of FIG.
3F. The fourth dielectric layer 340 is then formed on the first
conductive layer 338, and the second conductive layer 350 is formed
on the fourth dielectric layer 340. The second conductive layer 350
is patterned orthogonally to the patterning of the first conductive
layer 338, and the second conductive layer 350, the fourth
dielectric layer 340, and the first conductive layer 338 are
removed, e.g., by selective etching that stops at the first
dielectric layer 302 and the third dielectric layer 314, to expose
portions of the first dielectric layer 302 between gate stacks 322
and 324, between gate stacks 322 and 326.sub.1, and between gate
stacks 324 and 328.sub.1. This also exposes portions of the third
dielectric layer 314 between gate stacks 322 and 326.sub.1, between
gate stacks 324 and 328.sub.1, between gate stacks 330 and
326.sub.K, between gate stacks 332 and 328.sub.L, and between
successive gate stacks 326 and successive gate stacks 328.
[0030] It is generally desirable to use the same processing for all
of the gate stacks and to short the first and second conductive
layers of the gate stacks of the drain and source select gates
together, as described above. However, since the select gates
function differently than the memory cells, the gate stacks of the
select gates can be formed independently of the gate stacks of the
memory cells.
CONCLUSION
[0031] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement that is calculated to achieve the
same purpose may be substituted for the specific embodiments shown.
Many adaptations of the invention will be apparent to those of
ordinary skill in the art. Accordingly, this application is
intended to cover any adaptations or variations of the invention.
It is manifestly intended that this invention be limited only by
the following claims and equivalents thereof.
* * * * *