Abbott; Todd R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Abbott; Todd R..The latest application filed is for "photoresist processing methods".

Company Profile

0.43.45

Abbott; Todd R. - Boise ID US
Abbott; Todd R. - Highland UT US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Photoresist processing methods Grant 8,685,625 - Torek , et al. April 1, 2	2014-04-01
DRAM layout with vertical FETS and method of formation Grant 8,482,047 - Abbott , et al. July 9, 2	2013-07-09
DRAM layout with vertical FETs and method of formation Grant 8,389,360 - Abbott March 5, 2	2013-03-05
Photoresist Processing Methods App 20130017494 - Torek; Kevin J. ; et al.	2013-01-17
DRAM Layout with Vertical FETS and Method of Formation App 20130001663 - Abbott; Todd R. ; et al.	2013-01-03
Photoresist processing methods Grant 8,283,112 - Torek , et al. October 9, 2	2012-10-09
DRAM layout with vertical FETs and method of formation Grant 8,274,106 - Abbott , et al. September 25, 2	2012-09-25
DRAM Layout with Vertical FETS and Method of Formation App 20110254067 - Abbott; Todd R. ; et al.	2011-10-20
Photoresist Processing Methods App 20110244404 - Torek; Kevin J. ; et al.	2011-10-06
Dram Layout With Vertical Fets And Method Of Formation App 20110217819 - Abbott; Todd R.	2011-09-08
DRAM layout with vertical FETS and method of formation Grant 7,989,866 - Abbott , et al. August 2, 2	2011-08-02
Photoresist processing methods Grant 7,977,037 - Torek , et al. July 12, 2	2011-07-12
DRAM layout with vertical FETs and method of formation Grant 7,968,928 - Abbott June 28, 2	2011-06-28
DRAM including a vertical surround gate transistor Grant 7,768,051 - Abbott August 3, 2	2010-08-03
DRAM layout with vertical FETS and method of formation Grant 7,736,969 - Abbott , et al. June 15, 2	2010-06-15
DRAM Layout with Vertical FETS and Method of Formation App 20100052027 - Abbott; Todd R. ; et al.	2010-03-04
DRAM including a vertical surround gate transistor Grant 7,566,620 - Abbott July 28, 2	2009-07-28
DRAM layout with vertical FETs and method of formation Grant 7,560,336 - Abbott July 14, 2	2009-07-14
DRAM layout with vertical FETs and method of formation Grant 7,518,182 - Abbott , et al. April 14, 2	2009-04-14
Semiconductor constructions Grant 7,453,103 - Abbott , et al. November 18, 2	2008-11-18
DRAM layout with vertical FETs and method of formation App 20080237776 - Abbott; Todd R.	2008-10-02
Memory cells and select gates of NAND memory arrays Grant 7,402,861 - Abbott , et al. July 22, 2	2008-07-22
DRAM layout with vertical FETs and method of formation Grant 7,365,385 - Abbott April 29, 2	2008-04-29
Methods of forming a transistor with an integrated metal silicide gate electrode Grant 7,351,659 - Abbott April 1, 2	2008-04-01
Formation of memory cells and select gates of NAND memory arrays Grant 7,348,236 - Abbott , et al. March 25, 2	2008-03-25
Photoresist processing methods App 20080050925 - Torek; Kevin J. ; et al.	2008-02-28
Conductive structure for microelectronic devices and methods of fabricating such structures Grant 7,319,605 - Abbott January 15, 2	2008-01-15
NAND memory arrays and methods Grant 7,276,414 - Violette , et al. October 2, 2	2007-10-02
Methods of forming semiconductor structures Grant 7,262,089 - Abbott , et al. August 28, 2	2007-08-28
Dram including a vertical surround gate transistor App 20070090363 - Abbott; Todd R.	2007-04-26
NAND memory arrays App 20070063262 - Violette; Michael ; et al.	2007-03-22
Semiconductor damascene trench and methods thereof Grant 7,179,730 - Abbott February 20, 2	2007-02-20
Dram Including A Vertical Surround Gate Transistor App 20070018223 - Abbott; Todd R.	2007-01-25
Method of forming a field effect transistor with halo implant regions Grant 7,153,731 - Abbott , et al. December 26, 2	2006-12-26
Semiconductor Damascene Trench And Methods Thereof App 20060281302 - Abbott; Todd R.	2006-12-14
NAND memory arrays App 20060258093 - Violette; Michael ; et al.	2006-11-16
Method of forming a field effect transistor Grant 7,112,482 - Abbott , et al. September 26, 2	2006-09-26
Semiconductor damascene trench and methods thereof App 20060134898 - Abbott; Todd R.	2006-06-22
DRAM layout with vertical FETs and method of formation App 20060125123 - Abbott; Todd R.	2006-06-15
Semiconductor constructions App 20060081884 - Abbott; Todd R. ; et al.	2006-04-20
Semiconductor damascene trench and methods thereof Grant 7,029,963 - Abbott April 18, 2	2006-04-18
Methods of forming a transistor with an integrated metal silicide gate electrode Grant 7,012,024 - Abbott March 14, 2	2006-03-14
DRAM layout with vertical FETs and method of formation App 20060043617 - Abbott; Todd R.	2006-03-02
NAND memory arrays and methods App 20060040447 - Violette; Michael ; et al.	2006-02-23
DRAM layout with vertical FETS and method of formation App 20060038205 - Abbott; Todd R. ; et al.	2006-02-23
DRAM layout with vertical FETS and method of formation App 20060017088 - Abbott; Todd R. ; et al.	2006-01-26
Methods of forming a transistor with an integrated metal silicide gate electrode App 20060019457 - Abbott; Todd R.	2006-01-26
Integrated transistor circuitry Grant 6,987,291 - Abbott , et al. January 17, 2	2006-01-17
Memory cells and select gates of NAND memory arrays App 20060006456 - Abbott; Todd R. ; et al.	2006-01-12
Formation of memory cells and select gates of NAND memory arrays App 20050285178 - Abbott, Todd R. ; et al.	2005-12-29
Suppression of cross diffusion and gate depletion App 20050266666 - Trivedi, Jigish D. ; et al.	2005-12-01
Suppression of cross diffusion and gate depletion Grant 6,962,841 - Trivedi , et al. November 8, 2	2005-11-08
Semiconductor constructions, and methods of forming semiconductor structures App 20050199932 - Abbott, Todd R. ; et al.	2005-09-15
Conductive structure for microelectronic devices and methods of fabricating such structures App 20050167700 - Abbott, Todd R.	2005-08-04
Integrated circuitry Grant 6,911,702 - Abbott June 28, 2	2005-06-28
Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same Grant 6,900,494 - Abbott , et al. May 31, 2	2005-05-31
Conductive structure for microelectronic devices and methods of fabricating such structures Grant 6,879,507 - Abbott April 12, 2	2005-04-12
Methods of forming a transistor with an integrated metal silicide gate electrode App 20050037584 - Abbott, Todd R.	2005-02-17
Method of forming a field effect transistor App 20050003627 - Abbott, Todd R. ; et al.	2005-01-06
Semiconductor damascene trench and methods thereof App 20040241945 - Abbott, Todd R.	2004-12-02
Suppression of cross diffusion and gate depletion Grant 6,812,529 - Trivedi , et al. November 2, 2	2004-11-02
Sidewall strap for complementary semiconductor structures and method of making same Grant 6,806,134 - Trivedi , et al. October 19, 2	2004-10-19
Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same App 20040159895 - Abbott, Todd R. ; et al.	2004-08-19
Sidewall strap for complementary semiconductor structures and method of making same Grant 6,770,921 - Trivedi , et al. August 3, 2	2004-08-03
Method of forming local interconnects Grant 6,727,168 - Abbott April 27, 2	2004-04-27
Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same Grant 6,723,597 - Abbott , et al. April 20, 2	2004-04-20
Suppression of cross diffusion and gate depletion App 20040048431 - Trivedi, Jigish D. ; et al.	2004-03-11
Conductive structure for microelectronic devices and methods of fabricating such structures App 20040029331 - Abbott, Todd R.	2004-02-12
Method Of Using High-k Dielectric Materials To Reduce Soft Errors In Sram Memory Cells, And A Device Comprising Same App 20040009633 - Abbott, Todd R. ; et al.	2004-01-15
Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications Grant 6,677,650 - Fischer , et al. January 13, 2	2004-01-13
Cross-diffusion resistant dual-polycide semiconductor structure and method Grant 6,613,617 - Trivedi , et al. September 2, 2	2003-09-02
Method of forming a field effect transistor Grant 6,599,789 - Abbott , et al. July 29, 2	2003-07-29
Integrated circuitry App 20030082868 - Abbott, Todd R.	2003-05-01
Integrated circuitry and method of forming local interconnects App 20030077855 - Abbott, Todd R.	2003-04-24
Cross-diffusion resistant dual-polycide semiconductor structure and method App 20030057453 - Trivedi, Jigish D. ; et al.	2003-03-27
Sidewall strap for complementary semiconductor structures and method of making same App 20030054614 - Trivedi, Jigish D. ; et al.	2003-03-20
Sidewall strap for complementary semiconductor structures and method of making same App 20030042514 - Trivedi, Jigish D. ; et al.	2003-03-06
Cross-diffusion Resistant Dual-polycide Semiconductor Structure And Method App 20030042628 - Trivedi, Jigish D. ; et al.	2003-03-06
Semiconductor damascene trench and methods thereof App 20030042546 - Abbott, Todd R.	2003-03-06
Integrated circuitry App 20030015766 - Abbott, Todd R. ; et al.	2003-01-23
Method Of Forming A Field Effect Transistor App 20030008438 - Abbott, Todd R. ; et al.	2003-01-09
Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications App 20020132467 - Fischer, Mark ; et al.	2002-09-19
Suppression of cross diffusion and gate depletion App 20020132441 - Trivedi, Jigish D. ; et al.	2002-09-19
Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications Grant 6,376,358 - Fischer , et al. April 23, 2	2002-04-23