U.S. patent application number 10/908360 was filed with the patent office on 2006-11-09 for electrical programmable metal resistor.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Lawrence A. Clevenger, James J. Demarest, Louis C. Hsu, Carl Radens, Chih-Chao Yang.
Application Number | 20060249846 10/908360 |
Document ID | / |
Family ID | 37085918 |
Filed Date | 2006-11-09 |
United States Patent
Application |
20060249846 |
Kind Code |
A1 |
Yang; Chih-Chao ; et
al. |
November 9, 2006 |
ELECTRICAL PROGRAMMABLE METAL RESISTOR
Abstract
The present invention provides an electrical programmable metal
resistor and a method of fabricating the same in which
electromigration stress is used to create voids in the structure
that increase the electrical resistance of the resistor.
Specifically, a semiconductor structure is provided that includes
an interconnect structure comprising at least one dielectric layer,
wherein said at least one dielectric layer comprises at least two
conductive regions and an overlying interconnect region embedded
therein, said at least two conductive regions are in contact with
said overlying interconnect region by at least two contacts and at
least said interconnect region is separated from said at least one
dielectric layer by a diffusion barrier, wherein voids are present
in at least the interconnect region which increase the electrical
resistance of the interconnect region.
Inventors: |
Yang; Chih-Chao;
(Poughkeepsie, NY) ; Clevenger; Lawrence A.; (La
Grangeville, NY) ; Demarest; James J.; (Fishkill,
NY) ; Hsu; Louis C.; (Fishkill, NY) ; Radens;
Carl; (La Grangeville, NY) |
Correspondence
Address: |
SCULLY, SCOTT, MURPHY & PRESSNER, P.C.
400 GARDEN CITY PLAZA
Suite 300
GARDEN CITY
NY
11530
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
NEW ORCHARD ROAD
ARMONK
NY
|
Family ID: |
37085918 |
Appl. No.: |
10/908360 |
Filed: |
May 9, 2005 |
Current U.S.
Class: |
257/751 ;
257/E23.149; 257/E23.167 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 28/20 20130101; H01L 2924/00 20130101; H01L 23/5329 20130101;
H01L 2924/0002 20130101; H01L 23/5228 20130101; H01L 23/5256
20130101 |
Class at
Publication: |
257/751 |
International
Class: |
H01L 23/52 20060101
H01L023/52 |
Claims
1. A semiconductor structure comprising an interconnect structure
comprising at least one dielectric layer, wherein said at least one
dielectric layer comprises at least two conductive regions and an
overlying interconnect region embedded therein, said at least two
conductive regions are in contact with said overlying interconnect
region by at least two contacts and at least said interconnect
region is separated from said at least one dielectric layer by a
diffusion barrier, wherein voids are present in at least the
interconnect region which increase electrical resistance of the
interconnect region.
2. The semiconductor structure of claim 1 wherein said interconnect
structure is a single damascene interconnect structure and said at
least one dielectric layer includes a first dielectric layer and a
second dielectric layer, wherein said at least two conductive
regions and said at least two contacts are located in said first
dielectric layer and said interconnect region is located in said
second dielectric layer.
3. The semiconductor structure of claim 2 wherein said voids are
formed in the interconnect region above said at least two contact
regions.
4. The semiconductor structure of claim 2 further comprising a
capping layer located atop said second dielectric layer and said
interconnect region.
5. The semiconductor structure of claim 1 wherein said interconnect
structure is a dual damascene interconnect structure and said at
least one dielectric layer includes a first dielectric layer and a
second dielectric layer, wherein said at least two conductive
regions are located in said first dielectric layer, and said at
least two contacts and said interconnect region are located in said
second dielectric layer.
6. The semiconductor structure of claim 5 wherein said diffusion
barrier separates said at least two contacts and said interconnect
region from said second dielectric layer.
7. The semiconductor structure of claim 5 wherein said voids are
located in said interconnect region and said contacts.
8. The semiconductor structure of claim 5 further comprising a
capping layer located atop said second dielectric layer and said
interconnect region.
9. The semiconductor structure of claim 5 further comprising an
upper interconnect level atop said interconnect structure, said
upper interconnect level comprising conductively filled vias and
lines embedded within a third dielectric layer.
10. The semiconductor structure of claim 9 wherein said voids are
present in said interconnect region at the footprint of the
conductively filled vias of said upper interconnect level.
11. A method of fabricating a semiconductor structure comprising
providing an interconnect structure comprising at least one
dielectric layer, wherein said at least one dielectric layer
comprises at least two conductive regions and an overlying
interconnect region embedded therein, said at least two conductive
regions are in contact with said overlying interconnect region by
at least two contacts and said interconnect region is separated
from said at least one dielectric layer by a diffusion barrier; and
applying an electrical bias between two of said contacts under
electromigration stress conditions to form voids in at least the
interconnect region which increase the electrical resistance of the
interconnect region.
12. The method of claim 11 wherein said providing said interconnect
structure comprises a single or dual damascene process.
13. The method of claim 11 wherein said applying said electrical
bias is repeated a number of times to create a plurality of voids
within said interconnect region.
14. The method of claim 11 wherein said electromigration stress
conditions comprise a current of greater than 5 mA/.mu..sup.2 at a
temperature of greater than about 80.degree. C.
15. The method of claim 11 wherein said electromigration stress
conditions comprise a current of from about 5 to about 1000
mA/.mu.m.sup.2 and a temperature of from about 80.degree. C. to
about 500.degree. C.
16. The method of claim 11 wherein said electromigration stress
conditions cause electrons to flow upwards from one of the at least
two contacts to said interconnect region.
17. The method of claim 11 wherein said electromigration stress
conditions cause electrons to flow downwards from an overlying
conductively filled via of an upper interconnect level to said
interconnect region.
18. The method of claim 11 further comprising forming a capping
layer on said interconnect structure.
19. The method of claim 11 wherein said diffusion barrier separates
said at least one interconnect region from said at least one
dielectric layer.
20. A semiconductor circuit comprising: an interconnect structure
comprising at least one dielectric layer, wherein said at least one
dielectric layer comprises at least two conductive regions and an
overlying interconnect region embedded therein, said at least two
conductive regions are in contact with said overlying interconnect
region by at least two contacts and at least said interconnect
region is separated from said at least one dielectric layer by a
diffusion barrier, wherein voids are present in at least the
interconnect region which increase the resistance of the
interconnect region and said interconnect region includes a first
and second node and is coupled to a voltage output pin; a series of
switches in contact with said interconnect region, said series of
switches are coupled to a voltage input pin; and a decoder coupled
independently to each of said switches, said decoder providing bit
addresses that are based on output data received from each of the
switches.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a semiconductor structure
and a method of fabricating the same. More particularly, the
present invention provides an electrical programmable metal
resistor and a method of fabricating the same in which
electromigration stress is used to create voids in the structure
that increase the resistance of the resistor.
BACKGROUND OF THE INVENTION
[0002] In semiconductor devices, it is well known to have thin film
resistors embedded in the back-end-of-the-line (BEOL) of the chip
through either a damascene process or a subtractive etch method.
BEOL thin film resistors are preferred over other types of
resistors because of lower parasitics. However, the sheet
resistivity of the various resistors formed over the entire wafer
may vary and go beyond specifications due to poor process control.
In an advanced manufacturing line, wafers out of specification are
often scrapped for quality control.
[0003] The resistor is one of the most common electrical components
used in almost every electrical device. Conventionally, doped
polysilicon is used as the material of a resistor. However, the
conventional resistor can only provide a limited resistance within
a limited dimension as manufactures keep shrinking the device
feature size down. To overcome this problem, new materials with
higher resistivity and new integrations are required for
fabrication of thin film resistors in a highly integrated
semiconductor device.
[0004] Resistive thin films such as CrSi and TaN are often used as
resistors in semiconductor devices. Integration schemes used to
fabricate the resistor components within the interconnect structure
fall into two primarily categories. In the first integration
scheme, a thin film resistor is formed, by etching on top of an
insulator. A metallic layer is deposited on top of the resistive
layer and is used to protect the resistor layer from being damaged
during the sequential etching process. After the resistor has been
defined, the underlying dielectric layer is then patterned and
etched to define the interconnect pattern. Finally, a metallic
layer for the interconnect is deposited, patterned and etched.
Although the protective layer is capable of protecting the
resistive layer, the provided protection is limited and the
resistive layer may still be damaged during the etching process.
This integration scheme is disclosed, for example, in U.S. Pat. No.
6,207,560.
[0005] In the second integration scheme, a thin film resistor is
formed, by etching on top of an insulator. An interlevel dielectric
is then deposited, followed by patterning and etching processes to
define an upper level interconnect structure with vias connected to
the underlying thin film resistor. A planarization process is
usually required after deposition of the interlevel dielectric
material in order to compromise any possible topography related
issues caused by the underlying resistors.
[0006] Some additional prior art disclosures of BEOL resistors and
methods of fabricating the same include, for example: U.S. Patent
Application Publication No. 2004/0027234, U.S. Pat. No. 6,232,042,
U.S. Pat. No. 6,207,560, U.S. Pat. No. 6,083,785, and U.S. Pat. No.
5,485,138.
[0007] Resistors can be trimmed by using laser or high-energy
particle beams in order to set the resistance of the resistor. The
prior art trimming processes are not clean and therefore have never
become a common practice. Resistors can also be programmed by using
a shut resistor to deselect at least a portion of the resistor from
a chain of resistors within a circuit. This prior art method has
two problems; first the resolution of the programming is limited by
the least significant bit device size. Secondly, the shut device
itself has some resistance. The tuning precision is thus poor.
[0008] In view of the above, there is a need to provide a BEOL
resistor that can be electrically programmed without the need of
using prior art shut resistors and wherein the resistance of the
resistor can be set without the need of using prior art trimming
methods.
SUMMARY OF THE INVENTION
[0009] It is an object of the present invention to provide a BEOL
structure with an interconnect and a thin film resistor at the same
level. It is another object of the present invention to provide a
process that is BEOL compatible that does not require an extra mask
or extra materials to fabricate the thin film resistor.
[0010] Electromigration (EM) effect has long been identified as a
reliability related phenomenon inside a biased metal interconnect.
Voids are formed inside the biased metal interconnect due to metal
ion movement caused by high density of current flow. In short,
electromigration is caused by a positive divergence of the ionic
flux, which leads to an accumulation of vacancies, forming a void
in the metal. It appears that ions are moved "downstream" by the
force of "electron wind". In general, the void creating rate inside
the metal is a function of current density and temperature.
[0011] The present invention provides a method of adopting
electromigration (EM) stress as a required process step for chip
manufacturing. A diffusion barrier is used as an electrical path
around anode(s) within the inventive structure after the EM stress
and the resulting electrical resistance can be modulated via
controlling the stress time.
[0012] The present invention offers the following advantages over
the prior art: (i) No etch stop material is required to be located
over the thin film resistors, (ii) the thin film resistor can be
photographically defined and etched rather than be defined by
lift-off, (iii) the resistance of the structure is determined by
the void size inside the structure which is a direct result of EM
stress application which offers a feature of better resistor
control, and (iv) the inventive process is compatible to current
BEOL process flow, and no extra mask/material is required for
creating the resistor structure.
[0013] In addition to an extra mask being required in the prior art
for fabricating a BEOL thin film resistor structure, the prior art
processes are complicated which also increases the manufacturing
costs. Since the present invention does not require an extra mask
and relatively simple and BEOL compatible processing steps are
used, the inventive method does not add additional manufacturing
costs to the fabrication process.
[0014] In broad terms, the present invention provides a
semiconductor structure that comprises:
[0015] an interconnect structure comprising at least one dielectric
layer, wherein said at least one dielectric layer comprises at
least two conductive regions and an overlying interconnect region
embedded therein, said at least two conductive regions are in
contact with said overlying interconnect region by at least two
contacts and at least said interconnect region is separated from
said at least one dielectric layer by a diffusion barrier, wherein
voids are present in at least the interconnect region which
increase the electrical resistance of the interconnect region.
[0016] In one embodiment of the present invention, the interconnect
structure is a single damascene interconnect structure including a
first dielectric and a second dielectric layer located atop the
first dielectric. In this embodiment, the at least one conductive
region and the at least two contacts are located in the first
dielectric layer and the interconnect region is located in the
second dielectric layer. In such an embodiment, the voids are
located mainly within the interconnect region. A capping layer is
present in the interconnect structure and it is located atop the
second dielectric and the interconnect region.
[0017] In another embodiment of the present invention, the
interconnect structure is a dual damascene interconnect structure
including a first dielectric layer that includes the conductive
regions, and a second dielectric that includes the contacts and the
interconnect region embedded therein. In this embodiment, both the
interconnect region and the contacts are separated from the second
dielectric by the diffusion barrier. In the embodiment including
this dual damascene interconnect structure, the voids are located
within the interconnect region as well as the contacts. A capping
layer is also present atop the second dielectric layer and the
interconnect region in this interconnect structure as well.
[0018] In yet another embodiment of the present invention, the
interconnect structure is also a dual damascene structure in which
another interconnect level is located thereon. In this embodiment,
the voids are located within the interconnect region at the
footprints of the overlying conductively filled vias that are
present in the other interconnect level. A capping layer is also
present atop the second dielectric layer and the interconnect
region in this interconnect structure as well.
[0019] It is noted that in the inventive structure defined above,
the interconnect region is the thin film resistor of the present
invention which is embedded within one of the dielectric layers of
an interconnect (single or dual damascene) structure. The presents
of the voids controls the electrical resistance of the interconnect
region and thus the resistor.
[0020] In addition to the structure provided above, the present
invention also provides a method of fabricating the same. The
method of the present invention broadly includes the steps of:
[0021] providing an interconnect structure comprising at least one
dielectric layer, wherein said at least one dielectric layer
comprises at least two conductive regions and an overlying
interconnect region embedded therein, said at least two conductive
regions are in contact with said overlying interconnect region by
at least two contacts and at least said interconnect region is
separated from said at least one dielectric layer by a diffusion
barrier; and
[0022] applying an electrical bias between two of said contacts
under electromigration stress conditions to form voids in the
interconnect region which increase the electrical resistance of the
interconnect region.
[0023] The electromigration stress conditions that are capable of
forming the voids in the interconnect region comprise biasing using
a current of greater than 5 mA/.mu.m.sup.2 at a temperature of
greater than about 80.degree. C.
[0024] The located of the voids is dependent on whether a single or
dual damascene interconnect structure is employed and whether an
upstream stress mode or a downstream stress mode are employed. In
an upstream stress mode, the electromigration stress causes
electrons to flow upwards, while in the downstream stress mode the
electrons flow down. These terms will be defined in greater detail
herein below.
[0025] In addition to the above, the present invention also
provides a programmable circuit that includes:
[0026] an interconnect structure comprising at least one dielectric
layer, wherein said at least one dielectric layer comprises at
least two conductive regions and an overlying interconnect region
embedded therein, said at least two conductive regions are in
contact with said overlying interconnect region by at least two
contacts and at least said interconnect region is separated from
said at least one dielectric layer by a diffusion barrier, wherein
voids are present in at least the interconnect region which
increase the resistance of the interconnect region and said
interconnect region includes a first and second node and is coupled
to a voltage output pin;
[0027] a series of switches in contact with said interconnect
region, said series of switches are coupled to a voltage input pin;
and
[0028] a decoder coupled independently to each of said switches,
said decoder providing bit addresses that are based on output data
received from each of the switches.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] FIGS. 1A-1E are pictorial representations (through cross
section views) illustrating the basic processing steps employed in
one embodiment of the present invention.
[0030] FIGS. 2A-2E are pictorial representations (through cross
section views) illustrating the basic processing steps employed in
another embodiment of the present invention.
[0031] FIGS. 3A-3D are pictorial representations (through cross
section views) illustrating the basic processing steps employed in
yet another embodiment of the present invention.
[0032] FIG. 4 is a schematic showing the programmable circuit of
the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0033] The present invention, which provides an interconnect
structure with a thin film resistor at the same level as the
interconnect and a method of adopting electromigration (EM) stress
as a processing step for chip manufacturing, will now be described
in greater detail by referring to the drawings that accompany the
present application. It is noted that the drawings of the present
invention are provided for illustrative purposes and thus they are
not drawn to scale. In the drawings, like reference numerals are
used for describing like and corresponding elements.
[0034] Reference is first made to FIGS. 1A-1E which illustrate one
of the embodiments of the present invention. In this embodiment of
the present invention, a single damascene process is used and
electromigration of electrons for void formation occurs via an
upstream stress mode. Reference is first made to FIG. 1A, which
illustrates an initial interconnect structure 10 that is used in
the present invention. The initial interconnect structure 10 shown
in FIG. 1A comprises one of the interconnect levels of an
interconnect structure. The interconnect level illustrated in FIG.
1A is fabricated using a single damascene process which is well
known to those skilled in the art of semiconductor interconnect
technology.
[0035] The initial interconnect structure 10 illustrated in FIG. 1A
is formed atop a substrate (not shown). The underlying substrate,
which is not illustrated in the drawings of the present invention,
may include a semiconducting material, an insulating material, a
conductive material or any combination thereof, including
multilayered structures. Thus, for example, the underlying
substrate can be a semiconducting material such as Si, SiGe, SiGeC,
SiC, GaAs, InAs, InP and other III/V or II/VI compound
semiconductors. The semiconducting structure can also include a
layered substrate such as, for example, Si/SiGe, Si/SiC, a
silicon-on-insulator (SOI) or a silicon germanium-on-insulator.
[0036] When the underlying substrate is an insulating material, the
insulating material can be an organic insulator, an inorganic
insulator or a combination thereof, including multilayers. When the
underlying substrate is comprised of a conductive material, the
substrate may include, for example, polysilicon, an elemental
metal, alloys of elemental metals, a metal silicide, a metal
nitride or a combination thereof, including multilayers.
[0037] In some embodiments, the underlying substrate includes a
combination of a semiconducting material and an insulating
material, a combination of a semiconducting material and a
conductive material or a combination of a semiconducting material,
an insulating material and a conductive material.
[0038] When the underlying substrate comprises a semiconductor
material, one or more semiconductor devices such as, for example,
complementary metal oxide semiconductor (CMOS) devices can be
fabricated thereon. For clarity, the one or more semiconductor
devices are not shown in the drawings of the present
application.
[0039] The initial interconnect structure 10 shown in FIG. 1A
comprises a first dielectric layer 12 having at least two
conductive regions located therein. In the drawing, five conductive
regions 14A, 14B, 14C, 14D and 14E are shown for illustrative
purposes. The at least two conductive regions comprise a conductive
material such as, for example, polysilicon, a conductive metal
including, but not limited to: Al, Cu, W, and Ni, and other like
conductors including alloys, silicides and conductive oxynitrides
of the aforementioned conductive metals. Preferably, the at least
one conductive region comprises one of the above-mentioned
conductive metals, with Al and Cu being most preferred.
[0040] The first dielectric layer 12 may comprise an organic or
inorganic dielectric that is porous or non-porous. Porous materials
are formed by incorporating a porogen with the dielectric precursor
that is removed from the dielectric after deposition by a thermal
process. Examples of an inorganic dielectric that can be used as
the first dielectric layer 12 are oxides such as SiO.sub.2. One
example of an organic dielectric that can be used in the present
invention as the first dielectric layer 12 comprises a
silicon-containing material such as a composition containing atoms
of Si, C, O and H (SiCOH) also called C doped oxide or
organosilicate glass. Another example of an organic dielectric that
can be used as the first dielectric layer 12 is a thermosetting
polyarylene ether. The term "polyarylene"i is used herein to denote
aryl moieties or inertly substituted aryl moieties which are linked
together by bonds, fused rings, or inert linking groups such as
oxygen, sulfur, sulfone, sulfoxide or carbonyl. In one embodiment
of the present invention, the first dielectric is an inorganic
dielectric such as SiO.sub.2.
[0041] The first dielectric layer 12 typically has a dielectric
constant from about 7.0 or less, with a dielectric constant from
about 2.5 to about 4.0 being even more typical. All dielectric
constants mentioned in the present application are relative to a
vacuum unless otherwise noted. As indicated above, the first
dielectric layer 12 may be porous or non-porous. When porous
dielectrics are used, the dielectric constant of the porous
material is less than the nonporous version of the same dielectric
material.
[0042] The first dielectric layer 12 has a thickness that typically
ranges from about 50 nm to about 4 .mu.m, with a thickness from
about 100 to about 500 nm being even more typical. The thickness of
the first dielectric layer 12 is dependent upon the dielectric
material employed as well as the deposition process that was used
in forming the same. Illustrative examples of some deposition
processes that can be used in forming the first dielectric layer 12
are chemical vapor deposition (CVD), plasma enhanced chemical vapor
deposition (PECVD), high-density plasma deposition, pulsed PECVD,
spin-on application and other like deposition techniques.
[0043] The first dielectric layer 12 also includes at least two
contacts (i.e., vias) that connect the at least two conductive
regions in the first dielectric layer to an overlying interconnect
region. In FIG. 1A, five contacts (i.e., vias) 16A-16E are shown
for illustrative purposes only. The contacts are comprised of a
conductive material including, for example, W, Al, or Cu, with W
contacts being more typical.
[0044] The initial interconnect structure 10 also includes a second
dielectric layer 18 that is located atop the first dielectric layer
12. The second dielectric layer 18 may comprise the same or
different dielectric as that of the first dielectric layer 12.
Preferably, the second dielectric layer 18 is comprised of a
dielectric material that differs in composition from that of the
first dielectric layer 12. For example, when the first dielectric
layer 12 is comprised of SiO.sub.2, than the second dielectric
layer 18 is comprised of an organic dielectric such as a carbon
doped oxide or thermosetting polyarylene ether.
[0045] The second dielectric layer 18 is formed utilizing one of
the above-mentioned deposition processes and the second dielectric
layer 18 typically has a thickness from about 100 to about 450
nm.
[0046] The second dielectric layer 18 includes an interconnect
region 22 that is located with an opening formed into the second
dielectric layer. The interconnect region 22 shown in FIG. 1A
represents the thin film resistor of the present invention. Prior
to forming the interconnect region 22, the opening is lined with a
diffusion barrier 20. The diffusion barrier 20 comprises one or
more conductive materials including, for example, Ta, Ti, TaN, W,
Ru or TiSiN. The diffusion barrier 20 is formed by a conventional
deposition process such as, for example, plating, ALD (atomic layer
deposition), CVD, sputtering, evaporation and other like deposition
processes and the diffusion barrier 20 typically has a thickness
from about 1 to about 80 nm.
[0047] The interconnect region 22 that is located within an opening
formed into the second dielectric layer 18 is comprised of a
conductive material including the same or different conductor as
that of the at least one conductive regions. Typically, the
interconnect region is comprised of a conductive metal such as, for
example, Cu or Al.
[0048] The initial interconnect structure 10 also includes a
capping layer 24 that is located atop the second dielectric layer
18 as well as atop the interconnect region 22. The capping layer 24
is comprised of a dielectric material including, for example,
Si.sub.3NH.sub.4 or Si.sub.xC.sub.y(N.sub.zH). The capping layer 24
is formed by a conventional deposition process such as, for
example, CVD or PECVD, and its' thickness is typically from about
10 to about 80 nm.
[0049] It is again emphasized that the initial interconnect
structure 10 shown in FIG. 1A is formed utilizing a conventional
single damascene process that is well known to those skilled in the
art.
[0050] Electromigration is then carried out in the interconnect
region 22 by applying an electrical bias between two of the
contacts, e.g., contacts 16A and 16E, under stress conditions which
are capable of forming void 28 in the interconnect region 22. That
is, contacts 16A and 16E, for example, are used as a cathode and
anode respectively, and an electrical bias is applied to the
structure under a stress condition having a current of greater than
5 mA/.mu.m.sup.2 and at a temperature of greater than about
80.degree. C. Specifically, the void 28 is formed into the
interconnect region 22 by applying an electrical bias having a
current from about 5 to about 1000 mA/.mu.m.sup.2 and at a
temperature from about 80.degree. to about 500.degree. C. In the
embodiment depicted in FIG. 1B, the biasing causes electrons to
flow from contact 16A to contact 16E in an upstream stress mode
forming a void 28 above contact 16A. In FIG. 1B, the arrow under
the structure shows the direction of electron flow during the
electromigration process. The electrical resistance of the
structure, particularly the interconnect region 22, is in-situ
monitored during the electromigration process.
[0051] The electromigration process may be repeated any number of
times to form further voids 28 in the interconnect region 22.
Specifically, the electromigration process can be repeated any
number of times depending upon the number of contacts that are
present in the structure. FIGS. 1C and 1D show the structure after
a series of electromigration processes. The conditions of the other
electromigration processes are within the ranges mentioned above
for the first electromigration process. A shown in FIG. 1C, a
second void 28 is formed atop the contact 16B during the second
electromigration process, a third void 28 and fourth void 28 is
formed above the contact 16C and 16D during other electromigration
processes.
[0052] After performing the desired number of electromigrations, an
upper interconnect structure 29 comprising conductively filled
lines and vias 30 that are embedded into a third dielectric layer
32 utilizing techniques well known in the art. This resultant
structure is shown, for example, in FIG. 1E. The conductively
filled lines and vias 30 are comprised of one of the
above-mentioned conductive materials and the third dielectric layer
32 comprises one of the above-mentioned inorganic or organic
dielectric materials. Additional interconnect structures, as
desired, can be formed atop the structure shown in FIG. 1E.
[0053] FIGS. 2A-2E are pictorial representations of another
embodiment of the present invention in which dual damascene
technology is used together with an electromigration process that
is operated in the upstream stress mode. FIG. 2A shows the initial
dual damascene structure 50 that is located above a substrate as
defined above. Structure 50 includes at least two conductive
regions (14A-14E, for example) embedded within a first dielectric
layer 12'. The initial dual damascene structure 50 also includes at
least two contacts (16A-16E, for example) above the at least two
conductive regions embedded with a second dielectric layer 12. The
second dielectric layer 12 also includes an interconnect region 22
above the at least two contacts. The interconnect region 22 and the
contacts are formed using photolithography and etching of the
second dielectric layer 12. A diffusion barrier 20 is shown lining
the via and line openings created by photolithography and etching.
The initial dual damascene structure 50 also includes a capping
layer 24 atop the second dielectric layer 12 and the interconnect
region 22.
[0054] FIGS. 2B-2D shows the initial dual damascene structure 50
during various electromigration steps that are performed under
stress conditions that are capable of forming voids 28 in the
structure. In the dual damascene embodiment, the electromigration
process forms voids 28 with the interconnect region and the
contacts as shown.
[0055] FIG. 2E shows the structure after forming an upper
interconnect structure 29 including conductively filled lines and
vias 30 embedded within a dielectric 32.
[0056] FIGS. 3A-3D show an embodiment in which a dual damascene
technique and a downstream stress electromigration mode are used.
Reference is first made to FIG. 3A which shows an initial
interconnect structure 75 that includes a lower interconnect
structure 70 and an upper interconnect structure 29. The lower
interconnect structure 70 includes a first dielectric layer 12'
having at least two conductive regions (14A and 14B, for example)
embedded therein and a second dielectric 12 including contacts (16A
and 16B) and interconnect region 22. A diffusion barrier 20 lines
the interconnect region 22 and the contacts. The lower interconnect
structure 70 also including a capping layer 24 as described above
atop the second dielectric layer 12 and the interconnect region 22.
The upper interconnect structure 29 includes a third dielectric 32
having conductively filled vias and lines 30 embedded therein. A
capping layer 24' is located above the upper interconnect structure
29 and a diffusion barrier 20' is also present in the disclosed
structure.
[0057] FIGS. 3B-3D show the structure during the various
electromigration process which creates voids 28 in the structure.
In the embodiment depicted, the voids 28 are formed in the
interconnect region 22 that lies beneath the conductively filled
vias of the upper interconnect structure 29. The electromigration
process is conducted in this embodiment by applying an electrical
bias between the conductively filled vias and lines of the upper
interconnect structure 29. In this embodiment, the electrons flow
from top interconnect 29 to bottom interconnect 22. The voids are
formed utilizing the stress conditions mentioned above.
[0058] It should be noted that the interconnect region 22 shown in
the above embodiments represents the resistor of the present
invention. The electrical resistance of the resistor is determined
by the void size with larger voids providing increased resistance.
The size of the voids can be controlled by the electromigration
process thus offering better resistor control. Moreover, tuning of
the resistor can be automatically done using on-chip state-machine
and algorithms. The methods described above provide a means for
fabricating a high precision resistor.
[0059] FIG. 4 shows a simple programmable circuit scheme that can
include the inventive semiconductor structure. Here a 2.times.4
decoder taking a 2-bit address A0 and A1 generates four bit outputs
D0 to D3. Each output controls a switch (i.e., T0 to T3) therefore
each time only one switch is tuned on for EM programming. The two
nodes of the resistor are X and Y. The program V.sub.out pin is
intentionally attached at an extension side of the switch for two
purposes: (1) the extension would have capacity which can be used
to sink the metal during EM programming. (2) To keep the V.sub.out
pin away from Y would avoid the programming effect that typically
causes detrimental impact to the resistor thereby the resistor of
the present invention maintains its accuracy.
[0060] While the present invention has been particularly shown and
described with respect to preferred embodiments thereof, it will be
understood by those skilled in the art that the foregoing and other
changes in forms and details may be made without departing from the
scope and spirit of the present invention. It is therefore intended
that the present invention not be limited to the exact forms and
details described and illustrated, but fall within the scope of the
appended claims.
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