U.S. patent application number 11/408133 was filed with the patent office on 2006-09-07 for epitaxially deposited source/drain.
Invention is credited to Justin K. Brask, Nick Lindert, Anand S. Murthy.
Application Number | 20060197164 11/408133 |
Document ID | / |
Family ID | 34522194 |
Filed Date | 2006-09-07 |
United States Patent
Application |
20060197164 |
Kind Code |
A1 |
Lindert; Nick ; et
al. |
September 7, 2006 |
Epitaxially deposited source/drain
Abstract
An epitaxially deposited source/drain extension may be formed
for a metal oxide semiconductor field effect transistor. A
sacrificial layer may be formed and etched away to undercut under
the gate electrode. Then a source/drain extension of epitaxial
silicon may be deposited to extend under the edges of the gate
electrode. As a result, the extent by which the source/drain
extension extends under the gate may be controlled by controlling
the etching of the sacrificial material. Its thickness and depth
may be controlled by controlling the deposition process. Moreover,
the characteristics of the source/drain extension may be controlled
independently of those of the subsequently formed deep or heavily
doped source/drain junction.
Inventors: |
Lindert; Nick; (Beaverton,
OR) ; Murthy; Anand S.; (Portland, OR) ;
Brask; Justin K.; (Portland, OR) |
Correspondence
Address: |
TROP PRUNER & HU, PC
1616 S. VOSS ROAD, SUITE 750
HOUSTON
TX
77057-2631
US
|
Family ID: |
34522194 |
Appl. No.: |
11/408133 |
Filed: |
April 20, 2006 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10692696 |
Oct 24, 2003 |
7060576 |
|
|
11408133 |
Apr 20, 2006 |
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Current U.S.
Class: |
257/409 ;
257/E21.43; 257/E21.431; 438/140 |
Current CPC
Class: |
H01L 29/66636 20130101;
H01L 29/66628 20130101 |
Class at
Publication: |
257/409 ;
438/140 |
International
Class: |
H01L 29/76 20060101
H01L029/76; H01L 21/332 20060101 H01L021/332 |
Claims
1. A field effect transistor comprising: a substrate; a doped
epitaxial semiconductor material formed over said substrate; and a
gate electrode formed over said doped epitaxial semiconductor
material, said doped epitaxial semiconductor material extending
under said gate electrode.
2. The transistor of claim 1 including a source/drain having a
source/drain extension, said source/drain extension being formed of
said doped epitaxial semiconductor material and extends under the
edges of the gate electrode.
3. The transistor of claim 2 wherein said material has a first
thickness near said gate electrode and a second thickness spaced
from said gate electrode, said second thickness being greater than
said first thickness.
4. The transistor of claim 3 including a sidewall spacer, said
material extending under said sidewall spacer.
5. The transistor of claim 4 wherein said second thickness is
aligned with said sidewall spacer.
6. The transistor of claim 1 wherein said transistor is a delta
doped transistor.
7. The transistor of claim 1 including an ion implanted
source/drain under said doped epitaxial semiconductor material.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 10/692,696, filed on Oct. 24, 2003.
BACKGROUND
[0002] This invention relates generally to metal oxide
semiconductor field effect transistors.
[0003] Metal oxide semiconductor field effect transistors include a
gate that is self-aligned with a source/drain. The source/drain may
include a deeper or heavily doped region and a shallower and
lightly doped region, sometimes called a tip or source/drain
extension.
[0004] Gate underlap is the amount by which the source/drain
material diffuses under the gate after ion implantation and
subsequent heat processing. After implantation, the material that
is implanted is exposed to heat which causes the material to move
downwardly into the substrate and, to a lesser extent, laterally
under the gate. Thus, in a system using an ion implanted
source/drain extension, the amount of underdiffusion is determined
as a function of junction depth.
[0005] It is desirable to have relatively shallow junction depth
for the source/drain extension to support smaller transistor
dimensions. Usually, in source/drain extension implantation
techniques, the minimum tip junction depths are determined by the
necessary gate underlap.
[0006] The shallower the source/drain extension, generally the
shorter the gate lengths that may be utilized without increasing
off-state leakage currents. Extension doping under the gate edge is
needed to ensure a low resistance path between the inversion layer
under the gate and the highly doped source/drain extension region.
The low resistance is needed for a high drive currents, which are
critical for high circuit switching speeds.
[0007] Thus, there is a need for better ways to make source/drain
junctions of field effect transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a greatly enlarged, cross-sectional view at one
stage of manufacture;
[0009] FIG. 2 is an enlarged, cross-sectional view at a subsequent
stage of manufacture in accordance with one embodiment of the
present invention;
[0010] FIG. 3 is an enlarged, cross-sectional view at still a
subsequent stage of manufacture in accordance with one embodiment
of the present invention;
[0011] FIG. 4 is an enlarged, cross-sectional view at a subsequent
stage of manufacture in accordance with one embodiment of the
present invention; and
[0012] FIG. 5 is an enlarged, cross-sectional view at still a
subsequent stage of manufacture in accordance with one embodiment
of the present invention.
DETAILED DESCRIPTION
[0013] Referring to FIG. 1, a heavily doped semiconductor substrate
12 may be covered by a sacrificial, undoped, or lightly doped
epitaxial silicon layer 18. The layer 18 may be less than 500
Angstroms thick in one embodiment. A gate electrode structure
including a gate 16 formed over a gate dielectric 14 may be defined
on the epitaxial silicon layer 18.
[0014] The selective deposition of the sacrificial epitaxial
silicon layer 18 may be carried out, for example, using
dichlorosilane-based chemistry in a single wafer chemical vapor
deposition reactor, such as an Epsilon 3000 epitaxial reactor,
available from ASM International NV, Bilthoven, Netherlands. The
film may be deposited with gas flows of 150-200 sccm of
dichlorosilane, 100-150 sccm of HCl, 20 slm of H.sub.2 at
825.degree. C. in a processed pressure of 20 Torr. Under these
processing conditions, a deposition rate of 10-15 nanometers per
minute may be achieved for silicon on exposed substrate while
achieving selectivity to spacer and oxide regions. Other deposition
techniques may also be used.
[0015] The arrangement shown in FIG. 1 is sometimes called a delta
doped transistor. Because there is relatively high doping below the
epitaxial layer 18, a large delta or change in concentration occurs
at the interface between the substrate 12 and the epitaxial silicon
layer 18.
[0016] The structure shown in FIG. 1 may be covered by a spacer
material and then anisotropically etched to form the sidewall
spacers 28 shown in FIG. 2. Some limited etching of the epitaxial
silicon 18 may occur at the same time depending on the selectivity
of the spacer etch.
[0017] After spacer formation, a selective wet etch may remove the
exposed portions of the epitaxial silicon layer 18 and may continue
etching under the gate 16 to achieve the undercut structure shown
in FIG. 3. The extent of gate 16 undercut can be controlled by
adjusting the etch time.
[0018] The epitaxial silicon layer 18 may be selectively etched
with a variety of hydroxide-based solutions, for example. However,
for high selectivity of the undoped or lightly doped layer 18 to
the heavily doped substrate 12, relatively mild processing
conditions may be employed.
[0019] In one embodiment, an aqueous ammonium hydroxide solution in
the concentration range of 2 to 10 percent by volume at 20.degree.
C. may be used together with sonication. The sonication may be
provided by a transducer that dissipates ultra or megasonic energy
with a power of 0.5 to 5 watts per cm.sup.2 in one embodiment of
the present invention. Since the delta doped transistor has a
heavily doped region below the undoped region, it may serve as an
etch stop layer for the wet etch.
[0020] After the wet etch undercut, a doped selective epitaxial
silicon layer 50 may be grown. A shallow, highly doped source/drain
extension 50a laterally extends the desired distance under the gate
16 edge and the sidewall spacer 28, as shown in FIG. 4. A thicker
source/drain region 50b is aligned with the edge of the spacer 28
and extends away from the spacer 28. The spacer 28 enables the
length of the extension 50a to be tailored and allows the thickness
of the layer 50 to expand without shorting to the gate 16. The
thicker region 50b reduces resistance of the region 50 and brings
the lower resistance region close to the edge of the gate 16.
[0021] In forming the P-type MOS (PMOS) transistor, the
source/drain extension 50a and raised source/drain 50b may be
formed by selectively depositing epitaxial boron doped silicon or
silicon germanium with a germanium concentration of up to 30
percent, as one example. Under the processing conditions of 100
sccm of dichlorosilane, 20 slm H.sub.2, 750-800.degree. C., 20
Torr, 150-200 sccm HCl, diborane flow of 150-200 sccm and GeH.sub.4
flow of 150-200 sccm, a highly doped silicon germanium film with a
deposition rate of 20 nanometers per minute, a boron concentration
of 1E20 cm.sup.-3, and a germanium concentration of 20 percent may
be achieved in one embodiment. A low resistivity of 0.7-0.9 mOhm-cm
results from the high boron concentration of the film.
[0022] Low resistivity provide the benefit of high conductivity in
the extension and source/drain regions in some embodiments. This
lowered resistivity may reduce the external resistance. The larger
unit cell of the silicon germanium present in source/drain regions
50b may exert compressive strain on the channel, which in turn may
result in enhanced mobility and transistor performance in some
embodiments.
[0023] In the N-type transistor (NMOS), the source/drain 50b and
source/drain extension 50a may be formed using in situ phosphorus
doped silicon deposited in one embodiment. The silicon may be
deposited selectively under processing conditions of 100 sccm of
dichlorosilane, 25-50 sccm HCl, 200-300 sccm of 1 percent PH.sub.3
with a H.sub.2 gas carrier flow of 20 slm at 750.degree. C. and 20
Torr. A phosphorous concentration of 2E20 cm.sup.-3 with a
resistivity of 0.4-0.6 mOhm-cm may be achieved in the deposited
film in one embodiment.
[0024] Thereafter, a second thin spacer 34 may be formed using
conventional techniques as shown in FIG. 5. A deep source/drain 32
may be formed by ion implantation using the spacers 28 and 34 and
the gate 16 as a mask. The annealing of the deep source/drain 32
may be done in a way that reduces or minimizes the dopant diffusion
including the dopant in the layer 50.
[0025] The characteristics of the shallow source/drain extensions
50a and the degree by which they underlap the gate 16 may be
independent of the characteristics of the deep source/drain
junction 32. The extent of extension underlap of the gate 16 of the
source/drain extension 50a may be controlled as desired.
[0026] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
* * * * *