U.S. patent application number 10/905973 was filed with the patent office on 2006-08-03 for method of forming a mim capacitor for cu beol application.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Lawrence A. Clevenger, Timothy Joseph Dalton, Gerald R. Matusiewicz, Chih-Chao Yang.
Application Number | 20060170024 10/905973 |
Document ID | / |
Family ID | 36755603 |
Filed Date | 2006-08-03 |
United States Patent
Application |
20060170024 |
Kind Code |
A1 |
Yang; Chih-Chao ; et
al. |
August 3, 2006 |
METHOD OF FORMING A MIM CAPACITOR FOR CU BEOL APPLICATION
Abstract
The present invention relates generally to integrated circuits,
and particularly, but not by way of limitation,
metal-insulator-metal (MIM) capacitors formed within a trench
located within a metallization layer and in particular to MIM
capacitors for Cu BEOL semiconductor devices.
Inventors: |
Yang; Chih-Chao;
(Poughkeepsie, NY) ; Dalton; Timothy Joseph;
(Ridgefield, CT) ; Clevenger; Lawrence A.;
(LaGrangeville, NY) ; Matusiewicz; Gerald R.;
(Poughkeepsie, NY) |
Correspondence
Address: |
CONNOLLY BOVE LODGE & HUTZ LLP (IBM YORKTOWN)
1990 M STREET, NW
SUITE 800
WASHINGTON
DC
20036-3425
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
New Orchard Road
Armonk
NY
|
Family ID: |
36755603 |
Appl. No.: |
10/905973 |
Filed: |
January 28, 2005 |
Current U.S.
Class: |
257/301 ;
257/303; 257/306; 257/310; 257/532; 257/E21.009; 257/E21.011;
257/E21.582; 257/E27.048; 257/E27.071; 257/E27.092 |
Current CPC
Class: |
H01L 28/55 20130101;
H01L 28/60 20130101; H01L 21/76838 20130101 |
Class at
Publication: |
257/301 ;
257/303; 257/306; 257/310; 257/532; 257/E27.048; 257/E27.071;
257/E27.092 |
International
Class: |
H01L 29/94 20060101
H01L029/94; H01L 27/108 20060101 H01L027/108; H01L 29/00 20060101
H01L029/00 |
Claims
1. A metal-insulator-metal (MIN) capacitor for a Cu BEOL
semiconductor device comprising a bottom capacitor plate having a
trench defined therein; a top capacitor plate disposed within said
trench; a capacitor dielectric disposed between said capacitor
plates within said trench; a Cu diffusion barrier formed on said
bottom plate and disposed between said bottom plate and said
dielectric; a first electrode electrically connected to said bottom
plate; and a second electrode electrically connected to said top
plate.
2. (canceled)
3. The MIM capacitor, according to claim 1, wherein said Cu
diffusion barrier comprises a conductive material.
4. The MIN capacitor, according to claim 3, wherein said conductive
material is a metal selected from the group consisting of CoWP,
CoSnP, Pd, Ru, alloys thereof, and mixtures thereof.
5. The MIM capacitor, according to claim 1, further comprising a
conductive seed layer interposed between said capacitor dielectric
and said top plate.
6. The MIM capacitor, according to claim 5, wherein said conductive
seed layer comprises a metal selected from the group consisting of
Cu, Ru, alloys thereof and mixtures thereof.
7. The MIM capacitor, according to claim 1, wherein said bottom
plate is an electrically conductive material.
8. The MIM capacitor, according to claim 7, wherein said
electrically conductive material is a metal selected from the group
consisting of copper, aluminum, Al(Cu) alloys, W, Ru, alloys
thereof, and mixtures thereof.
9. The MIM capacitor, according to claim 8, wherein said bottom
plate is copper.
10. The MIM capacitor, according to claim 1, wherein said capacitor
dielectric is selected from the group consisting of
oxide-nitride-oxide, SiO.sub.2, TaO.sub.5,
PSiN.sub.xSi.sub.3N.sub.4, SiON, SiC, TaO.sub.2, ZrO.sub.2,
HfO.sub.2, Al.sub.2O.sub.3, and combination thereof.
11. The MIM capacitor, according to claim 1, wherein said top plate
is a metal selected from the group consisting of copper, Ta, TaN,
Ti, TiN, TiSiN, W, Ru, Al, alloys thereof, and mixtures
thereof.
12. The MIM capacitor, according to claim 1, wherein said first and
second electrodes are formed from a metal selected from the group
consisting of copper, Al, AlCu, Ti, TiN, Ta, TaN, W, WN, MoN, Pt,
Pd, Os, Ru, IrO2, ReO2, ReO3, alloys thereof and mixtures
thereof.
13-23. (canceled)
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to integrated
circuits, and particularly, but not by way of limitation,
metal-insulator-metal (MIM) capacitors formed within a trench
located within a metallization layer and in particular to MIM
capacitors for Cu BEOL semiconductor devices.
BACKGROUND
[0002] The information provided below is not admitted to be prior
art to the present invention, but is provided solely to assist the
understanding of the reader.
[0003] Metal-Insulator-Metal Capacitors (MIM Cap) have been
integrated in various integrated circuits for applications of
analog/logic, analog-to-digital, mixed signal, and radio frequency
circuits. The method of fabricating MIM Cap in the current 90 nm
technology is described with reference to FIGS. 1A-1G. As shown in
FIG. 1A, SiO.sub.2 (102) and Si.sub.3N.sub.4 (103) are deposited in
series on a wafer surface with interconnects (101) embedded in an
insulator layer 100. In FIG. 1B, the wafer is patterned with an
alignment mask to create alignment marks at kerf area 120. In FIGS.
1C and 1D, a first conductive TiN plate (104), a dielectric layer
(105), a second conductive TiN plate (106), and a passivation
Si.sub.3N.sub.4 layer (107) are sequentially deposited, and then
patterned by masking and etching to obtain a top-electrode (130) of
a capacitor. Another Si.sub.3N.sub.4 layer is then deposited on the
wafer, and then patterned by a third masking and etching to obtain
a bottom-electrode (150) and insulator (140) of the capacitor as
shown in FIGS. 1E and 1F. In FIG. 1G, another insular layer 109 is
deposited on the wafer, and then patterned to form electrical
contacts 160 and 170.
[0004] The above process of record for integrating MIM Cap into
back-end-of-line (BEOL) requires three extra masking and etching
steps to form the capacitors, which may increase overall
fabrication costs. Also, the capacitor-dielectric damage layer, as
shown in FIG. 2, resulting from top-electrode over-etch and the
poor adhesion between SiN/Cu and SiN/TiN interfaces can cause
reliability concerns. Moreover, the capacitor-dielectric thickness
is required to be thicker than 500 A in order to ensure sufficient
process window during top-electrode etch. This requirement limits
the extendibility of the process to next technology generations.
Furthermore, the high resistivity electrode material, TiN, limits Q
factor of the MIM Cap.
[0005] A method of manufacturing a capacitor with a compatible
copper process is disclosed in U.S. Pat. No. 6,461914, FIG. 3.
However, extra masking and etching steps are required to form the
capacitors. Moreover, the capacitor-dielectric layer existing in
non-capacitor area will increase the overall structure capacitance,
which can increase the interconnect RC delay. Furthermore, the high
resistivity electrode material, TaN, limits Q factor of the MIM
Cap.
[0006] Consequently, products containing MIM capacitors formed by
conventional methods are economically uncompetitive in view of
their high costs and poor performance. Therefore, a need exists for
lower-cost MIM capacitors, formed by methods that result in less
damage.
[0007] Other objects and advantages will become apparent from the
following disclosure.
SUMMARY OF THE INVENTION
[0008] The present invention provides a structure and corresponding
methods for MIM capacitors in semiconductor devices. An aspect of
the present invention provides a metal-insulator-metal (MIM)
capacitor for a Cu BEOL semiconductor device comprising a bottom
capacitor plate having a trench defined therein; a top capacitor
plate disposed within said trench; a capacitor dielectric disposed
between said capacitor plates within said trench; a first electrode
electrically connected to said bottom plate; and a second electrode
electrically connected to said top plate.
[0009] According to a preferred aspect, the inventive MIM capacitor
further comprises a Cu diffusion barrier formed on said bottom
plate and disposed between said bottom plate and said dielectric.
According to a more preferred aspect, the Cu diffusion barrier is
formed of CoWP.
[0010] According to an aspect the bottom capacitor plate is a metal
selected from the group consisting of copper, aluminum, or other
electrical conductive materials. Acording to a preferred aspect,
the bottom capacitor plate is copper.
[0011] According to an aspect the inventive MIM capacitor comprises
a capacitor dielectric disposed between two regions of
metallization. According to an aspect, the capacitor dielectric is
selected from the group consisting of oxide-nitride-oxide,
SiO.sub.2, TaO.sub.5, PSiN.sub.xSi.sub.3N.sub.4, SiON, SiC,
TaO.sub.2, ZrO.sub.2, HfO.sub.2, Al.sub.2O.sub.3, and combination
thereof. According to a preferred aspect, the capacitor dielectric
preferably comprises high-k materials, eg. TaO.sub.5, TaO2, ZrO2,
HfO.sub.2.
[0012] According to an aspect the top plate of the inventive MIM
capacitor is a metal selected from the group consisting of copper,
Ta, TaN, Ti, TiN, TiSiN, W, Ru, Al, alloys thereof, and mixtures
thereof. According to a preferred aspect, the top capacitor plate
preferably comprises copper.
[0013] According to an aspect the first and second electrodes of
the inventive MIM capacitor are formed from a metal selected from
the group consisting of copper, Al, AlCu, Ti, TiN, Ta, TaN, W, WN,
MoN, Pt, Pd, Os, Ru, IrO.sub.2, ReO.sub.2, ReO.sub.3, alloys
thereof and mixtures thereof. According to a preferred aspect, the
first and second electrodes are formed of the same metal. According
to a more preferred aspect, the electrodes are formed from
copper.
[0014] According to an aspect the present invention provides a
method of fabricating a MIM capacitor for a Cu BEOL semiconductor
device. According to an aspect the method comprises providing a
semiconductor wafer; providing a first dielectric layer on said
wafer; forming a first metallization in said dielectric, wherein an
upper surface of said first metallization and an upper surface of
said first dielectric form a substantially coplanar surface;
forming a dielectric film on said coplanar surface; masking and
etching a trench through said film into said first metallization;
forming an intermetal dielectric layer over said first
metallization in said trench; forming a second metalization over
said intermetal dielectric in said trench wherein an upper surface
of said second metallization and an upper surface of said first
dielectric form a substantially coplanar surface; forming a layer
of a second dielectric on said coplanar surface; forming a first
electrode in said second dielectric in electrical contact with said
first metallization; and forming a second electrode in said second
dielectric in electrical contact with said second
metallization.
[0015] According to a preferred aspect, the inventive method of
fabricating an MIM capacitor further comprises forming a Cu
diffusion barrier on said first metallization and disposed between
said first metallization and said intermetal dielectric. According
to a more preferred aspect, the Cu diffusion barrier is formed of
CoWP.
[0016] According to an aspect, the present invention provides an
MIM capacitor fabricated according to the inventive method.
[0017] Still other aspects and advantages of the present invention
will become readily apparent by those skilled in the art from the
following detailed description, wherein it is shown and described
preferred embodiments of the invention, simply by way of
illustration of the best mode contemplated of carrying out the
invention. As will be realized the invention is capable of other
and different embodiments, and its several details are capable of
modifications in various obvious respects, without departing from
the invention. Accordingly, the description is to be regarded as
illustrative in nature and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The invention is best understood from the following detailed
description when read in connection with the accompanying drawing.
It is emphasized that, according to common practice, the various
features of the drawing are not to scale. On the contrary, the
dimensions of the various features are arbitrarily expanded or
reduced for clarity. Included in the drawing are the following
figures:
[0019] FIG. 1 is a schematic of a conventional MIM capacitor
fabrication method;
[0020] FIG. 2 is a micrograph illustrating damage to a MIM
capacitor fabricated by conventional methods;
[0021] FIG. 3 is a schematic of a conventional MIM capacitor
disclosed in U.S. Pat. No. 6,461,914;
[0022] FIG. 4 is a micrograph illustrating the results of the
process step of FIG. 7;
[0023] FIG. 5 is a schematic illustrating a process step of the
present invention;
[0024] FIG. 6 is a schematic illustrating a process step of the
present invention;
[0025] FIG. 7A is a schematic illustrating a process step of the
present invention;
[0026] FIG. 8A is a schematic illustrating a process step of the
present invention;
[0027] FIG. 8B is a micrograph illustrating the result of the
process step of FIG. 8A;
[0028] FIG. 9 is a schematic illustrating a process step of the
present invention;
[0029] FIG. 10 is a schematic illustrating a process step of the
present invention; and
[0030] FIG. 11 is a schematic illustrating the inventive MIM
capacitor following the final process step of the inventive
method.
[0031] It is to be noted, however, that the appended drawings
illustrate only typical embodiments of this invention and are
therefore not to be considered limiting of its scope, for the
invention may admit to other equally effective embodiments.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENT
[0032] Reference is made to the figures to illustrate selected
embodiments and preferred modes of carrying out the invention. It
is to be understood that the invention is not hereby limited to
those aspects depicted in the figures. It is understood that
similar numerals in the various figures refer to equivalent
features.
[0033] With reference to FIG. 5, fabrication of the inventive MIM
capacitor starts from a wafer having an insulator layer 501
deposited thereon. The wafer further includes metallic circuit
elements 502 and 504 formed within layer 501. Preferably, circuit
elements 502 and 504 are copper and preferably circuit elements 502
and 504 were formed using conventional damascene and dual damascene
techniques. It is preferred that the upper surface of circuit
element 504 be flush with and coplanar to the surface of insulator
layer 501. The upper, exposed surface, defined by the wafer and any
feature built thereon, may be known as the wafer surface. A
dielectric film 503 is then deposited on the wafer surface. Film
503 is advantageously chosen from Si.sub.3N.sub.4, SiC, SiO.sub.2.
However, the film is not limited to the listed materials, but may
be chosen from any suitable insulator. Film 503 may be applied by
any suitable method known to the art.
[0034] Referring to FIG. 6, the dielectric film 603 is patterned by
masking and etching to define an area 610 in which to locate the
MIM capacitor. Etching film 603 exposes Cu interconnect 604 to form
the bottom-electrode of the capacitor. The bottom electrode may be
termed the first metallization.
[0035] Referring to FIG. 7, a trench 710 is formed by etching
portions of metal 704. Etching is advantageously performed by wet
etch processes known to the art using acids such as, but not
limited to HNO.sub.3, HCl, H.sub.2SO.sub.4, HF, and combinations
thereof. FIG. 4 is a micrograph illustrating the method through the
process of FIG. 7.
[0036] FIG. 8 relates to preferred embodiments wherein the exposed
surface of the copper conductor 804 is selectively capped with a
layer 805 of CoWP which serves both as a passivation and Cu
diffusion barrier layer. Preferably, the CoWP layer thickness is
between 50 and 300 .ANG.. The passivation and copper diffusion
barrier functions may be serve by materials such as CoSnP, Pd, Ru.
The passivation layer may be applied by any technique standard to
the art.
[0037] Referring to FIG. 9, a layer of a capacitor dielectric 906
is applied over conductor 904 or the optional passivation layer
905. The capacitor dielectric may be termed an intermetal
dielectric. The capacitor dielectric may advantageously be chosen
from any suitable insulator including, but not limited to
oxide-nitride-oxide, SiO.sub.2, TaO.sub.5,
PSiN.sub.xSi.sub.3N.sub.4, SiON, SiC, TaO.sub.2, Zro.sub.2,
HfO.sub.2, Al.sub.2O.sub.3, and mixtures thereof. The capacitor
dielectric may be applied by any suitable technique known to the
art. Preferably, the capacitor dielectric layer thickness is
between 50 and 10,00 .ANG..
[0038] Following application of the capacitor dielectric, the
various dielectric surfaces may be coated with a thin layer of a
conductive seed material, such as, but not limited to Cu and Ru.
The application may be performed by standard techniques, including,
but not limited to, PVD, CVD, or ALD deposition technologies. The
optional seed layer is not indicated in the figure.
[0039] A conductive layer 907 of a metal or alloy such as, but not
limited to Ta, TaN, Ti, TiN, TiSiN, W, Ru, Cu, Al, and mixtures
thereof is deposited on top of the wafer. The deposition methods
may be, but is not limited to, PVD, CVD, electroplating,
electroless plating, and spin-on processes. Preferably, the
thickness of the conductive layer is between 200 and 10,000 .ANG..
Layer 907 may be termed the top capacitor plate or the second
metallization.
[0040] Referring to FIG. 10, the capacitor is planarized by an
appropriate process, such as CMP stopping on film 1003.
[0041] The process is completed in FIG. 11. An insulation layer
1108 is deposited on the wafer. Preferably, the dielectric layer is
composed of oxide and has preferably a thickness between 500 and
10,000 .ANG.. Layer 1108 is masked, etched and filled with an
electrode material to form electrical contacts 1120 to the top
capacitor plate and 1130 to the bottom capacitor plate. Electrical
contacts 1120 and 1130 are preferably copper, but may be any
suitable conductor including, but not limited to Cu, Al, AlCu, Ti,
TiN, Ta, TaN, W, WN, MoN, Pt, Pd, Os, Ru, IrO.sub.2, ReO.sub.2,
ReO.sub.3, alloys thereof, and mixtures thereof.
[0042] It will, therefore, be appreciated by those skilled in the
art having the benefit of this disclosure that this invention is
capable of producing a MIM capacitor for Cu BEOL application.
Although the illustrative embodiments of the invention are drawn
from the semiconductor arts, the invention is not intrinsically
limited to that art. Furthermore, it is to be understood that the
form of the invention shown and described is to be taken as
presently preferred embodiments. Various modifications and changes
may be made to each and every processing step as would be obvious
to a person skilled in the art having the benefit of this
disclosure. It is intended that the following claims be interpreted
to embrace all such modifications and changes and, accordingly, the
specification and drawings are to be regarded in an illustrative
rather than a restrictive sense. Moreover, it is intended that the
appended claims be construed to include alternative
embodiments.
INCORPORATION BY REFERENCE
[0043] All publications, patents, and pre-grant patent application
publications cited in this specification are herein incorporated by
reference, and for any and all purposes, as if each individual
publication or patent application were specifically and
individually indicated to be incorporated by reference. In the case
of inconsistencies the present disclosure will prevail.
* * * * *