DALTON; Timothy Joseph

Patent Applications and Registrations

Patent applications and USPTO patent grants for DALTON; Timothy Joseph.The latest application filed is for "low temperature bi-cmos compatible process for mems rf resonators and filters".

Company Profile

0.33.41

DALTON; Timothy Joseph - Ridgefield CT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low Temperature Bi-cmos Compatible Process For Mems Rf Resonators And Filters App 20120270351 - BUCHWALTER; Leena Paivikki ; et al.	2012-10-25
Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters Grant 8,269,291 - Buchwalter , et al. September 18, 2	2012-09-18
Structures for semiconductor structures with error detection and correction Grant 8,146,046 - Dalton , et al. March 27, 2	2012-03-27
Double-sided Integrated Circuit Chips App 20110302542 - Bernstein; Kerry ; et al.	2011-12-08
Double-sided Integrated Circuit Chips App 20110241082 - Bernstein; Kerry ; et al.	2011-10-06
Double-sided integrated circuit chips Grant 8,013,342 - Bernstein , et al. September 6, 2	2011-09-06
Dual wired integrated circuit chips Grant 7,960,245 - Bernstein , et al. June 14, 2	2011-06-14
Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters Grant 7,943,412 - Buchwalter , et al. May 17, 2	2011-05-17
Low Temperature BI-CMOS Compatible Process For MEMS RF Resonators and Filters App 20110109405 - Buchwalter; Leena Paivikki ; et al.	2011-05-12
Dual wired integrated circuit chips Grant 7,939,914 - Bernstein , et al. May 10, 2	2011-05-10
Phase change memory element with a peripheral connection to a thin film electrode Grant 7,923,712 - Arnold , et al. April 12, 2	2011-04-12
Modified via bottom structure for reliability enhancement Grant 7,906,428 - Clevenger , et al. March 15, 2	2011-03-15
Semiconductor integrated circuit devices having high-Q wafer back-side capacitors Grant 7,851,321 - Clevenger , et al. December 14, 2	2010-12-14
Double-sided integrated circuit chips Grant 7,670,927 - Bernstein , et al. March 2, 2	2010-03-02
Method for delineation of phase change memory cell via film resistivity modification App 20100001253 - Arnold; John Christopher ; et al.	2010-01-07
Dual Wired Integrated Circuit Chips App 20090121287 - Bernstein; Kerry ; et al.	2009-05-14
Double-sided Integrated Circuit Chips App 20090121260 - Bernstein; Kerry ; et al.	2009-05-14
Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same Grant 7,531,407 - Clevenger , et al. May 12, 2	2009-05-12
Semiconductor Integrated Circuit Devices Having High-Q Wafer Back-Side Capacitors App 20090111235 - Clevenger; Lawrence ; et al.	2009-04-30
Low temperature bi-CMOS compatible process for MEMS RF resonators and filters App 20090108381 - Buchwalter; Leena Paivikki ; et al.	2009-04-30
Error detection and correction in semiconductor structures Grant 7,526,698 - Dalton , et al. April 28, 2	2009-04-28
Semiconductor integrated circuit devices having high-Q wafer back-side capacitors Grant 7,473,979 - Clevenger , et al. January 6, 2	2009-01-06
Modified Via Bottom Structure For Reliability Enhancement App 20080220608 - Clevenger; Lawrence A. ; et al.	2008-09-11
Dual Wired Integrated Circuit Chips App 20080213948 - Bernstein; Kerry ; et al.	2008-09-04
Design Structures For Semiconductor Structures With Error Detection And Correction App 20080216031 - Dalton; Timothy Joseph ; et al.	2008-09-04
Method Of Forming An Interconnect Structure App 20080146029 - Baks; Heidi Lee ; et al.	2008-06-19
Dual Wired Integrated Circuit Chips App 20080128812 - Bernstein; Kerry ; et al.	2008-06-05
Dual wired integrated circuit chips Grant 7,381,627 - Bernstein , et al. June 3, 2	2008-06-03
Interconnect structures and methods of making thereof Grant 7,365,001 - Yang , et al. April 29, 2	2008-04-29
Method of forming an interconnect structure Grant 7,358,182 - Baks , et al. April 15, 2	2008-04-15
Porous Silicon Composite Structure As Large Filtration Array App 20080083697 - Dalton; Timothy Joseph ; et al.	2008-04-10
Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gaseous additions Grant 7,344,965 - Zhang , et al. March 18, 2	2008-03-18
Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same App 20080020488 - Clevenger; Lawrence ; et al.	2008-01-24
Modified Via Bottom Structure For Reliability Enhancement App 20070281469 - Clevenger; Lawrence A. ; et al.	2007-12-06
Semiconductor integrated circuit devices having high-Q wafer back-side capacitors App 20070278619 - Clevenger; Lawrence ; et al.	2007-12-06
Dual Wired Integrated Circuit Chips App 20070267698 - Bernstein; Kerry ; et al.	2007-11-22
Double-sided Integrated Circuit Chips App 20070267723 - Bernstein; Kerry ; et al.	2007-11-22
Phase change memory element with a peripheral connection to a thin film electrode and method of manufacture thereof App 20070252127 - Arnold; John Christopher ; et al.	2007-11-01
Dual wired integrated circuit chips Grant 7,285,477 - Bernstein , et al. October 23, 2	2007-10-23
Error Detection And Correction In Semiconductor Structures App 20070241398 - Dalton; Timothy Joseph ; et al.	2007-10-18
Porous silicon composite structure as large filtration array Grant 7,282,148 - Dalton , et al. October 16, 2	2007-10-16
Modified via bottom structure for reliability enhancement Grant 7,282,802 - Clevenger , et al. October 16, 2	2007-10-16
Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer Grant 7,241,696 - Clevenger , et al. July 10, 2	2007-07-10
Method of forming an interconnect structure App 20070148966 - Baks; Heidi Lee ; et al.	2007-06-28
Wafer-to-wafer Alignments App 20070132067 - Dalton; Timothy Joseph ; et al.	2007-06-14
Wafer-to-wafer alignments Grant 7,193,423 - Dalton , et al. March 20, 2	2007-03-20
Nano-scaled gate structure with self-interconnect capabilities Grant 7,115,921 - Clevenger , et al. October 3, 2	2006-10-03
Multilayer interconnect structure containing air gaps and method for making Grant 7,098,476 - Babich , et al. August 29, 2	2006-08-29
Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gases additions App 20060183308 - Zhang; Ying ; et al.	2006-08-17
Method Of Forming A Mim Capacitor For Cu Beol Application App 20060170024 - Yang; Chih-Chao ; et al.	2006-08-03
Line level air gaps Grant 7,084,479 - Chen , et al. August 1, 2	2006-08-01
Deep filled vias Grant 7,060,624 - Andricacos , et al. June 13, 2	2006-06-13
High Ion Energy And Reative Species Partial Pressure Plasma Ash Process App 20060105576 - Fuller; Nicholas Colvin Masi ; et al.	2006-05-18
Modified via bottom structure for reliability enhancement App 20060081986 - Clevenger; Lawrence A. ; et al.	2006-04-20
Method for dry etching photomask material Grant 7,014,958 - Dalton , et al. March 21, 2	2006-03-21
Nano-scaled gate structure with self-interconnect capabilities App 20060043435 - Clevenger; Lawrence A. ; et al.	2006-03-02
Line level air gaps App 20050127514 - Chen, Shyng-Tsong ; et al.	2005-06-16
Interconnect structures and methods of making thereof App 20050127511 - Yang, Chih-Chao ; et al.	2005-06-16
Porous silicon composite structure as large filtration array App 20050092676 - Dalton, Timothy Joseph ; et al.	2005-05-05
Deep filled vias App 20050037608 - Andricacos, Panayotis ; et al.	2005-02-17
Multilayer interconnect structure containing air gaps and method for making App 20050037604 - Babich, Katherina E. ; et al.	2005-02-17
Method For Dry Etching Photomask Material App 20040265703 - Dalton, Timothy Joseph ; et al.	2004-12-30
Method for forming a porous dielectric material layer in a semiconductor device and device formed Grant 6,831,364 - Dalton , et al. December 14, 2	2004-12-14
Multilayer interconnect structure containing air gaps and method for making Grant 6,815,329 - Babich , et al. November 9, 2	2004-11-09
Diffusion barrier layer and semiconductor device containing same Grant 6,784,485 - Cohen , et al. August 31, 2	2004-08-31
Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer App 20040115921 - Clevenger, Larry ; et al.	2004-06-17
Spin-on cap layer, and semiconductor device containing same Grant 6,724,069 - Dalton , et al. April 20, 2	2004-04-20
Semiconductor recessed mask interconnect technology App 20040051178 - Cohen, Stephen Alan ; et al.	2004-03-18
Semiconductor recessed mask interconnect technology Grant 6,657,305 - Cohen , et al. December 2, 2	2003-12-02
Method for forming a porous dielectric material layer in a semiconductor device and device formed App 20030057414 - Dalton, Timothy Joseph ; et al.	2003-03-27
Multilayer interconnect structure containing air gaps and method for making App 20020158337 - Babich, Katherina E. ; et al.	2002-10-31
Spin-on cap layer, and semiconductor device containing same App 20020145200 - Dalton, Timothy Joseph ; et al.	2002-10-10
Method for forming a porous dielectric material layer in a semiconductor device and device formed Grant 6,451,712 - Dalton , et al. September 17, 2	2002-09-17
Method for forming a porous dielectric material layer in a semiconductor device and device formed App 20020074659 - Dalton, Timothy Joseph ; et al.	2002-06-20