U.S. patent application number 11/057176 was filed with the patent office on 2005-07-07 for single reactor, multi-pressure chemical vapor deposition for semiconductor devices.
This patent application is currently assigned to IBM Corporation (Burlington). Invention is credited to Chu, Jack O., Jagannathan, Basanth, Wuthrich, Ryan Wayne.
Application Number | 20050145172 11/057176 |
Document ID | / |
Family ID | 24742529 |
Filed Date | 2005-07-07 |
United States Patent
Application |
20050145172 |
Kind Code |
A1 |
Chu, Jack O. ; et
al. |
July 7, 2005 |
Single reactor, multi-pressure chemical vapor deposition for
semiconductor devices
Abstract
An apparatus and method for forming at least a portion of an
electronic device include a High Vacuum-Chemical Vapor Deposition
(UHV-CVD) system and a Low Pressure-Chemical Vapor Deposition
(LPCVD) system using a common reactor. The invention overcomes the
problem, of silicon containing wafers being dipped in HF acid prior
to CVD processing, and the problem of surface passivation between
processes in multiple CVD reactors.
Inventors: |
Chu, Jack O.; (Manhasset
Hills, NY) ; Jagannathan, Basanth; (Beacon, NY)
; Wuthrich, Ryan Wayne; (Burlington, VT) |
Correspondence
Address: |
CONNOLLY BOVE LODGE & HUTZ LLP
IBM MICROELECTRONICS DIVISION
1990 M STREET NW, SUITE 800
WASHINGTON
DC
20036-3425
US
|
Assignee: |
IBM Corporation
(Burlington)
Essex Junction
VT
|
Family ID: |
24742529 |
Appl. No.: |
11/057176 |
Filed: |
February 15, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11057176 |
Feb 15, 2005 |
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09683088 |
Nov 16, 2001 |
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6875279 |
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Current U.S.
Class: |
118/719 ;
427/248.1 |
Current CPC
Class: |
Y10T 117/10 20150115;
C30B 25/08 20130101; C23C 16/4412 20130101; C30B 25/14 20130101;
C23C 16/54 20130101 |
Class at
Publication: |
118/719 ;
427/248.1 |
International
Class: |
C23C 016/00; C23C
016/24 |
Claims
1-12. (canceled)
13. A method for forming at least a portion of a semiconductor
device, said method comprising steps of: heating in a reaction
chamber a substrate on which said semiconductor device is to be
formed; supplying a first treating gas to said reaction chamber
from a first gas source; maintaining said reaction chamber at a
first vacuum pressure with a first pumping system during the
supplying of said first treating gas to said reaction chamber;
stopping the supplying of said first treating gas and supplying a
second treating gas to said reaction chamber from a second gas
source; maintaining said reaction chamber at the first vacuum
pressure with the first pumping system during the supplying of said
second treating gas to said reaction chamber, supplying a third
treatment gas and transitioning said reaction chamber between said
first vacuum pressure and said second vacuum pressure using a third
pumping system; and supplying a fourth treatment gas at a second
pressure and temperature.
14. A method according to claim 13, wherein said first treating gas
and said first vacuum pressure in said reaction chamber provide a
low pressure chemical vapor deposition of a layer of silicon on
said substrate.
15. A method according to claim 14, wherein said first vacuum
pressure is in the range of 100 to 500 mT.
16. A method according to claim 14, wherein said fourth treating
gas and said second vacuum pressure in said reaction chamber
provide an ultra high vacuum deposition of a layer of Ge, Si or
SiGe on said substrate.
17. A method according to claim 16, wherein said second vacuum
pressure is in the range of about 0.1 to 1.0 mT.
18. A method according to claim 13, wherein said fourth treating
gas and said second vacuum pressure in said reaction chamber
provide an ultra high vacuum deposition of a layer of Ge, Si or
SiGe on said substrate.
19. A method according to claim 13, wherein said third pumping
system is coupled to said reaction chamber and comprises a cryopump
and a scroll pump arranged in series to remove contaminates from
said reaction chamber after the supplying of said first treating
gas.
20. A method according to claim 13, wherein said first pumping
system comprises a roots blower and a mechanical pump in series;
wherein said second pumping system comprises a turbomolecular pump,
a roots blower and a mechanical pump in series; and wherein said
first pumping system and said second pumping system share the same
roots blower and mechanical pump.
Description
FIELD OF THE INVENTION
[0001] This invention relates to semiconductor process equipment
and methods, and more particularly, to Chemical Vapor Deposition
(CVD) apparatuses and methods for performing a plurality of in situ
processes for forming all or portions of an electronic device.
BACKGROUND OF THE INVENTION
[0002] Present Chemical Vapor Deposition Equipment consists of
multiple chambers, gas inlets, gas outlets, vacuum pumps and
transfer load-lock systems for inserting, for example,
semiconductor wafers into the chambers. Examples of Chemical Vapor
Deposition Equipment are described in U.S. Pat. No. 5,259,918
issued on Nov. 9, 1993, which shows an Ultra High Vacuum Chemical
Vapor Deposition (UHV-CVD) reactor with a vacuum loading chamber;
and in U.S. Pat. No. 6,013,134 issued on Jan. 11, 2000, which shows
a UHV transfer system for transferring wafers between a UHV-CVD
reactor and a Low Pressure-Chemical Vapor Deposition (LPCVD)
reactor. The entire contents of both of these patents are
incorporated herein by reference.
[0003] In the growth of Si structures or Si/SiGE heterostructures
via UHV-CVD processing according to the prior art, a critical step
and requirement before loading wafers into the UHV-CVD equipment is
to perform a dip of each Si containing wafer into hydrofluoric (HF)
acid to remove the native oxide from the wafer surface and to
passivate the Si bonds at the surface with hydrogen. Si containing
wafers after being dipped in HF acid are loaded into a vacuum
loading apparatus of a CVD reactor and then inserted into the CVD
reactor. This particular HF cleaning procedure is a hazardous
practice to be performed manually under a chemical hood and
moreover, for patterned wafers, often there is residual HF liquid
left on the wafer surface which would require removal before
continuing to process the wafers. Removing residual liquid HF is an
extremely hazardous manual process. Presently, this HF-dip is not
an industry acceptable process and weakens the acceptance of the
UHV-CVD processing technique for doing low temperature epitaxy in
the semiconductor manufacturing industry.
[0004] Another key issue related to making high performance Si
and/or Si/SiGE Metal Oxide Silicon (MOS) field effect transistor
(FET) structures and/or Complementary Metal Oxide Silicon (CMOS)
structures is the requirement for a very high quality gate
dielectric and a gate electrode stack as described in U.S. Pat. No.
5,534,713 by K. Ismail et al. which issued Jul. 9, 1996, and the
entire contents of which are incorporated herein by reference. This
patent describes a gate dielectric of an ultra-thin SiO.sub.2 layer
with a thickness from 1 nm to 5 nm. The gate electrode is a heavily
doped polysilicon structure.
[0005] A typical problem of the prior art is that reactors and
related chambers are built to operate within a limited operating
pressure determined by the capacity of mass flow controllers and
the speed of the pump package. In many CVD applications, the vapor
deposited film is homogeneous, and therefore a single operating
point may be adequate. However, in some applications, where the
deposited continuous film is made of multiple layers containing
varying amounts of alloys, dopants, or other constituents, a
variety of operating conditions may prove useful for improving
productivity, film quality, and/or process control. For instance, a
portion of the deposited film may require UHV-CVD conditions to
reduce the defect density and improve process control. However,
UHV-CVD deposition of an entire film may be so slow as to be
unproductive. On the other hand, non-sensitive portions of a CVD
film could be deposited with greater speed by rapidly increasing
the operating temperature and pressure, thereby greatly improving
the total productivity of a CVD apparatus.
[0006] In addition, prior art UHV-CVD processes have generally
compromised the productivity of coupled UHV-CVD and LPCVD processes
by the steps introduced to satisfy the UHV-CVD segment, which is
the most sensitive. Alternatively, the UHV-CVD and the LPCVD
processes have been segmented such that the different layers are
each grown in a dedicated chamber.
SUMMARY OF THE INVENTION
[0007] The present invention provides a means to combine elements
of the UHV-CVD and LPCVD processes to improve the productivity of a
UHV-CVD system. In accordance with the present invention, an
apparatus and a method are described for forming the semiconductor
portion of CMOS, MODFET's, MOSFET's, MEMT's, NPN's and the like,
along with any desired gate structure such as an ultra thin gate
oxide and/or with a heavily doped polysilicon gate electrode layer
to be subsequently patterned. The apparatus is an Advanced
Integrated Chemical Vapor Deposition (AICVD) System having a single
reaction chamber that may be operated as part of an Ultra High
Vacuum-Chemical Vapor Deposition (UHV-CVD) System, a Low Pressure
Chemical Vapor (LPCVD) Deposition System, and a vacuum transfer
system for loading wafers from the external ambient. The vacuum
transfer system includes a load-lock section for the transfer of
wafers from the external ambient to an evacuated section that may
remain at vacuum pressures. The evacuated section includes a single
tube reactor operated as a Low Pressure/Ultra High Vacuum (LP/UHV)
evacuation chamber.
[0008] The invention further comprises a low mass, rapid heating
furnace in combination with three pumping packages. The three
pumping packages are preferably (1) a roots blower backed by
mechanical pump, (2) a turbomolecular pump backed by a roots blower
and a mechanical pump, and (3) a cryopump backed by a scroll pump.
By having three pumping packages communicating with the same
reactor tube, each pumping package with the ability to be isolated
from the reactor with a corresponding gate valve, operation of the
apparatus may be rapidly transitioned from an LP vacuum (100 to 500
mtorr) process to an ultra high vacuum (0.1 to 1.0 mtorr) process.
Since the wafers being treated are maintained under a vacuum in the
same reactor environment, the transition between depositing
sequential film layers may be seamless and defect free, while
providing maximum productivity.
[0009] The apparatus and method of the invention also provides
precise control of transitions from the LPCVD process to the
UHV-CVD process to prevent formation of deleterious defects. For
this purpose, isolation valves are provided to isolate the roots
blowers and mechanical pumps from the reaction chamber until the
appropriate pressure has been attained in that chamber. An
improvement in this transition is then realized by drawing a vacuum
on the chamber with a cryopump to remove any residual water
moisture or dopant related contaminants prior to completing the
transition to a UHV-CVD process from a LPCVD process. Because of
this, there is no need for process steps to "passivate" the Si
surface with H.sub.2. Instead, the invention maintains an
atomically clean surface during transitions between the LPCVD
process and the UHV-CVD process by means of reducing the oxidizing
agents to insignificant levels using a cryopump.
[0010] The cryopump provides particular benefits during the
transition from LPCVD to UHV-CVD processes. Although it is possible
to transition from LPCVD to UHV-CVD without the cryopump, the
environment would be contaminated with residual species from the
LPCVD process which are not efficiently removed by a turbomolecular
pump The cryopump is proficient at removing H.sub.2O, O.sub.2, B,
As, P, and other species that otherwise could accumulate on the Si
surface, react with the Si surface or otherwise degrade the quality
or prevent formation of the subsequent epitaxial film. Of
particular importance is the transition from moderate epitaxy
temperatures (approximately 700.degree. C.) to low epitaxy
temperatures (about 650.degree. C. or lower) where, if sufficient
partial pressures of O.sub.2 and H.sub.2O exist, oxides of Si can
readily form on the Si surface of the wafer. A cryopump is best
suited for this application due to the low volume gas load and the
broad range of effectively pumped gases.
[0011] The invention further provides methods of using the
apparatus arrangements for prebanking a silicon substrate surface
in hydrogen, growing a silicon containing layer with a first gas,
switching the first gas to a second gas such as SiH.sub.4 or
SiH.sub.6, and reducing the growth temperature to below 400.degree.
C.
[0012] The invention further provides methods of using the
apparatus arrangements for continuous epitaxial growth on a
semiconductor substrate in a single reactor comprising the steps of
growing an epitaxial layer on the semiconductor substrate under
first growth conditions, interrupting the growth of the epitaxial
layer, introducing flowing H.sub.2 to provide a reducing
environment and then transitioning to UHV-CVD conditions using the
combination of the cryopump system and the turbomolecular pump
system before lowering the growth temperature below 650.degree. C.
The growth of epitaxial silicon is resumed under second growth
conditions achieved by a turbomolecular pumped UHV-CVD process
below 650.degree. C.
[0013] The invention further provides changing the first growth
conditions to second growth conditions in the same reactor chamber
and restarting growth on the surface of the epitaxial layer under
the second growth conditions, such as by lowering the temperature
below 650.degree. C. under a cryopump assisted UHV-CVD process.
[0014] The invention further provides methods of using the
apparatus arrangements for continuous epitaxial growth on a
semiconductor substrate in a single reactor comprising the steps of
growing an epitaxial layer under first growth (e.g., LPCVD)
conditions, interrupting the growth of the epitaxial layer,
transitioning to second growth (e.g. UHV-CVD) conditions using the
combination of the cryopump and the turbomolecular pump to maintain
a controlled gaseous environment before lowering the temperature to
a second growth temperature below 650.degree. C., and restarting
continuous growth on the surface of the epitaxial layer under the
second growth conditions, such as by flowing a silicon containing
gas over the substrate and maintaining the temperature below
650.degree. C. The controlled gaseous environment herein is an
environment that may include hydrogen and exclude contaminants such
as O.sub.2, CO.sub.2, CO, H.sub.2 O, CH.sub.4, and other
hydrocarbons and gases such as mentioned as contaminants in U.S.
Pat. No. 5,298,452 issued on Mar. 29, 1994, the entire contents of
this patent being incorporated herein by reference. The partial
pressure of all contaminants are maintained at pressures below
10.sup.-8 Torr.
[0015] The invention further provides methods of using the
apparatus arrangements for forming a silicon/silicon oxide
interface with low interface traps comprising the steps of growing
a silicon containing layer on a substrate with a first gas in a
reaction chamber at a first growth temperature, switching the first
gas to a second gas such as H.sub.2 while transitioning to a second
growth temperature, introducing a third set of gases such as
SiH.sub.4 with NO.sub.2 or O.sub.2, and growing a silicon oxide
layer on the surface at the second growth temperature.
[0016] The invention further provides methods of using the
apparatus arrangements for fabricating silicon containing epitaxial
layers comprising the steps of a placing a semiconductor substrate
into a reaction chamber, removing any native oxide from the surface
of the semiconductor substrate by baking in the range from
850.degree. C. to 900.degree. C. for less than 30 minutes with
hydrogen gas flowing thereover, forming a medium/high temperature
silicon containing epitaxy layer on the surface of the
semiconductor substrate at a first growth temperature in the range
of 700.degree. C. to 850.degree. C. under LPCVD conditions before
flowing a hydrogen containing gas in the reaction chamber, followed
by transitioning to UHV/CVD conditions using a combination of the
cryopump system and the turbomolecular pump system before reducing
the reaction chamber temperature to below 650.degree. C., forming
an epitaxial layer on the semiconductor substrate suitable for the
channel of a FET or the base of an NPN transistor, maintaining the
reaction chamber under a controlled gaseous environment (e.g.,
H.sub.2) while changing it to a third growth temperature and LPCVD
conditions forming a gate oxide or base oxide on the upper surface
of the semiconductor substrate, maintaining the reaction chamber
under a controlled gaseous environment (e.g., H.sub.2) while
changing it to the fourth growth temperature and UHV/CVD
conditions, and forming a heavily doped n or p type polysilicon
gate electrode layer over the gate oxide. The n or p type doping
may be in the range of 1.times.10.sup.20 to 1.times.10.sup.21
atoms/cm.sup.3.
[0017] The invention further provides methods of using the
apparatus arrangements for performing two successive treatment
processes comprising the steps of placing a semiconductor substrate
into the reaction chamber, performing a first treatment process,
transitioning to a controlled gaseous environment (e.g., H.sub.2)
before lowering the temperature to a second growth temperature
below 650.degree. C., and performing a second treatment process in
the reaction chamber. The first and second treatment processes may
include growing Si containing layers with different compositions,
dopants, growth conditions and the like.
[0018] The invention thereby introduces a flexible apparatus and
method capable of migrating seamlessly between LPCVD processes and
UHV-CVD processes within the same reactor. The invention further
introduces a method and apparatus whereby cross contaminants, such
as H.sub.2O, O.sub.2, and the like, and "memory effect"
contaminants, such as BPA's, and the like, can be virtually
eliminated by including usage of a cryopump to mediate a process
transition between coupled UHV-CVD and LPCVD processes.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] These and other features, objects, and advantages of the
present invention may be better understood upon consideration of
the following detailed description of the invention in conjunction
with the accompanying drawings in which:
[0020] FIG. 1 is a first embodiment of the apparatus of the
invention;
[0021] FIG. 2 is a second embodiment of the apparatus of the
invention; and
[0022] FIG. 3 is an illustration of the layers of a high
performance Si and/or SiGe CMOS device structure.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0023] Referring to the drawings, FIG. 1 shows an Advanced
Integrated Chemical Vapor Deposition (AICVD) System 10 comprising a
push/pull transfer system 12 having a transfer arm 13 (including a
flange 19) for moving a plurality of wafers 14 in a carrier or boat
16 into a load lock chamber 18 from ambient conditions via a door
17. The load lock chamber 18 is coupled to the reactor chamber 22
for transferring the plurality of wafers 14 between the reactor
chamber 22 and the external ambient. The load lock chamber 18 is
also coupled to a turbomolecular pump 27 and a mechanical pump 28
in series. After a vacuum is established in load lock chamber 18,
the transfer system 12 also moves the boat supported wafers 14 into
the reactor 22. The load lock chamber 22 may include plural valves
21 and 26.
[0024] An ultra high vacuum level is drawn on the reactor chamber
22 at flange 20 via gate value 30 by a turbomolecular pump 31 in
series with a roots blower 32 and a mechanical pump 33. An
intermediate level vacuum is drawn on load lock chamber 18 via a
gate valve 26 by a turbomolecular pump 27 and a mechanical pump 28
in series. A low pressure vacuum is drawn at flange 24 via a gate
valve 35 by a roots blower 36 and a mechanical pump 37 in series.
For transitioning between a LPCVD process and a UHV-CVD process
(and vice versa) and for removing contaminants generated by these
processes, a vacuum is drawn at flange 20 via a gate valve 39 by a
cryopump 40 and a scroll pump 41 in series.
[0025] While an ultra high vacuum is being drawn at UHV flange 20
and CVD reaction chamber 22 by the pumps 31, 32 and 33, the wafers
14 are positioned in CVD reaction chamber 22 and are heated by a
surrounding furnace 42. Upon attaining the appropriate UHV-CVD
temperature, the wafers are treated with a UHV-CVD gas passing
through chamber 22 from a gas inlet 44 having an isolation valve
45. While a low pressure vacuum is being drawn at flange 24 and CVD
reaction chamber 22 by a roots blower 36 and a mechanical pump 37,
the wafers 14 are positioned in chamber 22, are heated with the
furnace 42 to an appropriate LPCVD temperature, and are treated
with a LPCVD gas passing through chamber 22 from an inlet 48 having
an isolation valve 49. One or more of the mechanical pumps 28, 33,
and 37 also may be a scroll-type pump.
[0026] A first pumping system comprises the roots blower 36 in
series with the mechanical pump 37. A second pumping system is the
series combination of the turbo pump 30, the roots blower 32 and
the mechanical pump 33. A third pumping system comprises the
cryopump 40 and the scroll pump 41. As an alternative, the need for
separated pumps 36 and 37 may be eliminated by the addition of an
interconnecting blower conduit 50 between conduits 52 and 53 so
that roots blower 32 and mechanical pump 33 may serve as the first
pumping system when valve 54 in conduit 50 is opened and valve 56
in conduit 53 is closed.
[0027] For the purpose of transitioning between a LPCVD process and
a UHV-CVD process (and vice versa), the surface of the
semiconductor wafers 14 may first be blanketed with hydrogen gas
introduced through the inlet 44 if the wafers are transferring from
an LPCVD process, or introduced through inlet 48 if the wafers are
transferring from a UHV-CVD process. After each gaseous treatment
process, the chamber 22 may also be purged with hydrogen or another
purge gas introduced through inlet 44 or preferably through both
inlets 44 and 48. After such blanketing and/or purging steps, the
cryopump 40 and the scroll pump 41 may be operated to remove any
remaining contaminants from the preceding treatment process, along
with any remaining blanket and/or purging gases. The contaminants
may include water vapor, dopant, O.sub.2, CO.sub.2, CO, CH.sub.4,
and other hydrocarbon gas other than CH.sub.4.
[0028] As another alternative the third pumping system may comprise
a cyrogenic pump for removing contaminants. The cyrogenic pump may
further include a cold trap for removing at least a portion of the
contaminants from the reaction chamber 22.
[0029] In the alternative embodiment of the apparatus shown in FIG.
2, the Low Pressure (LP) evacuation flange 24 of FIG. 1 has been
eliminated by using a combined LP-UHV flange 62. Attached to the
combined flange 62 is the same load lock chamber 18 and the same
UHV pumping system and transition pumping system as in FIG. 1, and
therefore the components of these systems bear the same numerical
designations as in FIG. 1. In the alternative AICVD system 60 of
FIG. 2, the LP vacuum is drawn on the combined flange 62 via a gate
valve 65 by roots blower 66 and a mechanical pump 67. The end of
combined flange 62 opposite to load lock chamber 18 is connected to
a reaction chamber 70 surrounded and heated by a furnace 71.
[0030] The gases for treating the wafers 14 in reaction chamber 70
are fed through a common gas inlet 72, which in turn is connected
to a UHV-CVD gas inlet line 74 having an isolation valve 75, and to
a LPCVD gas inlet line 77 having an isolation valve 78. Blanket
gases and purge gases may also be fed to the reaction chamber 70
through the common gas inlet 72 via either or preferably through
both of the inlet lines 74 and 77. In the AICVD system 60, the
wafers 14 are heated in reaction chamber 70 for any elevated
temperature portions of either a LPCVD process or a UHV-CVD
process.
[0031] The Advanced Integrated Chemical Vapor Deposition (AICVD)
systems 10 and 60 are based upon growth interrupt experiments and
results which indicate that continuous growth of a silicon
containing layer after an interruption of growth conditions is
possible without any material quality degradation, as long as the
wafers have an atomically clean surface which is maintained
throughout the growth interrupt period and/or during a change
between growth processes. The H.sub.2 pre-bake may also produce
wafer surface passivation, which is believed to be the termination
of atomic bonds on the surface, such as Si bonds, with hydrogen.
The results of growth interrupt experiments are shown and described
in U.S. Pat. No. 6,013,134 referenced above.
[0032] In the operation of AICVD systems 10 and 60, wafers which
may have some native or chemical oxide thereon are loaded into the
reaction chamber to first remove the native oxide from the silicon
or silicon containing surface by employing a H.sub.2 pre-bake at a
temperature in the range from 800.degree. C. to 950.degree. C. for
less than 30 minutes. Immediately after this pre-bake, a silicon
containing gas is flowed through the reaction chamber at a
medium/high temperature of 700.degree. C. to 950.degree. C. to
immediately grow a medium/high temperature silicon epitaxial layer,
after which the growth temperature is reduced to a second growth
temperature below 650.degree. C. and pressure, UHV-CVD mediated by
the cryopump. The foregoing process steps negate the need for the
ex-situ prior art cleaning step of dipping the wafers in HF acid as
mentioned above.
[0033] In the reaction chamber, the entire Si and/or SiGe CMOS
device structure may be formed as shown in FIG. 3. The CMOS device
structure may be composed of a graded up structure as described in
U.S. Pat. No. 5,534,713 by Ismail et al., which is incorporated
herein by reference, followed by both the p- and n-type modulation
doped structures which can now be grown over the surface of the
silicon containing layer using UHV-CVD processing. Since these
active device channels may be at least 5000 .ANG. from the actual
growth interface, which is 100 times more than required, no
degradation whatsoever is to be expected in the device performance
from these SiGe CMOS heterostructures.
[0034] After completion of the Si and/or SiGe CMOS device
structures, the wafers can then be subjected to growth conditions
wherein a gate oxide in the range from 1 nm to 5 nm can be grown in
the low temperature range from 400.degree. C. to 650.degree. C.
With the gate oxide process completed, the wafers can then be
subjected to growth conditions wherein a heavily doped p++
polysilicon gate layer may be grown over the thin gate oxide layer,
which will serve to maintain the oxide quality and thickness
uniformity, as well as a completed gate stack structure.
[0035] A standard polysilicon layer may also be grown using
reaction conditions providing very high in situ boron doping levels
ranging from 10.sup.20 to 10.sup.21 atoms/cm.sup.3. These
conditions are not readily achievable in a LPCVD. However, in AICVD
systems 10 and 60, integrated processing conditions and procedures
may be used for fabricating any high performance Si and/or SiGe
device structure with a high quality gate stack.
EXAMPLE 1
[0036] A method of operation for the AICVD system 60 shown in FIG.
2 would provide the following processes to fabricate any high
performance Si and/or SiGe device structure, such as shown in FIG.
3.
[0037] Start with wafers 14 having a Si substrate 83 outside of the
AICVD 60 after cleaning the wafers using a standard Huang or RCA
cleaning process well known in the art.
[0038] Load the cleaned wafers 14, which may be supported on the
boat 16, into the load lock chamber 18, and then transfer the
wafers on boat 16 into the quartz tube reactor 70 after opening
gate valve 21 and operating roots blower 66 and mechanical pump 67
to provide an LPCVD pressure environment.
[0039] Under a blanket of H.sub.2, pre-bake wafers 14 in the
temperature range from 800.degree. C. to 950.degree. C. for 5 to 30
minutes at a process pressure of 100-500 mtorr to remove native
oxides and prepare silicon surface 84.
[0040] Activate the Dichlorosilane (DCS) source, cease H.sub.2
flow, and grow the Si epitaxial pre-layer 85 to a desired film
thickness under LPCVD conditions, with temperatures between
700.degree. C. and 950.degree. C.
[0041] Cease DCS flow and purge with H.sub.2 for 5 minutes or
less.
[0042] Reduce H.sub.2 flow, open gate valve 30, and activate the
turbomolecular pump 31, roots blower 32 and mechanical pump 33, and
allow the pressure to stabilize at between 0.1 and 10 mtorr.
[0043] Cease H.sub.2 flow, close gate valve 30, open gate valve 39,
and activate cryogenic pump 40 and scroll pump 41; and upon
reaching a base pressure of 10.sup.-8 mtorr or less, rapidly cool
to the low temperature epitaxy growth temperature.
[0044] Close gate valve 65 to the cryogenic pump, initiate silane
flow, and operate the reactor 70 according to the UHV-CVD system
described by B. S. Meyerson in U.S. Pat. No. 5,298,452, issued Mar.
29, 1994, to grow a Si, Ge and/or SiGe layer 86 (a low temperature
epitaxial film).
[0045] When the low temperature epitaxial film 86 is complete,
cease process gas flow, introduce H.sub.2, modify the process
temperature as necessary to the range less than 650.degree. C.,
gradually increase H.sub.2 flow until the reactor pressure is about
10 mtorr, and close gate valve 30 to the reactor turbomolecular
pump 31.
[0046] Open gate valve 65 to the reactor roots blower 66 and start
this blower and mechanical pump 67 when the pressure has reached
100 to 500 mtorr.
[0047] At 100 to 500 mtorr, grow a low temperature thermal oxide
layer 87 by introducing SiH.sub.4 with NO.sub.2 or O.sub.2, under
LPCVD conditions. Alternatively, a silicon dioxide layer 87 may be
formed using tetra ethylortho silicate (TEOS), which is well-known
in the art.
[0048] Cease process gas flow, introduce a H.sub.2 purge flow for
less than 5 minutes and at a temperature of between 400.degree. C.
and 650.degree. C. Reduce H.sub.2 flow, open gate valve 30 and
activate the turbomolecular pump 31, roots blower 32 and mechanical
pump 33 and allow pressure to stabilize between 0.1 and 10 mtorr
and a temperature between 400 and 650.degree. C. Grow a P+ or
P++polysilicon film layer 88 using SiH.sub.4 and Diborane
(B.sub.2H.sub.6).
[0049] Cease process gas flow, introduce H.sub.2 as a cover gas,
transfer the wafers 14 to the load chamber 18 under LPCVD
conditions, and remove product wafers from chamber 18 after raising
its pressure to ambient.
[0050] A method of operation for the AICVD system 10 shown in FIG.
1 is essentially the same as described above for the AICVD system
60, except UHV-CVD process gases and LPCVD process gases are fed
into the reactor 22 from opposite ends of this reactor, and LPCVD
pressures are provided through the LP flange 24 instead of through
a combined LP/UHV chamber, such as chamber 62 in FIG. 2.
[0051] While there has been described and illustrated two
apparatuses using advanced integrated chemical vapor deposition for
fabricating semiconductor devices with LPCVD and UHV-CVD processes
involving interrupted growth of the semiconductor layers, it will
be apparent to those skilled in the art that modifications and
variations are possible without deviating from the broad scope of
the invention, which is to be limited solely by the scope of the
claims set forth below.
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