loadpatents
name:-0.041701078414917
name:-0.026255130767822
name:-0.0005640983581543
Jagannathan; Basanth Patent Filings

Jagannathan; Basanth

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jagannathan; Basanth.The latest application filed is for "integrated circuit (ic) design analysis and feature extraction".

Company Profile
0.22.25
  • Jagannathan; Basanth - Hopewell Junction NY
  • Jagannathan; Basanth - Beacon NY
  • Jagannathan; Basanth - Lake Zurich IL
  • Jagannathan; Basanth - Stormville NY
  • Jagannathan; Basanth - Schaumburg IL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated circuit (IC) design analysis and feature extraction
Grant 9,754,071 - Nanjundappa , et al. September 5, 2
2017-09-05
Integrated Circuit (ic) Design Analysis And Feature Extraction
App 20170242952 - Nanjundappa; Haraprasad ;   et al.
2017-08-24
Structure and layout of a FET prime cell
Grant 8,829,572 - Jagannathan , et al. September 9, 2
2014-09-09
Structure And Layout Of A Fet Prime Cell
App 20120146104 - Jagannathan; Basanth ;   et al.
2012-06-14
Structure and layout of a FET prime cell
Grant 8,187,930 - Jagannathan , et al. May 29, 2
2012-05-29
System and method for de-embedding a device under test employing a parametrized netlist
Grant 7,741,857 - Jagannathan , et al. June 22, 2
2010-06-22
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
Grant 7,713,829 - Chu , et al. May 11, 2
2010-05-11
System And Method For De-embedding A Device Under Test Employing A Parametrized Netlist
App 20090224772 - Jagannathan; Basanth ;   et al.
2009-09-10
INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR Si-Ge BIPOLAR TECHNOLOGY
App 20080124881 - Chu; Jack Ooh ;   et al.
2008-05-29
Field effect transistor having an asymmetrically stressed channel region
Grant 7,355,221 - Freeman , et al. April 8, 2
2008-04-08
Structure And Layout Of A Fet Prime Cell
App 20080076212 - JAGANNATHAN; Basanth ;   et al.
2008-03-27
Epitaxial and polycrystalline growth of Si.sub.1-x-yGe.sub.xC.sub.y and Si.sub.1-yC.sub.y alloy layers on Si by UHV-CVD
Grant 7,183,576 - Chu , et al. February 27, 2
2007-02-27
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
Grant 7,173,274 - Chu , et al. February 6, 2
2007-02-06
Structure And Method Of Making A Field Effect Transistor Having An Asymmetrically Stressed Channel Region
App 20060255415 - Freeman; Gregory G. ;   et al.
2006-11-16
Structure And Layout Of A Fet Prime Cell
App 20060071304 - Jagannathan; Basanth ;   et al.
2006-04-06
Bipolar device having shallow junction raised extrinsic base and method for making the same
Grant 6,927,476 - Freeman , et al. August 9, 2
2005-08-09
Single reactor, multi-pressure chemical vapor deposition for semiconductor devices
App 20050145172 - Chu, Jack O. ;   et al.
2005-07-07
Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
Grant 6,908,866 - Chu , et al. June 21, 2
2005-06-21
In-situ monitoring and control of germanium profile in silicon-germanium alloy films and temperature monitoring during deposition of silicon films
Grant 6,881,259 - Ahlgren , et al. April 19, 2
2005-04-19
Single reactor, multi-pressure chemical vapor deposition for semiconductor devices
Grant 6,875,279 - Chu , et al. April 5, 2
2005-04-05
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
App 20050054171 - Chu, Jack Oon ;   et al.
2005-03-10
Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling
Grant 6,858,532 - Natzle , et al. February 22, 2
2005-02-22
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
Grant 6,815,802 - Chu , et al. November 9, 2
2004-11-09
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics
Grant 6,787,427 - Greenberg , et al. September 7, 2
2004-09-07
BiCMOS integration scheme with raised extrinsic base
Grant 6,780,695 - Chen , et al. August 24, 2
2004-08-24
Method to increase carbon and boron doping concentrations in Si and SiGe films
Grant 6,780,735 - Jagannathan , et al. August 24, 2
2004-08-24
Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
App 20040161911 - Chu, Jack Oon ;   et al.
2004-08-19
Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
App 20040161875 - Chu, Jack Oon ;   et al.
2004-08-19
Optimized blocking impurity placement for SiGe HBTs
App 20040140481 - Jagannathan, Basanth ;   et al.
2004-07-22
Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
Grant 6,750,119 - Chu , et al. June 15, 2
2004-06-15
Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling
App 20040110354 - Natzle, Wesley C. ;   et al.
2004-06-10
Optimized blocking impurity placement for SiGe HBTs
Grant 6,744,079 - Jagannathan , et al. June 1, 2
2004-06-01
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics
App 20040063293 - Greenberg, David R. ;   et al.
2004-04-01
Method for fabricating heterojunction bipolar transistors
Grant 6,660,607 - Jagannathan December 9, 2
2003-12-09
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics
Grant 6,656,809 - Greenberg , et al. December 2, 2
2003-12-02
Optimized blocking impurity placement for SiGe HBTs
App 20030170960 - Jagannathan, Basanth ;   et al.
2003-09-11
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics
App 20030132453 - Greenberg, David R. ;   et al.
2003-07-17
Single reactor, multi-pressure chemical vapor deposition for semiconductor devices
App 20030094130 - Chu, Jack O. ;   et al.
2003-05-22
Bipolar device having shallow junction raised extrinsic base and method for making the same
App 20030057458 - Freeman, Gregory G. ;   et al.
2003-03-27
Non-self-aligned SiGe heterojunction bipolar transistor
App 20020197807 - Jagannathan, Basanth ;   et al.
2002-12-26
Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
App 20020182423 - Chu, Jack Oon ;   et al.
2002-12-05
Method to increase carbon and boron doping concentrations in Si and SiGe films
App 20020160587 - Jagannathan, Basanth ;   et al.
2002-10-31
Method for fabricating heterojunction bipolar transistors
App 20020139996 - Jagannathan, Basanth
2002-10-03
Stepped collector implant and method for fabrication
App 20020132434 - Freeman, Gregory G. ;   et al.
2002-09-19
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
App 20020121676 - Chu, Jack Oon ;   et al.
2002-09-05
Incorporation Of Carbon In Silicon/silicon Germanium Epitaxial Layer To Enhance Yield For Si-ge Bipolar Technology
App 20020100917 - Chu, Jack Oon ;   et al.
2002-08-01

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