U.S. patent application number 11/048073 was filed with the patent office on 2005-06-23 for sioc properties and its uniformity in bulk for damascene applications.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Bao, Tien-I, Jang, Syun-Ming, Ko, Chung-Chi, Li, Lih-Ping, Liu, Ai-Sen.
Application Number | 20050133931 11/048073 |
Document ID | / |
Family ID | 34522006 |
Filed Date | 2005-06-23 |
United States Patent
Application |
20050133931 |
Kind Code |
A1 |
Jang, Syun-Ming ; et
al. |
June 23, 2005 |
SiOC properties and its uniformity in bulk for damascene
applications
Abstract
A method of forming a low-k dielectric material layer comprising
the following steps. A first dielectric material sub-layer is
formed over a substrate. The first dielectric material sub-layer is
treated with an energy treatment to form a hardened layer on the
upper surface of the first dielectric material sub-layer. A second
dielectric material sub-layer is formed over the hardened layer,
wherein the first dielectric sub-layer, the hardened layer and the
second dielectric sub-layer comprise the low-k dielectric material
layer. And a dual damascene structure and a dielectric material
structure formed thereby.
Inventors: |
Jang, Syun-Ming; (Hsin-Chu,
CN) ; Ko, Chung-Chi; (Hsin-Chu, CN) ; Bao,
Tien-I; (Hsin-Chu, CN) ; Li, Lih-Ping;
(Hsin-Chu, CN) ; Liu, Ai-Sen; (Hsin-Chu,
CN) |
Correspondence
Address: |
HAYNES AND BOONE, LLP
901 MAIN STREET, SUITE 3100
DALLAS
TX
75202
US
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd.
Hsin-Chu
CN
|
Family ID: |
34522006 |
Appl. No.: |
11/048073 |
Filed: |
February 1, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11048073 |
Feb 1, 2005 |
|
|
|
10692030 |
Oct 23, 2003 |
|
|
|
Current U.S.
Class: |
257/774 ;
257/E21.277; 257/E21.576; 257/E21.579; 438/629 |
Current CPC
Class: |
H01L 21/02271 20130101;
H01L 21/76829 20130101; H01L 21/76807 20130101; H01L 21/76801
20130101; H01L 21/76835 20130101; H01L 21/0234 20130101; H01L
21/31633 20130101; H01L 21/02126 20130101; H01L 21/022 20130101;
H01L 21/76826 20130101 |
Class at
Publication: |
257/774 ;
438/629 |
International
Class: |
H01L 021/4763; H01L
023/52 |
Claims
We claim:
1. A dual damascene structure, comprising: a substrate; a first
patterned dielectric material sub-layer over the substrate; a
patterned hardened sub-layer upon the first patterned dielectric
material sub-layer; the patterned hardened sub-layer and the first
patterned dielectric material sub-layer having a via opening
therethrough exposing a portion of the substrate; and a second
patterned dielectric material sub-layer upon the patterned hardened
sub-layer; the second patterned sub-layer having a trench opening
therethrough over the via opening.
2. The structure of claim 1, wherein the first and second patterned
dielectric material sub-layers are each comprised of SiOC.
3. The structure of claim 1, wherein the first and second patterned
dielectric material sub-layers each have a dielectric constant of
from about 2.3 to 2.6.
4. The structure of claim 1, wherein the first and second patterned
dielectric material sub-layers each have a dielectric constant of
greater than about 2.8.
5. The structure of claim 1, wherein the hardened layer has a
thickness of from about 250 to 500 .ANG..
6. The structure of claim 1, wherein the hardened layer has a
thickness of from about 300 to 450 .ANG..
7. The structure of claim 1, wherein the hardened layer is an etch
stop layer.
8. A dielectric material structure, comprising: a substrate; one or
more dielectric material sub-layers over the substrate; one or more
respective hardened layers upon the one or more dielectric material
sub-layers; and an uppermost dielectric material sub-layer upon the
uppermost one or more respective hardened layer.
9. The structure of claim 8, wherein the one or more dielectric
material sub-layers and the uppermost dielectric material sub-layer
are each comprised of SiOC.
10. The structure of claim 8, wherein the one or more dielectric
material sub-layers and the uppermost dielectric material sub-layer
each have a dielectric constant of from about 2.3 to 2.6.
11. The structure of claim 8, wherein the one or more dielectric
material sub-layers and the uppermost dielectric material sub-layer
each have a dielectric constant of greater than about 2.8.
12. The structure of claim 8, wherein the one or more respective
hardened layers each have a thickness of from about 250 to 500
.ANG..
13. The structure of claim 8, wherein the one or more respective
hardened layers each have a thickness of from about 300 to 450
.ANG..
14. The structure of claim 8, wherein the one or more respective
hardened layers are etch stop layers.
15. An apparatus comprising a substrate, and a low-k dielectric
material layer formed over the substrate, the low-k dielectric
material layer including: a first dielectric material sub-layer
disposed over the substrate, the first dielectric material
sub-layer including a hardened layer at an upper surface thereof;
and a second dielectric material sub-layer disposed over the
hardened layer.
16. The apparatus of claim 15, wherein the first dielectric
material sub-layer is made of SiOC.
17. The apparatus of claim 15, wherein the first dielectric
material sub-layer has a dielectric constant in the range of about
2.3 to 2.6.
18. The apparatus of claim 15, wherein the hardened layer has a
thickness in the range of about 250 to 500 .ANG..
19. The apparatus of claim 15, wherein the hardened layer has a
thickness in the range of about 300 to 450 .ANG..
20. The apparatus of claim 15, wherein the hardened layer is made
from a material that can function as an etch stop layer.
21. The apparatus of claim 15, including: a trench opening
extending within the second dielectric material sub-layer above the
hardened layer; and a via opening extending through the hardened
layer and the first dielectric material sub-layer from the trench
opening to a portion of the substrate.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to semiconductor
fabrication and more specifically to formation of SiOC dielectric
layers.
BACKGROUND OF THE INVENTION
[0002] Chemical vapor deposition (CVD) low-k dielectric materials
with good mechanical and electrical strengths are in demand for
damascene applications
[0003] U.S. Pat. No. 6,372,661 B1 to Lin et al. describes SiOC
films and post-treatments.
[0004] U.S. Pat. No. 6,348,407 to Gupta et al. describes a plasma
treatment of a low-k layer and an etch stop layer in a dual
damascene process.
[0005] U.S. Pat. No. 6,323,125 B1 to Soo et al. describes a plasma
treatment and PPMSO layer in a dual damascene process.
[0006] U.S. Pat. No. 6,323,121 B1 to Liu et al. describes a dual
damascene process with etch stops and a plasma treatment.
SUMMARY OF THE INVENTION
[0007] Accordingly, it is an object of one or more embodiments of
the present invention to provide an method of improving the
properties of SiOC dielectric material layers.
[0008] It is another object of the present invention to provide a
method of forming an embedded hard layer within an SiOC dielectric
material layer, and structures formed thereby.
[0009] Other objects will appear hereinafter.
[0010] It has now been discovered that the above and other objects
of the present invention may be accomplished in the following
manner. Specifically, a first dielectric material sub-layer is
formed over a substrate. The first dielectric material sub-layer is
treated with an energy treatment to form a hardened layer on the
upper surface of the first dielectric material sub-layer. A second
dielectric material sub-layer is formed over the hardened layer,
wherein the first dielectric sub-layer, the hardened layer and the
second dielectric sub-layer comprise the low-k dielectric material
layer. And a dual damascene structure and a dielectric material
structure formed thereby.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The present invention will be more clearly understood from
the following description taken in conjunction with the
accompanying drawings in which like reference numerals designate
similar or corresponding elements, regions and portions and in
which:
[0012] FIGS. 1 to 6 schematically illustrate a first preferred
embodiment of the present invention.
[0013] FIG. 7 schematically illustrates a second preferred
embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
First Embodiment--FIGS. 1 Through 6
[0014] Initial Structure--FIG. 1
[0015] As shown in FIG. 1, structure 10 is preferably a silicon
(Si), germanium (Ge) or gallium arsenide (GaAs) substrate, is more
preferably a silicon substrate. Structure 10 is understood to
possibly include a semiconductor wafer or substrate, active and
passive devices formed within the wafer or substrate, conductive
layers and dielectric layers (e.g., inter-poly oxide (IPO),
intermetal dielectric (IMD), etc.) formed over the wafer surface.
The term "semiconductor structure" is meant to include devices
formed within a semiconductor wafer and the layers overlying the
wafer.
[0016] As described below, a dielectric layer 24 to be formed over
the structure 10 will have a total thickness of 12 and will have a
trench formed therein at thickness 14. Dielectric layer 24 is
preferably a low-k dielectric layer, i.e. having a dielectric
constant (k) of less than about 3.0.
[0017] Dielectric layer 24 may be, for example, an intermetal
dielectric (IMD) layer. The deposition of dielectric layer 24 is
stopped to provide the hydrogen treatment 18 and then started to
complete formation of dielectric layer 24.
[0018] Formation of Lower Dielectric Sub-Layer 16 to a Thickness
14
[0019] As shown in FIG. 2, a lower dielectric sub-layer 16 of
dielectric layer 24 is formed over structure 10 to a thickness 14
at which a trench will be formed above this thickness 14. Lower
dielectric sub-layer 16 is preferably comprised of SiOC having a
dielectric constant (k) of preferably from about 2.3 to 2.6, more
preferably from about 2.4 to 2.6 and most preferably greater than
about 2.3 as will be used for illustrative purposes hereafter.
[0020] Lower SiOC dielectric sub-layer 16 is preferably formed by a
chemical vapor deposition (CVD) process using the following
parameters:
[0021] temperature: preferably from about 250 to 450.degree. C. and
more preferably from about 300 to 400.degree. C.;
[0022] pressure: preferably from about 4.5 to 6.5 mTorr and more
preferably from about 5.0 to 6.0 mTorr;
[0023] time: preferably from about 40 to 60 seconds and more
preferably from about 45 to 55 seconds (depending upon how much
thickness is desired to be deposited); and
[0024] power: preferably from about 1500 to 3000 W and more
preferably from about 1800 to 2700 W.
[0025] Energy Treatment 18 to Improve Film Properties and to Form
Hard Layer 20
[0026] As shown in FIG. 3, the CVD deposition process is stopped
and lower SiOC dielectric sub-layer 16 is subjected to an energy
treatment 18 to improve the film properties of lower SiOC
dielectric sub-layer 16 and to convert an upper portion of lower
SiOC dielectric sub-layer 16 to hard layer 20.
[0027] Hard layer 20 has a thickness 14 of preferably from about
250 to 500 .ANG. and more preferably from about 350 to 450 .ANG..
The thickness 14 of lower SiOC dielectric sub-layer 16 denotes the
lower depth to which a subsequent trench will be formed within SiOC
dielectric layer 24.
[0028] The improved film properties of lower SiOC dielectric
sub-layer 16 include lowering the dielectric constant (k),
improving mechanical properties such as hardness, Young modulus,
peeling strength and Stress Migration (SM) and improving electrical
properties such as the breakdown voltage, leakage current density
and Time-Dependent Dielectric Breakdown (TDDB) Failure.
[0029] Energy treatment 18 is preferably a hydrogen treatment, as
will be used for purposes of illustration hereafter, and may be
performed in situ or ex situ in a separate chamber and is more
preferably performed ex-site because of different temperature
between deposition and treatment chambers.
[0030] Hydrogen treatment 18 is preferably a plasma treatment
comprising under the following conditions:
[0031] H.sub.2 flow: from about 1600 to 2400 sccm and more
preferably from about 1800 to 2200 sccm;
[0032] temperature: preferably from about 300 to 450.degree. C. and
more preferably from about 350 to 400.degree. C.;
[0033] pressure: preferably from about 4.5 to 9.0 mTorr and more
preferably from about 6.0 to 7.5 mTorr;
[0034] time: preferably from about 30 to 240 seconds and more
preferably from about 90 to 180 seconds; and
[0035] power: preferably from about 300 to 1500 W and more
preferably from about 600 to 1200 W.
[0036] Formation of Upper Dielectric Sub-Layer 22
[0037] As shown in FIG. 4, an upper dielectric sub-layer 22 is
formed over hard layer 20 to a thickness of preferably from about
2000 to 3000 .ANG. and more preferably from about 2200 to 2800
.ANG. to complete formation of dielectric layer 24 having embedded
hard layer 20 formed therein. Upper dielectric sub-layer 22 is
preferably comprised of SiOC having a dielectric constant (k) of
from about 2.3 to 2.6, more preferably from about 2.4 to 2.6 and
most preferably greater than about 2.3 as will be used for
illustrative purposes hereafter.
[0038] Upper SiOC dielectric sub-layer 22 is preferably formed by a
chemical vapor deposition (CVD) process using the following
parameters:
[0039] temperature: preferably from about 250 to 450.degree. C. and
more preferably from about 300 to 400.degree. C.;
[0040] pressure: preferably from about 4.5 to 6.5 mTorr and more
preferably from about 5.0 to 6.0 mTorr;
[0041] time: preferably from about 40 to 60 seconds and more
preferably from about 45 to 55 seconds; and
[0042] power: preferably from about 1500 to 3000 W and more
preferably from about 1800 to 2700 W.
[0043] Formation of Dual Damascene Opening 34
[0044] As shown in FIGS. 5 and 6 the structure of FIG. 4 may be
utilized in the formation of a damascene or dual damascene opening
34 as shown in FIG. 6 wherein hard layer 20 may function as an etch
stop layer in the formation of trench opening 32 as described
below. Hard layer 20 may function as an etch stop layer by having a
lower etch rate than the adjacent dielectric sub-layers 16, 22
and/or by an endpoint signal change.
[0045] As shown in FIG. 5, dielectric layer 24 is patterned to form
a via opening 28 exposing a portion 29 of structure 10. Dielectric
layer 24 may be patterned using, for example, an overlying first
patterned mask layer 26 that may be comprised of, for example,
photoresist as shown in FIG. 5.
[0046] For example, using first patterned mask layer 26, upper SiOC
dielectric sub-layer 22, hard layer 20 and lower SiOC dielectric
sub-layer 16 are patterned to form via opening 28 therethrough.
First patterned mask layer 26 is then removed and the structure may
be cleaned.
[0047] As shown in FIG. 6, using patterned hard layer 20' as an
etch stop layer, upper patterned SiOC dielectric sub-layer 22' is
again patterned to form trench opening 32 over reduced via opening
28' exposing portions 33 of hard layer 20'. Upper patterned SiOC
dielectric sub-layer 22' may be patterned using, for example, an
overlying second patterned mask layer 30 that may be comprised of,
for example, photoresist as shown in FIG. 6. Second patterned mask
layer 30 may then be removed and the structure may be cleaned.
[0048] The upper patterned SiOC dielectric sub-layer 22"/layer 24"
may then be subjected to another hydrogen treatment 18 to further
improve the film properties. The H.sub.2 treat at the upper layer
of low-k which can serve as a capped layer.
[0049] A dual damascene structure (not shown) may then be formed
within dual damascene opening 34.
[0050] It is noted that more than one etch stop layer 20 may be
formed embedded within SiOC dielectric layer 24 by performing
hydrogen treatments 18 at varying thicknesses during the formation
of SiOC dielectric layer 24 in accordance with the teachings of the
present invention.
Second Embodiment--FIG. 7
[0051] As shown in FIG. 7, if a dielectric layer 124 to be formed
will not include one or more etch stop layer(s), or if the
dielectric constant (k) of the dielectric layer as initially formed
is greater than about 2.8, then multiple hydrogen treatments 18 may
be employed to further enhance, and improve the uniformity of, the
film properties of dielectric layer 124 and to form numerous hard
layers 112, 116, 120 embedded within dielectric layer 124. In the
case of a dielectric layer 124 having a dielectric constant greater
than about 2.8 as initially formed, the dielectric constant is not
necessarily intended to be improved through the use of the multiple
hydrogen treatments 18. Dielectric layer 124 is preferably a low-k
dielectric layer, i.e. having a dielectric constant (k) of less
than about 3.0.
[0052] For example, as shown in FIG. 7, three separate hydrogen
treatments 18 may be conducted during the deposition of dielectric
layer 124 at thicknesses 104, 106 and 108 of respective dielectric
sub-layers 110, 114 and 118. The upper dielectric sub-layer 122 is
not subjected to hydrogen treatment 18 as the H.sub.2 treat at the
upper layer of low-k can serve as a CMP capped layer, and doesn't
need to be further treated.
[0053] Each respective hydrogen treatment 18 is conducted under
analogous conditions as hydrogen treatment 18 described in the
first embodiment.
[0054] The dielectric layer 124 and the dielectric sub-layers 110,
114, 118 are preferably comprised of SiOC as will be used for
illustrative purposes hereafter and may have varying dielectric
constants (k) of from about 2.3 to 2.6, from about 2.4 to 2.6 and
greater than about 2.8, for example.
[0055] As shown in FIG. 7, structure 10 is preferably a silicon
(Si), germanium (Ge) or gallium arsenide (GaAs) substrate, is more
preferably a silicon substrate. Structure 10 is understood to
possibly include a semiconductor wafer or substrate, active and
passive devices formed within the wafer, conductive layers and
dielectric layers (e.g., inter-poly oxide (IPO), intermetal
dielectric (IMD), etc.) formed over the wafer surface. The term
"semiconductor structure" is meant to include devices formed within
a semiconductor wafer and the layers overlying the wafer.
[0056] As taught in the first embodiment, lower SiOC dielectric
sub-layer 110 having a thickness 104 is formed over structure 100
and is then subjected to a hydrogen treatment 18 to enhance, and
improve the uniformity of, the film properties of the lower SiOC
dielectric sub-layer 110 and which forms lower hard layer 112.
[0057] Middle SiOC dielectric sub-layer 114 having a thickness 106
minus thickness 104 is formed over lower hard layer 112 and is then
subjected to a hydrogen treatment 18 to enhance, and improve the
uniformity of, the film properties of the middle hard layer 110 and
which forms middle hard layer 116.
[0058] Upper SiOC dielectric sub-layer 118 having a thickness 108
minus thickness 106 is formed over middle hard layer 116 and is
then subjected to a hydrogen treatment 18 to enhance, and improve
the uniformity of, the film properties of the upper dielectric
sub-layer 118 and which forms upper hard layer 120.
[0059] Uppermost SiOC dielectric sub-layer 122 having a thickness
102 minus thickness 108 is formed over upper hard layer 120 which
completes formation of SiOC dielectric layer 124. The uppermost
SiOC dielectric sub-layer 122 is not subjected to hydrogen
treatment 18.
[0060] It is noted that although FIG. 7 illustrates SiOC dielectric
layer 124 being comprised of four SiOC dielectric sub-layers with
respective embedded hard layers interposed therebetween SiOC
dielectric layer 124 may be comprised of only three SiOC dielectric
sub-layers with respective embedded hard layers interposed
therebetween or more than four SiOC dielectric sub-layers with
respective embedded hard layers interposed therebetween.
[0061] Advantages of the Present Invention
[0062] The advantages of one or more embodiments of the present
invention include:
[0063] 1. the dielectric constant of the entire dielectric layer so
formed is improved;
[0064] 2. the dielectric constant, select mechanical properties and
select electrical properties of the entire dielectric layer so
formed are improved;
[0065] 3. the uniformity of the dielectric constant, select
mechanical properties and select electrical properties of the
entire dielectric layer so formed is improved;
[0066] 4. packaging compatibility is improved due to the increase
mechanical strength of the entire dielectric layer so formed;
[0067] 5. arcing is reduced due to the increased breakdown strength
of the entire dielectric layer so formed; and
[0068] 6. one or more of the hard layers formed between the
sub-layers comprising the entire dielectric layer so formed may be
used as etch stop layers for subsequent etching of the entire
dielectric layer so formed.
[0069] While particular embodiments of the present invention have
been illustrated and described, it is not intended to limit the
invention, except as defined by the following claims.
* * * * *