U.S. patent application number 10/896547 was filed with the patent office on 2004-12-23 for extendible process for improved top oxide layer for dram array and the gate interconnects while providing self-aligned gate contacts.
This patent application is currently assigned to Infineon Technologies AG. Invention is credited to Arnold, Norbert, Dyer, Thomas W., Economikos, Laertis, Halle, Scott, Knorr, Andreas, Malik, Rajeev.
Application Number | 20040256651 10/896547 |
Document ID | / |
Family ID | 24710478 |
Filed Date | 2004-12-23 |
United States Patent
Application |
20040256651 |
Kind Code |
A1 |
Dyer, Thomas W. ; et
al. |
December 23, 2004 |
Extendible process for improved top oxide layer for DRAM array and
the gate interconnects while providing self-aligned gate
contacts
Abstract
A Top Oxide Method is used to form an oxide layer over an array
of vertical transistors as in a trench dynamic random access memory
(DRAM) array with vertically stacked access metal oxide
semiconductor field effect transistors (MOSFETs). The Top Oxide is
formed by first forming the vertical devices with the pad nitride
remaining in place. Once the devices have been formed and the gate
polysilicon has been planarized down to the surface of the pad
nitride, the pad nitride is stripped away leaving the tops of the
gate polysilicon plugs extending above the active silicon surface.
This pattern of polysilicon plugs defines the pattern over which
the Top Oxide is deposited. The deposited Top Oxide fills the
regions between and on top of the polysilicon plugs. The Top Oxide
is then planarized back to the tops of the polysilicon plugs so
contacts can be made between the passing interconnects and the
gates of the vertical devices. The Top Oxide layer serves to
separate the passing interconnects from the active silicon thereby
reducing capacitive coupling between the two levels and providing a
robust etch-stop layer for the reactive ion etch (RIE) patterning
of the subsequent interconnect level.
Inventors: |
Dyer, Thomas W.; (Pleasant
Valley, NY) ; Knorr, Andreas; (Fishkill, NY) ;
Economikos, Laertis; (Wappingers Falls, NY) ; Halle,
Scott; (Hopewell Junction, NY) ; Malik, Rajeev;
(Pleasantville, NY) ; Arnold, Norbert; (Chestnut
Ridge, NY) |
Correspondence
Address: |
LERNER, DAVID, LITTENBERG,
KRUMHOLZ & MENTLIK
600 SOUTH AVENUE WEST
WESTFIELD
NJ
07090
US
|
Assignee: |
Infineon Technologies AG
Munich
NY
International Business Machines Corporation
Armonk
|
Family ID: |
24710478 |
Appl. No.: |
10/896547 |
Filed: |
July 22, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10896547 |
Jul 22, 2004 |
|
|
|
09675435 |
Sep 29, 2000 |
|
|
|
6794242 |
|
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Current U.S.
Class: |
257/296 ;
257/330; 257/331; 257/E21.652; 257/E21.659; 438/244; 438/248;
438/270 |
Current CPC
Class: |
H01L 27/10864 20130101;
H01L 27/10891 20130101 |
Class at
Publication: |
257/296 ;
438/244; 438/248; 438/270; 257/331; 257/330 |
International
Class: |
H01L 029/76; H01L
021/8242; H01L 031/119; H01L 029/94; H01L 021/336 |
Claims
1. A semiconductor structure comprising: a vertical metal oxide
semiconductor field effect transistor (MOSFET) array formed in a
silicon substrate; a wiring layer that interconnects gates of
vertical MOSFETs of the MOSFET array; and an oxide layer disposed
between the MOSFET array and the wiring layer; the gate conductors
of the vertical MOSFETs extending vertically through the oxide and
having a constant cross-sectional dimension.
2. The semiconductor structure of claim 1, further comprising
isolation trenches filled with insulating material that
electrically insulates the vertical MOSFETs from one another.
3. The semiconductor structure of claim 1, wherein a thickness of
the oxide layer is adjustable over a wide range.
4. The semiconductor structure of claim 1, wherein a top surface of
the oxide is coplanar with top surfaces of gate polysilicon
extensions of the MOSFETs and is parallel to a surface of the
silicon substrate.
5. The semiconductor structure of claim 1, wherein a thickness of
the oxide is approximately equal over the MOSFET array and over
portions of the substrate beyond the MOSFET array.
6. The semiconductor structure of claim 1, wherein the oxide layer
is present only over predefined regions of the silicon substrate,
said predefined regions including a region of the MOSFET array.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional application of U.S. patent
application Ser. No. 09/675,435, entitled EXTENDIBLE PROCESS FOR
IMPROVED TOP OXIDE LAYER FOR DRAM ARRAY AND THE GATE INTERCONNECTS
WHILE PROVIDING SELF-ALIGNED GATE CONTACTS, filed Sep. 29, 2000,
the disclosure of which is hereby incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] The present invention generally relates to the manufacture
of integrated circuits (ICs) with vertical metal oxide
semiconductor field effect transistors (MOSFETs) and, more
particularly, to methods for forming a silicon dioxide layer over
an array of vertical MOSFETs. The oxide layer serves to separate
and electrically insulate the vertical devices from the overpassing
interconnect wiring while allowing for self-aligned contacts to be
made between the interconnects and the gates of the vertical
MOSFETs.
[0003] We propose a method (which we call the "Top Oxide Method")
for forming the oxide layer over an array of vertical transistors,
as in a trench DRAM array, in which the access transistors are
vertically stacked above the trench capacitors. An insulating layer
is needed on top of the active silicon to reduce capacitive
coupling between the passing interconnects and the underlying
semiconductor components. It is also needed to provide a robust
etch stop layer for the reactive ion etch (RIE) patterning of the
subsequent interconnect level. Oxide is preferred over silicon
nitride since it has a lower dielectric constant and since it
allows for standard processing of the self-aligned source junction
contacts. This insulating layer must also allow for electrical
contact to be made between the passing interconnects and the
vertical transistor gates. In addition, the thickness of the layer
should be freely adjustable for flexibility in engineering its
electrical and structural properties. The process sequence for
forming the oxide layer should also permit the implementation of
other features such as vertical gate pull-back and vertical gate
nitride spacers. The process should also be extendible to shrinking
feature sizes.
SUMMARY OF THE INVENTION
[0004] It is an object of the present invention to provide a method
(Top Oxide Method) for forming an insulating layer (Top Oxide) over
a vertical device array that satisfies the criteria mentioned
above.
[0005] According to the method of this invention, the vertical
MOSFETs and any underlying structures, such as deep trench
capacitors, are formed with a pad nitride in place. Then, after the
gate oxide and vertical gate polycrystalline silicon (polysilicon)
conductor are formed, any materials deposited on the top of the pad
nitride are removed with the polysilicon gate conductor protecting
the structures inside the vertical device recess. The gate
polysilicon could then be further planarized (e.g., using a
chemical-mechanical polish (CMP)) down to the pad nitride, if
desired. Once the top surface of the pad nitride is cleared and the
gate polysilicon is planarized as desired, the pad nitride is
etched away selective to the polysilicon gate conductor and pad
oxide which covers the silicon surface. Then, the Top Oxide is
deposited. This oxide covers the polysilicon gate plugs that extend
above the silicon surface and fills the spaces in between. This
oxide is then CMP planarized or otherwise etched back to the tops
of the polysilicon plugs.
[0006] The resulting structure is a square edged oxide surrounding
the gate polysilicon plugs. This square edge makes the process
extendible to shrinking ground rules. The Top Oxide thickness is
freely adjustable since it is determined solely by the pad nitride
thickness that can be increased or decreased as needed. In
addition, this method lends itself to additional process options
such as a vertical gate pull-back, vertical gate nitride sidewall
spacers, and a TTO nitride liner.
[0007] In an alternate sequence, the isolation trenches (ITs) can
be formed before the Top Oxide is deposited. In this sequence, the
pad nitride is kept in place after the vertical devices have been
formed and it is used for IT processing. This pad nitride is
stripped after the ITs have been etched, filled, and planarized
down to this pad nitride. After the pad nitride is stripped, the
Top Oxide would be deposited and planarized down to the tops of the
gate polysilicon plugs in a manner similar to that of the original
sequence.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The foregoing and other objects, aspects and advantages will
be better understood from the following detailed description of a
preferred embodiment of the invention with reference to the
drawings, in which:
[0009] FIGS. 1A and 1B are, respectively, a top view and a
cross-sectional view showing the structure after depositing the TTO
HDP;
[0010] FIGS. 2A and 2B are, respectively, a top view and a
cross-sectional view showing the etch of the excess HDP TTO to the
TTO nitride liner;
[0011] FIGS. 3A and 3B are, respectively, a top view and a
cross-sectional view showing the formed gate;
[0012] FIGS. 4A and 4B are, respectively, a top view and a
cross-sectional view showing the excess gate polysilicon and the
TTO oxide on top of the pad nitride removed down to the surface the
pad nitride;
[0013] FIGS. 5A and 5B are, respectively, a top view and a
cross-sectional view showing the pad nitride stripped from the top
surface selective to the pad oxide and the polysilicon plugs
extending above the silicon surface;
[0014] FIGS. 6A and 6B are, respectively, a top view and a
cross-sectional view showing the deposited Top Oxide which has been
planarized down to the tops of the polysilicon plugs;
[0015] FIG. 7 is a microphotograph providing a perspective view of
the top surface and cross-section after the pad nitride has been
stripped and before the Top Oxide deposition;
[0016] FIG. 8 is a microphotograph of higher magnification showing
a view of the cross-section after stripping the pad nitride;
[0017] FIG. 9 is a microphotograph showing the resulting structure
of the Top Oxide Method according to the invention;
[0018] FIG. 10 is a microphotograph showing the Top Oxide outside
the array in an unpatterned region on the same chip shown in FIG.
9;
[0019] FIG. 11 is a microphotograph of higher magnification showing
the details of the Top Oxide structure in which the gate
polysilicon plugs extend to the top surface of the Top Oxide so
contact can be easily made to the interconnects which would be
subsequently fabricated;
[0020] FIGS. 12A and 12B are, respectively, a top view and an
orthogonal cross-sectional view showing the structure corresponding
to FIGS. 4A and 4B (after vertical device formation and gate
polysilicon planarization down to the pad nitride) as the starting
point for isolation trench (IT) formation using the pad
nitride;
[0021] FIGS. 13A and 13B are, respectively, a top view and an
orthogonal cross-sectional view showing the isolation trenches
after they have been etched, filled with oxide and planarized back
to the top of the pad nitride; 22) FIGS. 14A and 14B are,
respectively, a top view and an orthogonal cross-sectional view
showing the pad nitride stripped from the top surface selective to
the pad oxide, the IT oxide, and the poly-Si plugs which extend
above the silicon surface; and FIGS. 15A and 15B are, respectively,
a top view and an orthogonal cross-sectional view showing the
deposited Top Oxide that has been planarized to the tops of the
polysilicon plugs.
DETAILED DESCRIPTION
[0022] Referring now to the drawings, and more particularly to
FIGS. 1 to 6, there is shown the basic sequence and the resulting
structure of this invention. FIGS. 1A and 1B show, respectively, a
top view and a cross-sectional view of a portion of a semiconductor
structure which has been processed by previous conventional
processing steps to produce a one-sided buried strap and collar in
the device recess. A one-sided buried strap 11 and an oxide collar
12 are formed in device recesses 13 and 14 previously formed in the
silicon substrate 10. After forming the one-sided buried strap 11
and collar 12 in the device recesses, the High Density Plasma (HDP)
Trench Top Oxide (TTO) 15 is deposited over the pad nitride 16 and
the TTO nitride barrier liner 17, the pad nitride 16 and the
nitride barrier liner 17 covering the one-sided oxide collar in the
device recesses having been formed in preceding processing
steps.
[0023] In FIGS. 2A and 2B, the TTO HDP oxide 15 is etched just
enough to clear it from the sidewalls in the recesses 13 and 14.
This etch is done selectively to the nitride barrier liner 17
covering the remaining collar oxide 12. The gate sacrificial oxide
(sac ox) could also be removed during this etch step.
Alternatively, it can be grown and stripped away later or skipped
altogether. The nitride barrier liner from previous steps may or
may not be removed after the oxide etch.
[0024] FIGS. 3A and 3B show the gate formed as usual. This includes
growing the gate oxide 19 and overfilling the recesses with
amorphous silicon (a-Si) or polysilicon 18. If needed, a
sacrificial oxide could be grown and stripped away just prior to
gate oxidation to prepare the vertical silicon surface for gate
oxidation.
[0025] FIGS. 4A and 4B show the excess gate a-Si or polysilicon and
TTO oxide on top of the pad nitride removed down to the surface of
the pad nitride 16. Chemical-mechanical polishing (CMP), wet
etching, dry etching, or some combination of these techniques may
be used to remove the oxide.
[0026] In the next step, shown in FIGS. 5A and 5B, the pad nitride
is stripped from the top surface selective to the pad oxide 20 and
the polysilicon plugs 18 extending above the silicon surface. The
polysilicon plugs 18 define the form for the subsequent oxide
deposition. If desired, this form could be modified by additional
processing steps such as an isotropic wet or dry silicon etch to
reduce the size of the exposed top part of the plug. This would be
done to facilitate the integration with subsequent processing
(e.g., formation of the gate interconnects and formation of the
source junction contacts).
[0027] Finally, as shown in FIGS. 6A and 6B, the Top Oxide 21 is
deposited by HDP or some other oxide deposition technique. The
oxide 21 fills the gaps between the polysilicon plugs 18 and can
also cover them. CMP or a wet or dry etch-back removes the oxide
from the tops of the plugs without over-etching too much outside of
the array. The combination of HDP deposition and oxide CMP is the
preferred implementation of this step.
[0028] FIG. 7 is a scanning electron microscope (SEM)
microphotograph showing a perspective view of the top surface and
cross section of the device after the pad nitride has been stripped
and before the Top Oxide deposition. FIG. 8 is a higher
magnification SEM microphotograph showing a view of the
cross-section after the pad nitride strip. FIG. 9 is a SEM
microphotograph showing the resulting structure of the Top Oxide
Method according to the invention. The top layer seen in the
microphotograph is a chrome capping layer deposited for image
enhancement. The SEM microphotograph shown in FIG. 10 shows the Top
Oxide outside of the array in an unpatterned region on the same
chip shown in FIG. 9. The microphotograph shows nearly the same
oxide thickness in these unpatterned regions as is seen in the
array. This indicates very little dishing of the HDP oxide across
the chip. This capability of the HDP/CMP combination is the
preferred implementation of the method.
[0029] FIG. 11 shows the structural details of the Top Oxide
according to the present invention. In this figure, there is a
silicon nitride capping layer used for image enhancement. The
structure produced as shown in FIG. 11 is a square edged oxide
surrounding the gate polysilicon plugs. It is primarily this square
edge which makes the process according to the invention extendible
to shrinking ground rules. The process is flexible since the Top
Oxide thickness is determined by the thickness of the pad nitride
that can be freely adjusted. In addition, the method of this
invention lends itself to additional process options such as
vertical gate pull-back, vertical gate nitride spacers, and a TTO
nitride liner.
[0030] In FIGS. 12 to 15, there is shown an alternate sequence to
the process according to the invention. In this sequence, the
insulation trenches (ITs) are formed with the pad nitride in place
and the Top Oxide is formed after IT processing.
[0031] The starting point for this alternate sequence is where the
isolation trenches have been formed with the pad nitride 16 still
in place is that shown in FIGS. 12A and 12B. This structure
corresponds exactly to that in FIGS. 4A and 4B (that is, after the
vertical device has been fabricated and the gate polysilicon 18 has
been planarized back to the pad nitride 16). All steps up to this
point would be identical to those already described.
[0032] The next series of steps are the standard sequence for
isolation trench (IT) formation. FIGS. 13A and 13B illustrate the
structure after the isolations trenches have been patterned
lithographically, etched using silicon reactive ion etching (RIE),
filled with oxide, and the IT oxide 22 has been CMP planarized back
to the top of the pad nitride.
[0033] In the next step, shown in FIGS. 14A and 14B, the pad
nitride is stripped from the top surface selective to the pad oxide
20, the IT oxide 22, and the polysilicon plugs 18 that extend above
the silicon surface. The polysilicon plugs 18 and the IT pattern
define the pattern for the subsequent oxide deposition. If desired,
this pattern could be adjusted by an additional process step such
as an isotropic wet or dry silicon etch to reduce the size of the
exposed top part of the polysilicon plugs 18. This would be done to
facilitate the integration with subsequent processing steps (e.g.,
formation of the gate interconnects and formation of the source
junction contacts).
[0034] Finally, as shown in FIGS. 15A and 15B, the Top Oxide 21 is
deposited by HDP oxide deposition or by some other oxide deposition
technique. The oxide fills the gaps between the polysilicon plugs
18 and can also cover them. It also fills in the regions between
the IT oxide 22 which also extends above the silicon surface. CMP
or a wet or dry etch-back removes the oxide to the tops of the
plugs 18 without over-etching too much outside of the array. The
combination of HDP oxide deposition and oxide CMP is the preferred
implementation of this step.
[0035] While the invention has been described in terms of preferred
embodiments, those skilled in the art will recognize that the
invention can be practiced with modification within the spirit and
scope of the appended claims.
* * * * *