Malik; Rajeev

Patent Applications and Registrations

Patent applications and USPTO patent grants for Malik; Rajeev.The latest application filed is for "preventing cavitation in high aspect ratio dielectric regions of semiconductor device".

Company Profile

0.23.22

Malik; Rajeev - Pleasantville NY
Malik; Rajeev - Wappingers Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Device having dual etch stop liner and reformed silicide layer and related methods Grant 7,928,571 - Chidambarrao , et al. April 19, 2	2011-04-19
Semiconductor device structure having low and high performance devices of same conductive type on same substrate Grant 7,776,695 - Arnold , et al. August 17, 2	2010-08-17
Device having enhanced stress state and related methods Grant 7,732,270 - Chidambarrao , et al. June 8, 2	2010-06-08
Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Grant 7,683,434 - Agnello , et al. March 23, 2	2010-03-23
OPC trimming for performance Grant 7,627,836 - Culp , et al. December 1, 2	2009-12-01
Preventing Cavitation In High Aspect Ratio Dielectric Regions Of Semiconductor Device App 20080303070 - Agnello; Paul D. ; et al.	2008-12-11
Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Grant 7,459,384 - Agnello , et al. December 2, 2	2008-12-02
Device having dual etch stop liner and reformed silicide layer and related methods Grant 7,446,062 - Chidambarrao , et al. November 4, 2	2008-11-04
Device having dual etch stop liner and protective layer Grant 7,446,395 - Chidambarrao , et al. November 4, 2	2008-11-04
Device Having Enhanced Stress State And Related Methods App 20080108228 - Chidambarrao; Dureseti ; et al.	2008-05-08
Device having enhanced stress state and related methods Grant 7,348,635 - Chidambarrao , et al. March 25, 2	2008-03-25
Device Having Dual Etch Stop Liner And Reformed Silicide Layer And Related Methods App 20070296044 - Chidambarrao; Dureseti ; et al.	2007-12-27
Device Having Dual Etch Stop Liner And Protective Layer App 20070292696 - Chidambarrao; Dureseti ; et al.	2007-12-20
Method for forming dual etch stop liner and protective layer in a semiconductor device Grant 7,306,983 - Chidambarrao , et al. December 11, 2	2007-12-11
Semiconductor Device Structure Having Low And High Performance Devices Of Same Conductive Type On Same Substrate App 20070158753 - Arnold; John C. ; et al.	2007-07-12
Opc Trimming For Performance App 20070106968 - Culp; James A. ; et al.	2007-05-10
Device Having Dual Etch Stop Liner And Reformed Silicide Layer And Related Methods App 20060128145 - Chidambarrao; Dureseti ; et al.	2006-06-15
Device Having Enhanced Stress State And Related Methods App 20060128091 - Chidambarrao; Dureseti ; et al.	2006-06-15
Device Having Dual Etch Stop Liner And Protective Layer And Related Methods App 20060128086 - Chidambarrao; Dureseti ; et al.	2006-06-15
Apparatus and method to improve resist line roughness in semiconductor wafer processing App 20060110685 - Li; Wai-kin ; et al.	2006-05-25
Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM Grant 7,030,012 - Divakaruni , et al. April 18, 2	2006-04-18
Apparatus and method to improve resist line roughness in semiconductor wafer processing Grant 7,018,779 - Li , et al. March 28, 2	2006-03-28
Nitride and polysilicon interface with titanium layer App 20060001162 - Schutz; Ronald J. ; et al.	2006-01-05
Preventing Cavitation In High Aspect Ratio Dielectric Regions Of Semiconductor Device App 20050287798 - Agnello, Paul D. ; et al.	2005-12-29
Method For Manufacturing Tungsten/polysilicon Word Line Structure In Vertical Dram And Device Manufactured Thereby App 20050202672 - Divakaruni, Ramachandra ; et al.	2005-09-15
Gate metal recess for oxidation protection and parasitic capacitance reduction Grant 6,908,806 - Yang , et al. June 21, 2	2005-06-21
Method for forming TTO nitride liner for improved collar protection and TTO reliability Grant 6,897,107 - Divakaruni , et al. May 24, 2	2005-05-24
Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts App 20040256651 - Dyer, Thomas W. ; et al.	2004-12-23
TTO nitride liner for improved collar protection and TTO reliability Grant 6,809,368 - Divakaruni , et al. October 26, 2	2004-10-26
Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts Grant 6,794,242 - Dyer , et al. September 21, 2	2004-09-21
Three layer aluminum deposition process for high aspect ratio CL contacts Grant 6,794,282 - Goebel , et al. September 21, 2	2004-09-21
Structure and methods for process integration in vertical DRAM cell fabrication Grant 6,790,739 - Malik , et al. September 14, 2	2004-09-14
TTO nitride liner for improved collar protection and TTO reliability App 20040155275 - Divakaruni, Rama ; et al.	2004-08-12
Apparatus and method to improve resist line roughness in semiconductor wafer processing App 20040131979 - Li, Wai-kin ; et al.	2004-07-08
TTO nitride liner for improved collar protection and TTO reliability App 20040106258 - Divakaruni, Rama ; et al.	2004-06-03
Three layer aluminum deposition process for high aspect ratio CL contacts App 20040102001 - Goebel, Thomas ; et al.	2004-05-27
Self-aligned contact formation using double SiN spacers Grant 6,724,054 - Kang , et al. April 20, 2	2004-04-20
Structure and method for dual work function logic devices in vertical DRAM process Grant 6,635,526 - Malik , et al. October 21, 2	2003-10-21
Structure And Methods For Process Integration In Vertical Dram Cell Fabrication App 20030186502 - Malik, Rajeev ; et al.	2003-10-02
Structure and methods for process integration in vertical DRAM cell fabrication Grant 6,620,676 - Malik , et al. September 16, 2	2003-09-16
Modified vertical MOSFET and methods of formation thereof Grant 6,541,810 - Divakaruni , et al. April 1, 2	2003-04-01
Modified vertical MOSFET and methods of formation thereof App 20030001200 - Divakaruni, Ramachandra ; et al.	2003-01-02
Structure and methods for process integration in vertical DRAM cell fabrication App 20030003653 - Malik, Rajeev ; et al.	2003-01-02
TTO nitride liner for improved collar protection and TTO reliability App 20020149047 - Divakaruni, Rama ; et al.	2002-10-17
Method for forming and filling isolation trenches Grant 6,294,423 - Malik , et al. September 25, 2	2001-09-25

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