U.S. patent application number 10/448656 was filed with the patent office on 2004-12-02 for method and pattern for reducing interconnect failures.
Invention is credited to Hsia, Chin-Chiu, Huang, Tai-Chun, Wan, Wen-Kai, Yao, Chih-Hsiang.
Application Number | 20040238959 10/448656 |
Document ID | / |
Family ID | 33451547 |
Filed Date | 2004-12-02 |
United States Patent
Application |
20040238959 |
Kind Code |
A1 |
Yao, Chih-Hsiang ; et
al. |
December 2, 2004 |
METHOD AND PATTERN FOR REDUCING INTERCONNECT FAILURES
Abstract
A method and a pattern for reducing interconnect failures are
described. The method and pattern are used for a multilevel
structure of metal/dielectric/metal. At least one assistant pattern
is attached to one metal layer of the multilevel structure. A
thermal stress gradient resulting from the assistant pattern can
collect vacancies of the metal layer, so as to prevent
stress-induced voids from generating at the bottom of a via plug
which connects the two metal layers.
Inventors: |
Yao, Chih-Hsiang; (Taipei,
TW) ; Wan, Wen-Kai; (Hsinchu City, TW) ;
Huang, Tai-Chun; (Kaohsiung, TW) ; Hsia,
Chin-Chiu; (Taipei, TW) |
Correspondence
Address: |
SEYFARTH SHAW
55 EAST MONROE STREET
SUITE 4200
CHICAGO
IL
60603-5803
US
|
Family ID: |
33451547 |
Appl. No.: |
10/448656 |
Filed: |
May 30, 2003 |
Current U.S.
Class: |
257/758 ;
257/E23.145; 257/E23.151 |
Current CPC
Class: |
H01L 23/528 20130101;
H01L 2924/0002 20130101; H01L 23/5226 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/758 |
International
Class: |
H01L 023/48 |
Claims
1. A pattern for reducing interconnect failures, the pattern for
reducing interconnect failures comprising: a first metal layer; a
second metal layer; a dielectric layer, between the first metal
layer and the second metal layer; a first via plug in the
dielectric layer, a first end of the first via plug is connected
with the first metal layer, and a second end of the first via plug
is connected with the second metal layer; and at least one first
line extension, attached to the first metal layer, wherein when the
first via plug is connected with a second line extension attached
to the first metal layer, the first line extension and the second
line extension are on the same side of the first metal layer, and
the first line extension collects vacancies of the first metal
layer to prevent the vacancies of the first metal layer from being
accumulated at a bottom of the first via plug and then forming
voids.
2-5. (canceled)
6. The pattern for reducing interconnect failures of claim 1,
wherein a material of the first via plug, the first metal layer,
the second metal layer, and the first line extension is copper.
7. The pattern for reducing interconnect failures of claim 1,
wherein a material of the dielectric layer is a low k material.
8. A pattern for reducing interconnect failures, the pattern for
reducing interconnect failures comprising: a first metal layer,
having a line extension; a second metal layer; a dielectric layer,
between the first metal layer and the second metal layer; and a via
plug in the dielectric layer, a first end of the via plug is
connected with the line extension, and a second end of the via plug
is connected with the second metal layer, wherein the line
extension having at least one turning corner between the first
metal layer and the via plug, the turning corner avoids vacancies
in the first metal layer being driven to a bottom of the via
plug.
9. The pattern for reducing interconnect failures of claim 8,
wherein an angle of the turning corner is 90 degrees.
10. The pattern for reducing interconnect failures of claim 8,
wherein a material of the via plug, the first metal layer, the
second metal layer and the line extension is copper.
11. The pattern for reducing interconnect failures of claim 8,
wherein a material of the dielectric layer is a low k material.
12. In an interconnect having a first via plug to connect a first
metal layer and a second metal layer, an improvement thereto
comprising: at least one first line extension, attached to the
first metal layer, wherein when the first via plug is connected
with a second line extension attached to the first metal layer, the
first line extension and the second line extension are on the same
side of the first metal layer, and the first line extension
collects vacancies of the first metal layer to prevent the
vacancies of the first metal layer from being accumulated at a
bottom of the first via plug and then forming voids.
13-16. (canceled)
17. The interconnect of claim 12, wherein a material of the first
via plug, the first metal layer, the second metal layer, and the
first line extension is copper.
18. In an interconnect having a via plug to connect a first metal
layer and a line extension attached to a second metal layer, an
improvement thereto comprising: the line extension having at least
one turning corner between the second metal layer and the via plug,
wherein the turning corner avoids vacancies in the second metal
layer being driven to a bottom of the via plug.
19. The interconnect of claim 18, wherein an angle of the turning
corner is 90 degrees.
20. The interconnect of claim 18, wherein a material of the via
plug, the first metal layer, the second metal layer and the line
extension is copper.
21. A pattern for reducing interconnect failures, the pattern for
reducing interconnect failures comprising: a first metal layer; a
second metal layer; a dielectric layer, between the first metal
layer and the second metal layer; a first via plug in the
dielectric layer, a first end of the first via plug is connected
with the first metal layer, and a second end of the first via plug
is connected with the second metal layer; and at least one second
via plug in the dielectric layer, a first end of the second plug is
connected with the first metal layer, wherein when the first via
plug is connected to a line extension attached to the first metal
layer, the first end of the second via plug is not connected to the
line extension to avoid interrupting the line extension, and the
second via plug collects vacancies of the first metal layer to
prevent the vacancies of the first metal layer from being
accumulated at a bottom of the first via plug and then forming
voids.
22. The pattern for reducing interconnect failures of claim 21,
wherein a material of the first via plug, the first metal layer,
the second metal layer, and the second via plug is copper.
23. The pattern for reducing interconnect failures of claim 21,
wherein a material of the dielectric layer is a low k material.
24. In an interconnect having a first via plug to connect a first
metal layer and a second metal layer, an improvement thereto
comprising: at least one second via plug in the dielectric layer, a
first end of the second plug is connected with the first metal
layer, wherein when the first via plug is connected to a line
extension attached to the first metal layer, the first end of the
second via plug is not connected to the line extension to avoid
interrupting the line extension, and the second via plug collects
vacancies of the first metal layer to prevent the vacancies of the
first metal layer from being accumulated at a bottom of the first
via plug and then forming voids.
25. The interconnect of claim 24, wherein a material of the first
via plug, the first metal layer, the second metal layer, and the
second via plug is copper.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of Invention
[0002] The present invention relates to semiconductor structure and
process. More particularly, the present invention relates to a
method and pattern for reducing interconnect failures.
[0003] 2. Description of Related Art
[0004] An integrated circuit is formed with many electronic
elements and circuits shrunk on a microchip. High-density
integrated circuits, such as very large scale integration (VLSI)
circuits, are typically formed with two or more metal wires serving
as multilevel structures to comply with a very high density of
devices.
[0005] Interconnect structures, such as via plugs, connect the
metal wires of the multilevel structure to form a complete circuit.
The isolation structures in the metal wires are achieved by the
formation of an inter-metal dielectric (IMD) layer. Recently, a
process of fabricating the multilevel interconnect structure which
forms the metal wire and the via plug at the same time has been
developed, and is called a dual damascene process.
[0006] Aluminum (Al) is a commonly used conductive material for
connecting various devices in the conventional semiconductor
process because of its high conductivity, low price, and facility
of deposition and etching. As the integrated density increases, the
capacitance effect between the metal wires increases. Consequently,
the resistance-capacitance time delay (RC delay time) increases,
and cross talk between the metal wires becomes more frequent. The
metal wire thus carries a current flow at a slower speed.
[0007] In the various factors, the inherent resistance of a metal
wire and parasitic capacitance between two metal wires are crucial
factors for determining the speed of the current flow. The
parasitic capacitance can be reduced by insulating metal wiring
layers with low k (dielectric constant) materials, the dielectric
constants thereof being generally lower than 3.5. To achieve the
reduction of the resistances of metal wires, materials with low
resistances are selected for fabricating the metal wires. Copper
(Cu) having a relatively high melting point, low resistance (about
1.7 .mu..OMEGA.-cm) and high anti electro-migration ability
gradually has become the new material of choice for replacing
aluminum.
[0008] FIG. 1A illustrates a schematic view of a conventional via
plug structure between two metal layers. The via plug structure 100
is a metal layer/dielectric layer/metal layer structure. A metal
layer 104 having a line extension attached thereto is connected to
a metal layer 106 by a via plug 108. FIG. 1B illustrates a partial
side view of FIG. 1A. The other portions of the two metal layers
104 and 106 are insulated by a dielectric layer 102 as illustrated
in FIG. 1B.
[0009] However, it is hard to avoid formation of some vacancies on
the edges of grains of the metal layer 104 as the metal layer 104
is formed. As a result of a stress gradient, the vacancies are
driven to pass through the line extension 104a, and collect at the
bottom of the via plug 108, named via plug bottom 112, so as to
form stress-induced voids (SIVs). The SIV is at the via plug bottom
112 and causes the via plug 108 to be interrupted, thereby
generating interconnect failures.
[0010] The SIV formation mechanism is usually explained as
vacancies in the metal layer being driven by the thermal stress
gradient to a certain area to form voids. The thermal stress
gradient results from the stress variations of different areas with
different thermal expansion constants. For an integrated circuit,
the variations of temperature during processing or operating, and
the mismatching of different materials, generally generate a
thermal stress gradient.
[0011] For example, when there are wires with different widths in
the metal layers, such as the metal layers 104 and the line
extension 104a in FIG. 1A, a thermal stress gradient is generated
due to their different area dimensions as their temperatures are
varying The voids resulting from the thermal stress gradient
especially tend to form at the via plug bottom 112, because the via
plug bottom 112 is the lowest stress area. Thus the via plug 108 is
interrupted.
SUMMARY OF THE INVENTION
[0012] It is therefore an objective of the present invention to
provide method and pattern for reducing interconnect failures,
which satisfies the need to avoid the via plug bottom being
interrupted by voids.
[0013] In accordance with the foregoing and other objectives of the
present invention, a method and a pattern for reducing the
interconnect failures are described. At least one assistant
pattern, such as a 2-D dummy line extension or a 3-D dummy via
plug, is attached to one metal layer of the multilevel structure. A
thermal stress gradient resulting from the assistant pattern can
collect vacancies of the metal layer, so as to prevent
stress-induced voids from being generated at the bottom of a via
plug which connects the two metal layers.
[0014] When a via plug connects one metal layer and a line
extension attached to the other metal layer, the invention improves
the interconnect structure by imposing at least one turning corner
upon the line extension, the turning corner being located between
the other metal layer and the via plug. The turning corner is the
high stress area and prevents the vacancies of the other metal
layer from being driven to the line extension, therefore keeping
the via plug bottom from being interrupted.
[0015] In one preferred embodiments of the present inventions, a
material of the two metal layers, the via plug and the assistant
pattern is copper, and a material of the dielectric layer is a low
k material.
[0016] A higher quantity of assistant pattern has a greater ability
of dissipating vacancies to prevent the voids from being generated
at the via plug bottom. Additionally, if the assistant pattern is
nearer the line extension, the probability of sharing the vacancies
is higher and the effect of preventing the voids from being
generated at the via plug bottom is therefore also better.
[0017] Besides, the dummy via plug is not located at the line
extension or the junction of the line extension and the metal
layer. If it were, the vacancies gathered by the dummy via plug
would form voids, and then the line extension or the junction would
be interrupted, resulting in the metal layer being interrupted.
[0018] In another preferred embodiment of the invention, a turning
corner is imposed upon the line extension attached to the metal
layer. The turning corner is located between the metal layer and
the via plug. The angle of the turning corner is 90 degrees, but
other turning corners with other degrees that are high stress areas
are also applicable in the present invention.
[0019] In addition, more than one turning corner can be used.
Multiple turning corners imposed upon the line extension improve
void prevention at the via plug bottom.
[0020] In conclusion, the dummy line extensions and the dummy vias
not only reduce the area dimension having a local stress gradient,
called an effective vacancy diffusion area, that drives the
vacancies towards the via plug bottom, but also share the vacancies
and diversify the destinations of the traveling vacancies.
[0021] The turning corner provides a high stress area in the line
extension connecting with the via plug, which increases the stress
migration incubation and reduces the probability of interconnect
failures caused by the stress-induced voids. The stress
migration-related interconnect reliability is thus improved.
[0022] It is to be understood that both the foregoing general
description and the following detailed description are examples,
and are intended to provide further explanation of the invention as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] These and other features, aspects, and advantages of the
present invention will become better understood with regard to the
following description, appended claims, and accompanying drawings
where:
[0024] FIG. 1A illustrates a schematic view of a conventional via
plug structure between two metal layers;
[0025] FIG. 1B illustrates a side view of FIG. 1A;
[0026] FIG. 2 illustrates a schematic view of one preferred
embodiment of this invention;
[0027] FIG. 3 illustrates a schematic view of another preferred
embodiment of this invention;
[0028] FIG. 4A illustrates a schematic view of another preferred
embodiment of this invention; and
[0029] FIG. 4B illustrates a schematic view of another preferred
embodiment of this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0030] Reference will now be made in detail to the present
preferred embodiments of the invention, examples of which are
illustrated in the accompanying drawings. Wherever possible, the
same reference numbers are used in the drawings and the description
to refer to the same or like parts.
[0031] The present invention provides method and pattern for
avoiding interruption of the via plug bottom by voids to reduce
interconnect failures.
[0032] The invention is used for a multilevel structure of metal
layer/dielectric layer/metal layer. At least one assistant pattern,
like a 2-D dummy line extension or a 3-D dummy via plug, is
attached to one metal layer of the multilevel structure. A thermal
stress gradient resulting from the assistant pattern can collect
vacancies of the metal layer, so as to prevent stress-induced voids
from generating at the bottom of a via plug which connects the two
metal layers.
[0033] When a via plug connects one metal layer and a line
extension attached to the other metal layer, the invention improves
the interconnect structure by imposing at least one turning corner
upon the line extension, the turning corner being located between
the other metal layer and the via plug. The turning corner is a
high stress area and prevents the vacancies of the other metal
layer from being driven to the line extension, therefore keeping
the via plug bottom from being interrupted.
[0034] According to one preferred embodiment of the invention, a
material of the two metal layers, the via plug, and the assistant
pattern is copper, and a material of the dielectric layer is a low
k material. However, the invention is also used to improve the
foregoing structures when composed of other metal materials and
when dielectric materials insulate the two metal layers, and thus
the invention is not limited by the preferred embodiment.
[0035] FIG. 2 illustrates a schematic view of one preferred
embodiment of this invention. For a clear explanation, FIG. 2 does
not illustrate the dielectric layer 102 between the metal layers
104 and 106 as in FIG. 1B. In this preferred embodiment, a dummy
line extension 214 is attached to the metal layer 104. The dummy
line extension 214 shares the vacancies of the metal layer 104 to
avoid the vacancies gathering at the via plug bottom 112 to form
voids so as to interrupt the via plug 108.
[0036] A higher quantity of dummy line extensions 214 increases
vacancy dissipation and thus void formation at the via plug bottom
112 is better. Besides, if the dummy line extension 214 is nearer
the line extension 104a, the probability of sharing the vacancies
is higher and the effect of preventing the voids from being
generated at the via plug bottom 112 is also better.
[0037] FIG. 3 illustrates a schematic view of another preferred
embodiment of this invention. For a clearer explanation, FIG. 3
also does not include dielectric layer 102 between the metal layers
104 and 106 as in FIG. 1B. In this preferred embodiment, a dummy
via plug 212 is located in the dielectric layer 102 and an end of
the dummy via 212 is connected with the metal layer 104. The dummy
via plug 212 shares the vacancies of the metal layer 104 to avoid
vacancies gathering at the via plug bottom 112 to form voids so as
to interrupt the via plug 108.
[0038] Similarly, more dummy via plugs 212 results in a greater
vacancy dissipation ability and thus a better void generation
prevention at the via plug bottom 112 is better. Besides, if the
dummy via 212 plug is nearer the line extension 104a, the
probability of sharing the vacancies is higher and the effect of
preventing voids from generating at the via plug bottom 112 thus is
also better.
[0039] However, the dummy via plug 212 is not located at the line
extension 104a or the junction of the line extension 104a and the
metal layer 104. If it were, the vacancies gathered by the dummy
via plug 212 would form voids, and then interrupt the line
extension 104a or the junction, thus interrupting the metal layer
104 and the metal layer 106 instead.
[0040] FIG. 4A illustrates a schematic view of another preferred
embodiment of this invention. For a clearer explanation, FIG. 4
also does not illustrate the dielectric layer 102 between the metal
layers 104 and 106 as in FIG. 1B. In this preferred embodiment, a
turning corner 402a is imposed upon the line extension 404a
attached to the metal layer 104. The turning corner 402a is located
between the metal layer 104 and the via plug 108. Because the
thermal stress of the turning corner 402a is higher than that of
the metal layer 104, the vacancies of the metal layer 104 are
pushed back when they attempt enter the line extension 404a The
turning corner 402a prevent the vacancies of the metal layer 104
from being driven to the line extension 404a and therefore keeps
the via plug 108 from being interrupted by voids.
[0041] In this preferred embodiment, the angle of the turning
corner 402a is 90 degrees, but other turning corners with different
degrees that are high stress areas are also applicable in the
present invention, which is not limited by the embodiment In
addition, more than one turning corner can be employed, as
exemplified by turning corners 402a and 402b in FIG. 4B Multiple
turning corners imposed upon the line extension 404b improve the
void generation prevention ability at the via plug bottom 112.
[0042] In one aspect, the dummy line extensions and the dummy vias
not only reduce the area dimension having a local stress gradient,
called an effective vacancy diffusion area, that drives the
vacancies towards the via plug bottom, but also share the vacancies
and diversify the destinations of the traveling vacancies.
[0043] In another aspect, the turning corner provides a high stress
area in the line extension connecting with the via plug, which
increases the stress migration incubation and reduces the
probability of interconnect failures caused by the stress-induced
voids. The stress migration related interconnect reliability is
thus improved.
[0044] In conclusion, the dummy line extensions and the dummy vias
can share the vacancies of the metal layer, and the turning corners
can prevent the vacancies from entering the line extension. The
invention therefore prevents the voids from being generated at the
via plug bottom to interrupt the interconnects of the metal
layer/dielectric layer/metal layer/multilevel structure.
[0045] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
present invention cover modifications and variations of this
invention provided they fall within the scope of the following
claims and their equivalents.
* * * * *