Hsia; Chin-Chiu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hsia; Chin-Chiu.The latest application filed is for "shallow trench isolation dummy pattern and layout method using the same".

Company Profile

0.17.13

Hsia; Chin-Chiu - Taipei TW
Hsia; Chin-Chiu - Taipei City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Shallow trench isolation dummy pattern and layout method using the same Grant 8,136,070 - Doong , et al. March 13, 2	2012-03-13
Shallow trench isolation dummy pattern and layout method using the same Grant 7,849,432 - Doong , et al. December 7, 2	2010-12-07
Shallow Trench Isolation Dummy Pattern and Layout Method Using the Same App 20100252907 - Doong; Kelvin Yih-Yuh ; et al.	2010-10-07
Seal ring structure for integrated circuit chips Grant 7,777,338 - Yao , et al. August 17, 2	2010-08-17
Bond pad structure for wire bonding Grant 7,592,710 - Hsia , et al. September 22, 2	2009-09-22
Bonding pad structure and method for making the same Grant 7,470,994 - Huang , et al. December 30, 2	2008-12-30
Shallow Trench Isolation Dummy Pattern And Layout Method Using The Same App 20080209381 - Doong; Kelvin Yih-Yuh ; et al.	2008-08-28
Shallow trench isolation dummy pattern and layout method using the same Grant 7,388,263 - Doong , et al. June 17, 2	2008-06-17
Bonding pad structure and method for making the same App 20080003820 - Huang; Tai-Chun ; et al.	2008-01-03
Stripe board dummy metal for reducing coupling capacitance Grant 7,312,486 - Lin , et al. December 25, 2	2007-12-25
Method for forming an interconnection structure for ic metallization Grant 7,291,557 - Wan , et al. November 6, 2	2007-11-06
Bond pad structure for wire bonding App 20070205508 - Hsia; Chin-Chiu ; et al.	2007-09-06
Semiconductor bonding pad structure Grant 7,253,531 - Huang , et al. August 7, 2	2007-08-07
Multiple etch-stop layer deposition scheme and materials Grant 7,151,052 - Huang , et al. December 19, 2	2006-12-19
Multiple Etch-stop Layer Deposition Scheme And Materials App 20060246686 - Huang; Tai-Chun ; et al.	2006-11-02
Structure for reducing stress-induced voiding in an interconnect of integrated circuits App 20060108696 - Yao; Chih-Hsiang ; et al.	2006-05-25
Structure for reducing stress-induced voiding in an interconnect of integrated circuits Grant 7,042,097 - Yao , et al. May 9, 2	2006-05-09
Interconnection structure for IC metallization App 20060057841 - Wan; Wen-Kai ; et al.	2006-03-16
Methods for enhancing die saw and packaging reliability App 20060055002 - Yao; Chih-Hsiang ; et al.	2006-03-16
Seal ring structure for integrated circuit chips App 20060055007 - Yao; Chih-Hsiang ; et al.	2006-03-16
Shallow trench isolation dummy pattern and layout method using the same App 20050112840 - Doong, Kelvin Yih-Yuh ; et al.	2005-05-26
Test structure for differentiating the line and via contribution in stress migration Grant 6,835,578 - Lin , et al. December 28, 2	2004-12-28
Method and pattern for reducing interconnect failures Grant 6,831,365 - Yao , et al. December 14, 2	2004-12-14
Structure for reducing stress-induced voiding in an interconnect of integrated circuits App 20040245639 - Yao, Chih-Hsiang ; et al.	2004-12-09
Method And Pattern For Reducing Interconnect Failures App 20040238959 - Yao, Chih-Hsiang ; et al.	2004-12-02
Scheme to define laser fuse in dual damascene CU process Grant 6,737,345 - Lin , et al. May 18, 2	2004-05-18
Bonding pad and method for manufacturing it Grant 6,566,752 - Hsia , et al. May 20, 2	2003-05-20
Bonding pad and method for manufacturing it App 20020149115 - Hsia, Chin Chiu ; et al.	2002-10-17
Bonding pad and method for manufacturing it Grant 6,426,555 - Hsia , et al. July 30, 2	2002-07-30
Illumination aperture filter design using superposition Grant 6,361,909 - Gau , et al. March 26, 2	2002-03-26

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