Yao; Chih-Hsiang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yao; Chih-Hsiang.The latest application filed is for "semiconductor device and manufacturing method thereof".

Company Profile

3.39.38

Yao; Chih-Hsiang - Taipei TW
Yao; Chih-Hsiang - Hsin-Chu TW
Yao; Chih-Hsiang - Taipei City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device and manufacturing method thereof Grant 10,872,806 - Huang , et al. December 22, 2	2020-12-22
Semiconductor Device And Manufacturing Method Thereof App 20190139815 - HUANG; Yi-Chun ; et al.	2019-05-09
Circuit design method and system Grant 10,169,506 - Wang , et al. J	2019-01-01
Semiconductor device and manufacturing method thereof Grant 10,170,355 - Huang , et al. J	2019-01-01
Interconnect structures and methods of forming same Grant 9,793,212 - Huang , et al. October 17, 2	2017-10-17
Semiconductor Device And Manufacturing Method Thereof App 20170271198 - HUANG; Yi-Chun ; et al.	2017-09-21
Semiconductor Device And Manufacturing Method Thereof App 20170207112 - Huang; Yi-Chun ; et al.	2017-07-20
Semiconductor device and manufacturing method thereof Grant 9,711,391 - Huang , et al. July 18, 2	2017-07-18
Circuit Design Method And System App 20170039310 - WANG; Chung-Hsing ; et al.	2017-02-09
Method of generating techfile having reduced corner variation value Grant 9,477,803 - Wang , et al. October 25, 2	2016-10-25
Interconnect Structures and Methods of Forming Same App 20160307793 - Huang; Yi-Chun ; et al.	2016-10-20
Method for line stress reduction through dummy shoulder structures Grant 9,437,485 - Kuo , et al. September 6, 2	2016-09-06
Method Of Generating Techfile Having Reduced Corner Variation Value App 20160034631 - WANG; Chung-Hsing ; et al.	2016-02-04
Conductor layout technique to reduce stress-induced void formations Grant 9,209,079 - Chi , et al. December 8, 2	2015-12-08
Novel Conductor Layout Technique To Reduce Stress-induced Void Formations App 20150011086 - CHI; Min-Hwa ; et al.	2015-01-08
Conductor layout technique to reduce stress-induced void formations Grant 8,836,141 - Chi , et al. September 16, 2	2014-09-16
Dummy Shoulder Structure For Line Stress Reduction App 20140208283 - Kuo; Cheng-Cheng ; et al.	2014-07-24
Dummy shoulder structure for line stress reduction Grant 8,692,351 - Kuo , et al. April 8, 2	2014-04-08
Metal line and via formation using hard masks Grant 8,669,661 - Yao , et al. March 11, 2	2014-03-11
Novel Conductor Layout Technique To Reduce Stress-induced Void Formations App 20130241079 - Chi; Min-Hwa ; et al.	2013-09-19
Metal Line and Via Formation Using Hard Masks App 20130207273 - Yao; Chih-Hsiang ; et al.	2013-08-15
Method for stacked contact with low aspect ratio Grant 8,450,200 - Yu , et al. May 28, 2	2013-05-28
Conductor layout technique to reduce stress-induced void formations Grant 8,435,802 - Chi , et al. May 7, 2	2013-05-07
Dummy Shoulder Structure For Line Stress Reduction App 20110241207 - Kuo; Cheng Cheng ; et al.	2011-10-06
Method for Stacked Contact with Low Aspect Ratio App 20110092019 - Yu; Chen-Hua ; et al.	2011-04-21
Stacked contact with low aspect ratio Grant 7,880,303 - Yu , et al. February 1, 2	2011-02-01
Semiconductor device fault detection system and method Grant 7,791,070 - Huang , et al. September 7, 2	2010-09-07
Seal ring structure for integrated circuit chips Grant 7,777,338 - Yao , et al. August 17, 2	2010-08-17
Integrated circuit having improved interconnect structure Grant 7,772,701 - Yao , et al. August 10, 2	2010-08-10
Bond pad structure with stress-buffering layer capping interconnection metal layer Grant 7,741,714 - Huang , et al. June 22, 2	2010-06-22
Bond pad structure for wire bonding Grant 7,592,710 - Hsia , et al. September 22, 2	2009-09-22
Bonding pad structure and method for making the same Grant 7,470,994 - Huang , et al. December 30, 2	2008-12-30
Stacked contact with low aspect ratio App 20080191352 - Yu; Chen-Hua ; et al.	2008-08-14
Bonding pad structure and method for making the same App 20080003820 - Huang; Tai-Chun ; et al.	2008-01-03
Integrated Circuit Having Improved Interconnect Structure App 20070284747 - Yao; Chih-Hsiang ; et al.	2007-12-13
Novel conductor layout technique to reduce stress-induced void formations App 20070269907 - Chi; Min-Hwa ; et al.	2007-11-22
Bond pad structure for wire bonding App 20070205508 - Hsia; Chin-Chiu ; et al.	2007-09-06
Non-repeated and non-uniform width seal ring structure Grant 7,265,436 - Huang , et al. September 4, 2	2007-09-04
Semiconductor bonding pad structure Grant 7,253,531 - Huang , et al. August 7, 2	2007-08-07
Integration film scheme for copper / low-k interconnect Grant 7,244,673 - Huang , et al. July 17, 2	2007-07-17
Semiconductor device fault detection system and method App 20070096092 - Huang; Tai-Chun ; et al.	2007-05-03
Multiple etch-stop layer deposition scheme and materials Grant 7,151,052 - Huang , et al. December 19, 2	2006-12-19
Multiple Etch-stop Layer Deposition Scheme And Materials App 20060246686 - Huang; Tai-Chun ; et al.	2006-11-02
Semiconductor chip singulation method Grant 7,098,077 - Huang , et al. August 29, 2	2006-08-29
Structure and method for reinforcing a bond pad on a chip Grant 7,081,679 - Huang , et al. July 25, 2	2006-07-25
Test patterns for measurement of effective vacancy diffusion area Grant 7,074,629 - Yao , et al. July 11, 2	2006-07-11
Structure for reducing stress-induced voiding in an interconnect of integrated circuits App 20060108696 - Yao; Chih-Hsiang ; et al.	2006-05-25
Structure for reducing stress-induced voiding in an interconnect of integrated circuits Grant 7,042,097 - Yao , et al. May 9, 2	2006-05-09
Bond pad structure with stress-buffering layer capping interconnection metal layer App 20060091536 - Huang; Tai-Chun ; et al.	2006-05-04
Seal ring structure for integrated circuit chips App 20060055007 - Yao; Chih-Hsiang ; et al.	2006-03-16
Methods for enhancing die saw and packaging reliability App 20060055002 - Yao; Chih-Hsiang ; et al.	2006-03-16
Non-repeated and non-uniform width seal ring structure App 20050179213 - Huang, Tai-Chun ; et al.	2005-08-18
Bond pad for flip chip package Grant 6,927,498 - Huang , et al. August 9, 2	2005-08-09
Semiconductor chip singulation method App 20050158967 - Huang, Tai-Chun ; et al.	2005-07-21
Test patterns for measurement of effective vacancy diffusion area App 20050139827 - Yao, Chih-Hsiang ; et al.	2005-06-30
Chip orientation and attachment method App 20050133241 - Chi, Kuan-Shou ; et al.	2005-06-23
Structure and method for reinforcing a bond pad on a chip App 20050127529 - Huang, Tai-Chun ; et al.	2005-06-16
Bond pad for flip chip package App 20050104224 - Huang, Tai-Chun ; et al.	2005-05-19
Integration film scheme for copper / low-k interconnect App 20050098896 - Huang, Tai-Chun ; et al.	2005-05-12
Test patterns for measurement of effective vacancy diffusion area Grant 6,864,701 - Yao , et al. March 8, 2	2005-03-08
Test Patterns For Measurement Of Effective Vacancy Diffusion Area App 20050006782 - Yao, Chih-Hsiang ; et al.	2005-01-13
Hybrid copper/low k dielectric interconnect integration method and device App 20040251549 - Huang, Tai-Chun ; et al.	2004-12-16
Method and pattern for reducing interconnect failures Grant 6,831,365 - Yao , et al. December 14, 2	2004-12-14
Structure for reducing stress-induced voiding in an interconnect of integrated circuits App 20040245639 - Yao, Chih-Hsiang ; et al.	2004-12-09
Method And Pattern For Reducing Interconnect Failures App 20040238959 - Yao, Chih-Hsiang ; et al.	2004-12-02
Method for improving semiconductor process wafer CMP uniformity while avoiding fracture Grant 6,812,069 - Tseng , et al. November 2, 2	2004-11-02
Method of reducing visible light induced arcing in a semiconductor wafer manufacturing process Grant 6,787,484 - Yao , et al. September 7, 2	2004-09-07
Test patterns for measurement of low-k dielectric cracking thresholds Grant 6,787,803 - Yao , et al. September 7, 2	2004-09-07
Method of avoiding dielectric arcing Grant 6,759,342 - Yao , et al. July 6, 2	2004-07-06
Method for improving semiconductor process wafer CMP uniformity while avoiding fracture App 20040115925 - Tseng, Tung-Ching ; et al.	2004-06-17
Method of reducing visible light induced arcing in a semiconductor wafer manufacturing process App 20040115943 - Yao, Chih-Hsiang ; et al.	2004-06-17
Method Of Avoiding Dielectric Arcing App 20040072405 - Yao, Chih-Hsiang ; et al.	2004-04-15