U.S. patent application number 10/796958 was filed with the patent office on 2004-09-09 for data processor.
This patent application is currently assigned to Hitachi,Ltd. Invention is credited to Hanawa, Makoto, Hasegawa, Atsushi, Kawasaki, Ikuya, Nishimukai, Tadahiko, Uchiyama, Kunio.
Application Number | 20040177231 10/796958 |
Document ID | / |
Family ID | 12861017 |
Filed Date | 2004-09-09 |
United States Patent
Application |
20040177231 |
Kind Code |
A1 |
Nishimukai, Tadahiko ; et
al. |
September 9, 2004 |
Data processor
Abstract
A data processor for executing instructions using operand data
stored in a main memory includes an instruction control unit having
a first associative memory storing instructions read out from the
main memory. The data processor also includes an instruction
controller reading out an instruction from the first associative
memory when the instruction is present in the first associative
memory and reading an instruction from the main memory when the
instruction is not present in the first associative memory. The
controller also has as an output instruction to be executed. An
instruction execution unit has a second associative memory storing
operand data read out from the main memory. An instruction executor
executes the instruction by using operand data read out from the
second associative memory when the operand data is present in the
second associative memory and from the main memory when the operand
data is not present in the second associative memory.
Inventors: |
Nishimukai, Tadahiko;
(Sagamihara-shi, JP) ; Hasegawa, Atsushi; (Tokyo,
JP) ; Uchiyama, Kunio; (Tokyo, JP) ; Kawasaki,
Ikuya; (Tokyo, JP) ; Hanawa, Makoto; (Tokyo,
JP) |
Correspondence
Address: |
KENYON & KENYON
1500 K STREET, N.W., SUITE 700
WASHINGTON
DC
20005
US
|
Assignee: |
Hitachi,Ltd
Tokyo
JP
|
Family ID: |
12861017 |
Appl. No.: |
10/796958 |
Filed: |
March 11, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10796958 |
Mar 11, 2004 |
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09886267 |
Jun 22, 2001 |
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09886267 |
Jun 22, 2001 |
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09396414 |
Sep 15, 1999 |
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6272596 |
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09396414 |
Sep 15, 1999 |
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09113550 |
Jul 10, 1998 |
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5974533 |
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09113550 |
Jul 10, 1998 |
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08886464 |
Jul 1, 1997 |
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5809274 |
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08886464 |
Jul 1, 1997 |
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07978069 |
Nov 18, 1992 |
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5680631 |
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07978069 |
Nov 18, 1992 |
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07596752 |
Oct 12, 1990 |
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07596752 |
Oct 12, 1990 |
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07238260 |
Aug 30, 1988 |
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07238260 |
Aug 30, 1988 |
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06840433 |
Mar 17, 1986 |
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Current U.S.
Class: |
712/1 ;
711/E12.022; 711/E12.046; 712/E9.032; 712/E9.046; 712/E9.055 |
Current CPC
Class: |
G06F 9/3802 20130101;
G06F 9/30047 20130101; G06F 9/3824 20130101; G06F 9/30043 20130101;
G06F 12/0848 20130101; G06F 12/0891 20130101 |
Class at
Publication: |
712/001 |
International
Class: |
G06F 015/00 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 15, 1985 |
JP |
60-50512 |
Claims
What is claimed is:
1. A data processor formed on an LSI chip comprising: an
instruction address generator generating an instruction address; an
instruction cache memory having entries each storing an instruction
corresponding to the instruction address; an instruction decoder
decoding an instruction read out from said cache memory; an operand
address generator generating an operand address in response to an
output signal of said instruction decoder; and an operand cache
memory having entries each storing operand data corresponding to
the operand address in its entry, wherein the data processor
executes a first instruction that makes entries in both of said
instruction cache memory and said operand cache memory ineffective,
wherein the first instruction is stored in a main memory with other
instructions, the main memory being external to the data processor,
wherein the instruction address generator generates the instruction
address as a logic address, and wherein an address of the main
memory is a physical address.
2. A data processor formed on an LSI chip according to claim 1,
further comprising: an execution unit executing an instruction
based on the decoded result at said instruction decoder, wherein
said instruction decoder and said execution unit can be operated in
parallel.
3. A data processor formed on an LSI chip according to claim 2,
further comprising: a ROM storing a control information
corresponding to an instruction, wherein said ROM outputs the
control information corresponding to an instruction output from
said instruction cache memory.
4. A data processor formed on an LSI chip according to claim 2,
wherein said execution unit has an arithmetic circuit, the
arithmetic circuit computing an operand data and outputting the
computed result.
5. A data processor formed on an LSI chip according to claim 2,
wherein each of entries in said instruction cache memory and said
operand cache memory has a valid bit, and wherein when said data
processor executes the instruction that makes entries in both of
said instruction cache memory and said operand cache memory
ineffective, the valid bits of said instruction cache memory and
said operand cache memory are cleared.
6. A data processor formed on an-LSI chip according to claim 2,
wherein each of said instruction cache memory and said operand
cache memory is an associative memory.
7. A data processor formed on an LSI chip according to claim 1,
wherein each of said instruction cache memory and said operand
cache memory is an associative memory.
8. A data processor formed on an LSI chip according to claim 1,
wherein each of entries in said instruction cache memory and said
operand cache memory has a valid bit, and wherein when said data
processor executes the instruction that makes entries in both of
said instruction cache memory and said operand cache memory
ineffective, the valid bits of said instruction cache memory and
said operand cache memory are cleared.
9. A data processor formed on an LSI chip according to claim 1,
further comprising: an address transformation circuit transforming
the logical address generated by said address generator to the
physical address, wherein the address transformation circuit is
connected to the output part inside of the LSI chip.
10. A data processor formed on an LSI chip according to claim 9,
wherein the instruction cache memory stores the instruction address
which is the physical address.
11. A data processor formed on an LSI chip comprising: an
instruction address generator; an instruction cache memory; an
instruction decoder; an operand address generator; and;; an operand
cache memory, wherein the instruction address generator generates
an instruction address, wherein said instruction cache memory has
entries each storing an instruction corresponding to the
instruction address in its entry, wherein into said instruction
decoder is input an instruction from said instruction cache memory
and said decoder outputs a decoded result, wherein said operand
address generator generates an operand address response to the
decoded result of said instruction decoder, wherein said operand
cache memory has entries each storing operand data corresponding to
the operand address in its entry, wherein when the data processor
executes a first instruction, the data processor invalidates the
instruction and operand cache memories, wherein the first
instruction is stored in a main memory with other instructions, the
main memory being external to the data processor, wherein the
instruction address generator generates the instruction address as
a logic address, and wherein an address of the main memory is a
physical address.
12. A data processor formed on an LSI chip according to claim 11,
further comprising: an execution unit executing an instruction
based on the decoded result at said instruction decoder, wherein
said instruction decoder and said execution unit can be operated in
parallel.
13. A data processor formed on an LSI chip according to claim 12,
further comprising: a ROM storing a control information
corresponding to an instruction, wherein said ROM outputs the
control information corresponding to an instruction output from
said instruction cache memory.
14. A data processor formed on an LSI chip according to claim 12,
wherein each of entries in said instruction cache memory and said
operand cache memory has a valid bit, and wherein when said data
processor executes the first instruction, the valid bits of said
instruction cache memory and said operand cache memory are
cleared.
15. A data processor formed on an LSI chip according to claim 12,
wherein each of said instruction cache memory and said operand
cache memory is an associative memory.
16. A data processor formed on an LSI chip according to claim 11,
wherein each of said instruction cache memory and said operand
cache memory is an associative memory.
17. A data processor formed on an LSI chip according to claim 11,
wherein each of entries in said instruction cache memory and said
operand cache memory has a valid bit, and wherein when said data
processor executes the first instruction, the valid bits of said
instruction cache memory and said operand cache memory are
cleared.
18. A data processor formed on an LSI chip according to claim 1 1,
further comprising: a purge control unit; wherein said purge
control unit outputs the first instruction when the purge signal is
input into said purge control circuit.
19. A data processor formed on an LSI chip according to claim 1 1,
further comprising: an address transformation circuit, wherein into
said address transformation circuit is input a logical address
generated by said address generator and said address transformation
circuit outputs a physical address corresponding to the logical
address, and is connected to the output part inside of the LSI
chip.
20. A data processor formed on an LSI chip according to claim 19,
wherein the instruction cache memory stores the instruction address
which is the physical address.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation of application Ser. No. 09/886,267
filed 22 Jun. 2001, which is a division of application Ser. No.
09/396,414 filed Sep. 15, 1999, U.S. Pat. No. 6,272,596, which is a
continuation of application Ser. No. 09/113,550 filed Jul. 10,
1998, U.S. Pat. No. 5,974,533, which is a continuation of
application Ser. No. 08/886,464 filed Jul. 01, 1997, U.S. Pat. No.
5,809,274, which is a continuation of application Ser. No.
07/978,069 filed Nov. 18, 1992, U.S. Pat. No. 5,680,631, which is a
continuation of application Ser. No. 07/596,752 filed Oct. 12, 1990
(abandoned), which is a continuation of application Ser. No.
07/238,260 filed Aug. 30, 1988 (abandoned), which is a division of
application Ser. No. 06/840,433 filed Mar. 17, 1986
(abandoned).
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a data processor capable of
processing instructions at a high speed.
[0003] The data processor of the prior art comprises, as shown in
FIG. 1, an interface circuit 7 for data transfer with a main memory
5, an instruction control unit 3 for controlling an instruction to
be executed, and an instruction execution unit 4 for executing the
instruction. When an instruction read out from the main memory 5 is
transferred to an instruction control unit 3 via a line 73, the
interface circuit 7 and a line 11, the instruction control unit 3
analyzes the instruction and transfers the result to the
instruction execution unit 4 over a line 15. (It will be recognized
that lines 73, 11 and 15 along with others to be described herein
include more than one wire and are actually buses. Thus, the use of
the term "line" herein includes both single conductors and multiple
conductors.) As a result of the analysis, the instruction execution
unit 4 generates a variety of control signals so that respective
gates in the instruction execution unit 4 are opened or closed by
those control signals to execute processing such as arithmetic
operation, storage or shift. An instruction designates an address
via lines 14 and 74 to read out data from the main memory 5 via
lines 13 and 73 or write the arithmetic result in the main memory
5. The instruction control unit 3 designates the read address of a
subsequent instruction in the main memory 5 via a line 12, the
interface circuit 7 and the line 74. By repeating a series of those
operations, data processor 1 executes the program which is stored
in the main memory 5.
[0004] This processor of the prior art is equipped with a cache
memory 71 to allow reading data from the main memory 5 at high
speed. The cache memory 71 is addressed by the address on line 74
so that the data in the corresponding entry are read out but the
main memory 5 is not accessed when the cache memory 71 is accessed.
Consequently, when data are read out from the cache memory,
accessing the main memory is unnecessary, so that reading out of
data is much faster than it would be without said cache memory.
[0005] This processor is exemplified by the data processor which is
disclosed on pages 144 to 148 of the Iwanami Microelectronics
Course, Vol. 5, "Microcomputer Hardare", November, 1984.
[0006] In this processor, however, both the instruction control
unit 3 and the instruction execution unit 4 use lines 73 and 74,
and the cache memory 71 jointly when pipeline control is to be
effected. To prevent conflict, therefore, a selector 72 may inhibit
concurrent use so that one of the units is held on standby.
SUMMARY OF THE INVENTION
[0007] An object of the present invention is to provide a data
processor which can reduce conflict during access of an instruction
control unit and an instruction execution unit to a main memory so
as to process instructions at a high speed.
[0008] The data processor of the present invention enables parallel
operation of the instruction control unit 3 and the instruction
execution unit 4 to effect pipeline control.
[0009] In order to eliminate the above-specified defects, according
to the present invention, the instruction control unit and the
instruction execution unit are equipped with associative memories,
and first access the corresponding associative memory so that they
do not use common address lines and data lines, before data are
present, to access the main memory. Namely, the instruction control
unit has a first associative memory storing instructions read out
from the main memory, and an instruction controller which reads out
an instruction from the first associative memory when the
instruction is present in the first associative memory and from the
main memory when the instruction is not present in the first
associative memory. The instruction execution unit has a second
associative memory storing operand data read out from the main
memory, and an instruction executor for executing the instruction
by using operand data read out from the second associative memory
when operand data is present in the second associative memory and
from the main memory when the operand data is not present in the
second associative memory.
[0010] As a result, no conflict arises between the instruction
control unit and the instruction execution unit when data are
present in the associative memory of a least one of the two
memories. This reduces the chance of one of the units being held on
standby. As a result, the instructions can be processed more
rapidly.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a circuit diagram showing the data processor of
the prior art.
[0012] FIGS. 2A and 2B are diagrams showing the instruction format
used in the present invention.
[0013] FIGS. 3A and 3B are diagrams showing the format of the
special instructions used in the present invention.
[0014] FIG. 4 is a diagram showing the construction of an
embodiment of the present invention.
[0015] FIG. 5 is a diagram showing the construction of the address
generator 32 used in FIG. 4
[0016] FIG. 6 is a diagram showing the construction of the
associative memory 31 used in FIG. 4.
[0017] FIG. 7 is a diagram showing the construction of the
associative memories 36, 37 and 38 used in FIG. 4.
[0018] FIG. 8 is a diagram showing the construction of the
processor 45 used in FIG. 4.
[0019] FIG. 9 is a diagram showing the construction of the operand
buffer 24 used in FIG. 4.
[0020] FIG. 10 is a diagram showing the line buffer 25 used in FIG.
4.
[0021] FIG. 11 is a diagram showing the construction of the
selector 22 used in FIG. 4.
[0022] FIG. 12 is a diagram showing the purge controller 6 in FIG.
4.
[0023] FIG. 13 is a diagram showing the instruction array to be
executed by the processor of FIG. 4.
[0024] FIGS. 14A and 14B are time charts of when the instruction
array shown in FIG. 13 is executed by the processor of the present
invention.
DETAILED DESCRIPTION
[0025] The present invention will be described in detail in
connection with a specific embodiment thereof with reference to the
accompanying drawings.
[0026] In the description to be made, the instructions to be used
in the data processor of the present invention are first described,
and the construction of the processor is then described, finally
followed by the description of the operations.
[0027] A. Instructions
[0028] I. Basic Instruction Format
[0029] FIGS. 2A and 2B show the instruction format of the present
invention. An instruction, which has a length of 32 bits, is
composed of: type of arithmetic operation (bits 15 to 12);
operation words (bits 11 to 0) for designating addressing modes;
and an extension for data for address computations. Depending upon
the addressing mode, the instruction may or may not be accompanied
by the extension. Bits 11 to 9 (Dn) of the operation words indicate
the numbers of data registers which hold data used as one
arithmetic operand. The other operand is designated by bits 5 to 0
of the operation words. More specifically, bits 2 to 0 (Rn)
indicate the numbers of registers to be referred to for~those
operands, whereas bits 5 to 3 (MODES) indicate the addressing
modes.
[0030] The processor of the present invention is equipped with
eight data registers and eight address registers, which will be
described later.
[0031] The correspondence between patterns of bits 5 to 3 and the
addressing modes are shown in FIG. 2B. In this Figure, the "data
register" mode and the "address register" mode are those in which
the contents of the respective data registers and address registers
designated are used as the operands, as they are. The "address
register indirect" mode is one in which the content of the address
register designated is used as the memory address of the operand.
The "post-increment" mode and the "pre-decrement" mode are
basically identical to the address register indirect mode but are
different therefrom in that the contents of these address registers
are incremented by 1 and decremented by 1, respectively,
immediately after and before the operands are stored or fetched. In
these modes, therefore, the operand data stored in a series of
addresses are consecutively read out and computed.
[0032] The "displaced address register indirect" mode is one in
which the value obtained by adding the content of the extension
part to the content of the designated address register is used as
the memory address of the operand, whereas the "displaced program
counter relative" mode is one in which the value obtained by adding
the content of the extension part to the address of the instruction
(or the content of the program counter) is used as the memory
address of the operand. Moreover, the "absolute address" mode is
one in which the content of the extension part is used, as it is,
as the memory address of the operand.
[0033] II. Stack Instructions
[0034] Since the program of the present invention is written in a
high level language, it has a stack as its data structure.
Especially, when a subroutine is used, it is necessary to store, as
different groups, the variables to be used in the main routine and
the variables to be used in the subroutine. These groups are called
frames.
[0035] The stack is composed of a part of the main memory and a
stack pointer. This stack pointer is a register which stores an
address for sequentially storing variables from a lower address in
the main memory.
[0036] When a subroutine is called, the value of the stack pointer
is transferred to a frame pointer. This frame pointer is a register
which stores the highest address of one frame. Of the eight address
registers, in the illustrated embodiment, one is used as the stack
pointer whereas another is used as the frame pointer.
[0037] Access to the stack is executed by designating the frame
pointer or the stack pointer in bits 2 to 0 of the instruction and
by designating any of the "address register indirect",
"post-increment", "pre-decrement" and "displaced address register
indirect" modes as the addressing mode of bits 5 to 3 of the
instruction. All of the modes of the accesses to the stack will be
called a "stack access mode", and those instructions will be called
"stack instructions."
[0038] Since the stack pointer is predetermined in one register in
the present processor, as has been described above, the program
which fails to designate that register as the stack pointer will
not give optimum performance.
[0039] III. Control Instruction
[0040] Moreover, the data processor according to the present
invention has a control instruction which has a format different
from that of the aforementioned general instruction.
[0041] This instruction is a purge instruction, which is issued
exclusively by the data processor itself. Despite this, the purge
instruction may be read out along with the aforementioned basic
instruction from the main memory. The purge instruction has a
function built into the data processor which makes associative
memories 21 and 31, or 36 and 37 of FIG. 4, to be described below,
ineffective.
[0042] The reason why this instruction is present will be described
in the following.
[0043] The data processor 1 of the present invention is formed on a
single chip. External access is effected by generating an address
on that chip. In the present system, however, the address on the
chip and the address actually assigned to an external unit may be
different; and the address in the data processor may be considered
a logical address whereas the address actually assigned to the
external unit may be considered a physical address. Generally, the
transformation between the logical address and the physical address
is accomplished by disposing a special piece of hardware called in
"address transformation device" either in the output part inside of
the chip of the data processor or outside of the same. This is
disclosed on page 145 of the above-specified publication, for
example.
[0044] Since the data processor of the present invention provides
only the logical address on the chip, as will be described
hereinafter, the address of the main memory which is a physical
address and the address of the associative memory on the chip which
is a logical address may be different in the case of a system
having an address transformation device attached to the
outside.
[0045] Especially when switching to address space above that in the
main memory, correspondence between the address of the information
held in the associative memory in the data processor 1 and the
actual address of the main memory cannot be guaranteed.
[0046] The solution to this problem lies in the fact that the data
processor issues a purge instruction in advance to make the
internal associative memory ineffective.
[0047] As a result, when an address transformation device is
disposed in the system, it has to inform the data processor, with a
purge signal, of the fact that the address space has been
switched.
[0048] The data processor of the present invention is designed to
issue a purge instruction in response to a purge signal and a purge
instruction from the address transformation device.
[0049] The description thus far has described the reason for
providing the purge instruction.
[0050] Next, the format of the purge instruction will be described
with reference to FIG. 3A.
[0051] In the purge instruction, the designation of the memory to
have its content made ineffective depends upon a purge code. This
correspondence is shown in FIG. 3B. The memory is not made
ineffective when bits 7 and 6 of the purge code are "00." The
associative memory of the data system is made ineffective when the
purge code is "01000000." An associative memory 21 which will be
described later corresponds to that of the data system.
[0052] The associative memory of the instruction system is made
ineffective when the purge code is "10000000." Associative memories
31, 36, 37 and 38, which will be described later in connection with
FIG. 4, correspond to those of the instruction system.
[0053] All the internal associative memories are made ineffective
when the purge code is "11111111."
[0054] B. Construction of the Processor
[0055] Next, the construction of the processor of the present
invention will be described in detail. Indicated at reference
numeral 1 of FIG. 4 is a data processor which is composed of: an
interface unit 2 for transferring data to and from the main memory
5; an instruction control unit 3 for analyzing the data from the
interface unit. 2; and an instruction execution unit 4 for
executing analytical instruction from the instruction control unit
3.
[0056] Four bytes of data (32 bits) can be read out from the main
memory 5 by a single access.
[0057] The instruction execution unit 4 reads out the data
necessary for the instruction execution through the interface unit
2.
[0058] The instruction control unit 3 and the instruction execution
unit 4 can be operated in parallel so that they are subjected to
pipeline control.
[0059] The respective circuits will be described in the
following.
[0060] I. Instruction Control Unit 3
[0061] The instruction control unit 3 has an instruction controller
300 and the associative memory 31. The instruction controller 300
includes an address generator 32, a control circuit 33 and a
first-in-first-out memory 34. The address generator 32 is a circuit
made receptive to a pre-fetch address renewal signal via a line l34
and a branch address via a line l33 to output a pre-fetch address
and a fetch demand to a line l31 and the address of the instruction
being executed in the instruction execution unit 4 to a line
l32.
[0062] FIG. 5 shows the detail of the address generator 32.
Indicated at numeral 323 is a selector for selecting a pre-fetch
address, normally from a register 321, and a branch address when
the latter is given via a line l332.
[0063] Indicated at numeral 325 is an adder for adding the number
given from a constant generator 324 to the instruction address from
the selector 323. The number generated by the constant generator
324 corresponds to the length of the instruction to be read
out.
[0064] The register 321 latches the output of the adder 325 in
response to a signal from a line l342. As a result, the register
321 is updated each time it receives the signal from the line l34
so that the pre-fetch address is output on a line 12 of the line
l31. The updated signal of the line l34 is output from line l311 of
line l31.
[0065] Indicated at numeral 326 is a selector which normally
selects the output from an adder 329, but which selects the branch
address when this address is applied via the line l332. A register
327 latches an instruction address from the selector 326 to output
it to the line l32.
[0066] The adder 329 adds the number from a constant generator 328
to the instruction address on the line l32. The number to be
generated by the constant generator 328 corresponds to the length
of the instruction to be executed.
[0067] The associative memory 31 of FIG. 4 is for storing the
instruction address and an instruction corresponding to the former
in a common entry.
[0068] The construction of associative memory 31 is shown in FIG.
6. The associative memory 31 is constructed, in its entirety, of 64
entries each of which is composed of a location field 311, a valid
bit 312 and a data field 313.
[0069] The location field 311 is for storing the instruction
address given via line l312. The valid bit is for indicating
whether or not the data stored in the data field 313 are effective.
The data field is for storing the instruction given via line l35 of
FIG. 4 and has a length of 4 bytes (or 32 bits).
[0070] The address of the associative memory 31 is accomplished by
the instruction address given via line l31. If the instruction
address is present and the valid bit is set, the instruction stored
in the data field of the corresponding entry is output to a line
l352. A fetch end signal is also output to a line l351. When the
associative memory 31 is accessed, the signal on line l26 is turned
ON to inhibit access to the main memory by selector 22.
[0071] Updating of the associative memory 31 is effected when there
is no entry stored with the instruction address from the line l31
and when the valid bit is reset. In that case, input read out when
the fetch end signal of the line l351 from the main memory 5 is
turned ON is input via the line l35 and is written together with
the instruction address from the line l31 in the oldest entry. The
valid bit 312 of the newly written entry is set.
[0072] The associative memory 31 is made ineffective by executing
the purge instruction. When this purge instruction is executed, the
valid bit 312 is reset for all the entries by a signal line (not
shown) from the instruction execution unit 4.
[0073] The first-in first-out memory 34 of FIG. 4 stores-a
plurality of instructions given via the line l352 when the fetch
end signal of the line l315 is turned on. With this memory l34,
reading out of the oldest instruction occurs first.
[0074] The control circuit 33 sends out a pre-fetch address renewal
signal to the address generator 32 via the line l34 so as to read
out a subsequent instruction when information that the memory 34 is
vacant is received via the line l330 and when the fetch end signal
of the line l351 is turned off.
[0075] A decoder 35 analyzes the instruction from the memory 34 and
transforms it to the instruction address of the microprogram to
output the same to a line l36.
[0076] Associative memories 36, 37 and 38 are buffers for
suppressing disturbances on pipelines to store the branched
address, the branched instruction and the decoded result in a
common entry.
[0077] The construction of the associative memories 36, 37 and 38
is shown in FIG. 7. These memories are constructed in their
entirety of four entries, each of which is composed of a location
field 361, a valid bit 362 and data fields 363, 377 and 388.
[0078] The location field 361 stores the branched address given via
the line l32. The valid bit field 362 indicates whether the data
stored in the data fields 363, 377 and 388 are effective. A part
363 of the data field stores the subsequent branched instruction
given via a line l38. Another part 388 of the data field stores the
branched instruction itself given via the line l38. Another part
377 of the data field stores the micro instruction address given
via the line l36. In the overall construction view of FIG. 4, the
associative memory 36 is connected between the address generator 32
and the address inputs of associative memories 37 and 38, and the
associative memory 37 is connected between the decoder 35 and the
instruction execution unit 4. This is because the locations of
sources for the variety of information to be stored in the
associative memory 36 are different from those of sources for the
information to be stored in the associative memory 37. Due to the
division of the associative memories 36 and 37, it is possible to
shorten the distances between the information source and the
associative memories and to reduce the area of the chip occupied by
the lines between. The associative memories 36 and 37 are connected
via a line l37, and the address of the entry selected at the
associative memory 36 is given to the associative memories 37 and
38 via the line l37 so that the entry commonly shared between them
is selected.
[0079] The locations to the associative memories 36, 37 and 38 are
selected by the branched address given via the line l32. When the
branched address is present and when the valid bit 362 is set,
items of information stored in the data fields 363, 377 and 388 of
the corresponding entry are output to line l35, l39 and l40,
respectively.
[0080] Reloading of the associative memories 36, 37 and 38 is
conducted when there is no entry stored with the branched address
from the line l32 and when the valid bit 362 is reset. At this
time, the branched address, the decoded result of the branched
instruction, and the branched subsequent instruction are written
together at the location of the oldest previous entry. The valid
bit 362 of the entry newly written is set.
[0081] The associative memories 36, 37 and 38 are made ineffective
when the purge instruction is executed. When this purge instruction
is executed, the valid bit 362 is reset for all the entries by the
signal line (not shown) from the instruction execution unit 4.
[0082] A selector 47 of FIG. 4 selects line l39 when it receives a
branch success signal given via line l45. The selector 47 selects
line l36 when it receives branch failure signal.
[0083] A selector 46 selects line l38 when it receives the branch
success given via line l45. The selector 46 selects line l40 when
it receives a branch failure signal.
[0084] A register 380 latches the micro instruction address from
the decoder 35 or associative memory 37 coupled through selector 47
in response to a subsequent instruction demand signal given via
line l41. The register 380 also sends out the latched micro
instruction address to the instruction execution unit. However, the
register 380 latches the purge instruction via line l63 rather than
the micro instruction address from the selector 47 when it is given
the purge instruction signal of a subsequent instruction demand
signal of line l41 via line l62.
[0085] Register 40 latches the signal from the selector 46 when
receives the subsequent instruction demand signal via line l41.
[0086] II. Instruction Execution Unit 4
[0087] The instruction execution unit 4 has an instruction executor
400 and an associative memory 21. The instruction executor 400
includes a ROM 41 and a processor 45. The ROM 41 sequentially takes
as the addresses a series of respective micro instructions, which
are given via line l381 and arrayed on a time axis, to sequentially
read out the control information stored at the corresponding
addresses and to output it to line l42.
[0088] The processor 45 performs arithmethic operations on the
basis of the control information on the line l42. The processor 45
outputs the address for obtaining the operand data from the main
memory via line l33 and outputs the operand data read out via line
l43. The processor 45 also inputs the instruction itself via line
l44. The subsequent instruction demand signal is output to line l41
when the instruction execution ends. When a branch instruction is
executed, moreover, the branch success signal is output to line l45
if the branch succeeds, whereas the branch failure signal is output
if the branch fails.
[0089] FIG. 8 is a diagram showing the construction of the
processor 55. Lines l46, l47 and l48 are internal data buses. A
group of registers 452 is composed of eight data registers and
eight address registers. One or two registers from the group 452
are designated by a line l422 to read out the data to the buses l46
and l47 or to read in the data from the bus l48.
[0090] The eight address registers contain a stack pointer and a
frame pointer. The stack pointer is decremented by 1 each time it
is used for storing data in the main memory and incremented by 1
each time it is used for reading out those data.
[0091] Indicated at numeral 453 is an arithmetic circuit for adding
or subtracting the signals on the buses l46 and l47 in accordance
with the instruction from a line l423 to output the computed result
to the internal data bus l48. The arithmetic circuit 453 also
outputs the subsequent instruction demand signal to the line l41
after all the control information for one instruction has been
input from line l42 and after the end of the computation.
[0092] Moreover, the arithmetic circuit 453 refers to a condition
code C.C, when a branch instruction is executed, to output the
branch success signal to line l45, when the condition specified by
the branch instruction has been satisfied, and the branch failure
signal when that condition is not satisfied.
[0093] When the purge instruction is executed, a purge clear signal
is first output to a line l49 to reset the valid bit of the
associative memory expressed by the purge code via the signal line
(not shown).
[0094] Indicated at numeral 454 is a data designator for
establishing the lower two bits of the address on line l33 on the
basis of the operand size indicated on line l424, in which 1, 2 or
4 bytes are designated by the instruction, when a post-increment
mode and a pre-decrement mode is executed. It does this by
providing interface 451 a signal via a line l50 to utilize those of
the 32-bit data on the line l43, which are necessary as the operand
and which have the length of the operand size.
[0095] The interface 451 outputs data from the line l432 in
accordance with the control information on the line l421, when the
fetch end signal of a line l431 is turned on, to turn off the fetch
demand signal on the line l431. The interface 451 also outputs the
data from the internal data buses l47 and l48 to the line l432 and
the fetch demand signal to the line l431. When the bit location and
the length of the data to be read out are designated on the line
l50, the interface 451 cuts out the data on the basis of the
designation.
[0096] Returning to FIG. 4, the associative memory 21 is composed
of an operand buffer 24 for storing the operand data, and a line
buffer 25 for storing the byte data.
[0097] The arrangement of the operand buffer 24 is shown in FIG. 9.
The operand buffer 24 contains in its entirety 22 entries, each of
which is composed of a location field 241, a valid bit 242 and a
data field 243. The location field is for storing the addresses of
the operand data given via the line l33. The valid bit 242 is for
indicating whether or not the operand data stored in the data field
are effective. The data field 243 is for storing the operand data
given via line l21.
[0098] The updating and selection of the operand buffer 24
are-subjected to the following two kinds of controls on the basis
of the instructions to be executed in the instruction execution
unit 4.
[0099] 1. In the stack access mode and when the content of the
address register designated by the instruction is output as the
address of the operand data line l332, the operand buffer 24 is
located by said operand data address. When the operand data address
is present and when the valid bit 242 is set, the operand data
stored in the data field of the corresponding entry are output to
the line l432. At this time, the fetch end signal of the line l431
is turned on. If the associative memory 24 is accessed, moreover,
the access to main memory 5 is inhibited by the selector 22 via a
line l25. If the operand buffer 24 does not contain the operand
data address, the operand data read out from the main memory 5 are
input via line l21 and are written together with the operand
address from line l33 in the oldest previous entry. The effective
bit 242 of the newly written entry is set.
[0100] 2. When the instruction execution result is obtained so that
it is output to line l43 along with the address of the main memory
5 where the execution result is output is to be stored, the operand
buffer 24 is selected by that address. In case this address is
present and when the valid but 242 is set, the data of the data
field in the corresponding entry are rewritten to the execution
result on line l332. The valid bit 242 is set. Even if the
associative memory is accessed at this time, no output is produced
on the line l25. As a result, the selector 22 is not inhibited from
accessing the main memory 5. If the operand buffer 24 does not
contain the address, the data of the operand buffer 24 are not
rewritten.
[0101] In cases other than the above-specified 1 and 2, the data in
the operand buffer are not rewritten.
[0102] Example 1 is one which corresponds to the updating of the
stack and the data read-out from the stack. Since, in example 2, an
update and rewrite of the operand buffer are effected, the operand
buffer can be said to be an internal memory for storing the stack
data.
[0103] Since, in example 2, the stack may be subjected to direct
address designation for rewriting the data, example 2 is processing
for this.
[0104] The operand buffer 24 is made ineffective by the purge
signal. The resetting is conducted for all the valid bits 242 when
the purge signal is input.
[0105] The line buffer 25 of associative memory 21 is a memory for
holding the 4 bytes of the sequential addresses, which all are read
out together from the main memory 5 when the byte data of a length
designated by the operand size is read out in the post-increment
mode and in the pre-decrement mode, to speed up the access to the
sequential operand addresses in the subsequent instructions.
[0106] The arrangement of the line buffer 25 is shown in FIG. 10.
The line buffer 25 has entries which correspond one to one to those
six registers of the eight address registers of FIG. 8, other than
the stack pointer and the frame pointer. Thus, the line buffer is
constructed of six entries as a whole.
[0107] Each entry is composed of a location field 251, four valid
bits 252 to 255, and four data fields 256 to 259. The valid bits
252 to 255 correspond to the data fields 256 to 259, respectively,
and indicate whether or not the data of the corresponding data
fields are effective. The four data fields of one entry are
respectively stored with the data of 4 bytes of the sequential
addresses read out all at once from the main memory 5.
[0108] The addresses of the line buffer 25 are selected in the
post-increment mode and the pre-decrement mode of the address
indirect modes.
[0109] The post-increment and pre-decrement modes are those in
which the address register is incremented or decremented by 1 to
sequentially read out the data stored in the sequential
addresses.
[0110] When the first data are to be read out in this mode, it is
usual that no corresponding entry is present even if the line
buffer is selected. As a result, the address is sent out from
processor 45 of FIG. 4 to the main memory via the line l33. At this
time, 4 bytes of data are all read out together from the main
memory 5 and are written in the entry corresponding to the address
register designated by the instruction via the line l21.
Simultaneously with this, the data are output from the selector 22
to the line l43.
[0111] At this time, the 32 bits of data are sent to the line l43,
but the data necessary for the operand are those of such a number
of bytes as is designated by the operand size. This data cutting is
conducted by the aforementioned data designator 454 and interface
451 of FIG. 8.
[0112] When the first data processing is finished, the content of
the address register designated by the instruction is incremented
or decremented by 1, and the subsequent data are read out. Since,
at this time, the address output to line l33 is the one succeeding
the address output previously, the possibility of this address
corresponding to the address in the data stored beforehand in the
line buffer 25 is remarkably high. When a line buffer access
results from this address, the data are not read out from the main
memory 5, but the 4 bytes of data in the corresponding entry are
output to line l43. Moreover, an output is fed to line l25 to
inhibit access to the main memory 5 by the selector 22.
[0113] When the instruction execution result is obtained in the
instruction execution unit 4 and output to line l43 so that the
address of the main memory 5 to store said execution result is
output to line l33, the line buffer 25 is selected by that address.
If this address is present in line buffer 25, and its associated
valid bit is set, the data of the data field in the corresponding
entry are replaced with the execution result on line l33. The valid
bit is set. Even if line buffer 25 is accessed at this time, no
output is produced on the line 25. As a result, the selector 22 is
not inhibited from accessing the main memory 5. If the line buffer
25 does not contain this address, the data are not rewritten in the
line buffer 25. This operation is processing similar to that of the
operand buffer for making the content of the line buffer coincident
with that of the main memory 5.
[0114] By using the line buffer 25, as above, in the post-increment
and pre-decrement modes, the access to the main memory may be
conducted once for four bytes on an average so that a fast read-out
can be conducted, especially in a case where the operand size is
sufficient for processing of four sets of operand data.
[0115] III. Interface Unit 2
[0116] The interface unit 2 includes a selector 22. The selector 22
sends out either the instruction address given via line l31 or the
operand data address given via line l33 to the main memory 5 via
line l23.
[0117] FIG. 11 is a diagram showing the construction of the
selector 22. Line l311 corresponds to the read demand signal
whereas line l312 corresponds to the address signal, and these two
lines combined make up the line l31. Line l331 carries a fetch
demand signal whereas line l332 carries the address signal, and
these together make up the line l33. An AND circuit 222 determines
the logical product of the signals on the lines l311 and l26 to
output a signal to inhibit access to the main memory 5 from the
instruction control unit 3 when the associative memory 31 is
accessed. An AND circuit 226 determines the logical product of the
signals on the lines l331 and l25 to output a signal for inhibiting
access to the main memory 5 from the instruction execution unit 4
when the associative memory 21 is accessed.
[0118] AND circuits 223 and 227 are for making the access demand
from the instruction execution-unit 4 predominant. Either a
flip-flop 224 or 228 is set by a respective AND circuit 323 or 227.
A selector circuit 221 outputs one address signal, selected by an
output from the flip-flop 224 or the flip-flop 228 to line
l232.
[0119] An OR circuit 230 determines the logical sum of the outputs
of the flip-flops 224 and 228 to output a fetch demand signal to
line l231. This line l231, together with line l232 makes up line
l23.
[0120] The data from the main memory 5 are obtained via a line l24.
Line l241 produces a fetch (or read) end signal to announce that
the data have been prepared. The data themselves are input to line
l242.
[0121] AND circuits 225 and 229 judge which of the instruction
control unit 3 and the instruction execution unit 4 has produced a
fetch demand to line l231 to inform line l351 or l211, having sent
the demand of the fact that the data are prepared by the fetch end
signal. The instruction control unit 3 and the instruction
execution unit 4 examines line l351 in line l35 and line l211 in
line l21 to determine whether response has been made to the fetch
demand, thereby to turn off the fetch demand. The interface unit 2
also includes transformation device 222 for transforming logical
addresses to physical addresses for use in main memory 5.
[0122] IV. Purge Controller 6
[0123] When the purge signal is input from line l61, the purge
controller 6 outputs the purge instruction signal to line l62 and
the purge instruction to line l63.
[0124] The construction of the purge controller 6 is shown in FIG.
12.
[0125] When the purge signal is input from line l61, the D terminal
of a flip-flop 65 is raised to a high level through an AND circuit
64. When a subsequent instruction demand signal is input through
line l41, the input of the D terminal is latched at that time to
turn on the purge instruction signal of line l62. As a result, the
content of a register 66 stored in advance with the purge
instruction via line l64 is latched in the register 380, as shown
in FIG. 4, via line l63. At this time, moreover, a flip-flop 62 is
set. When the purge instruction is executed at the instruction
execution unit 4, the purge clear signal is first output to line
49. As a result, the flip-flop 62 is reset. The D input of the
flip-flop 65 is set at a low level through a delay circuit 63 and
the AND circuit 64. When the execution of the purge instruction is
ended, the subsequent instruction demand signal of line l41 is
turned on. As a result, the flip-flop 62 is set, and the flip-flop
65 is reset. The output of the flip-flop 62 is the input to the
delay circuit 63. During this time, the register 380 latches the
instructions decoded result from the selector 47. After this, the
output from the delay circuit 63 goes high. While line 161 outputs
the purge signal, the D input of the flip-flop 65 is high. As a
result, when the subsequent instruction demand signal is input, the
purge instruction signal is output again to line l62.
[0126] An address transformer (not shown) can be connected with
lines l61 and l63.
[0127] The address transformer is used, as has been described
hereinbefore, in the system in which the address to be used in the
data processor and the address to be given to the system other than
the data processor are different.
[0128] Incidentally, in the illustrated embodiment, the purge
instruction can be latched alternately in register 380. This is
because the usual instruction is executed step by step by the data
processor to check the program.
[0129] C. Operation
[0130] Next, the operations of the data processor of the present
invention will be described in the following.
[0131] FIG. 13 shows one example of the instruction array to be
executed in the data processor of the present invention.
[0132] The instructions are stored from No. 1 to No. 11 in
sequential addresses in the main memory.
[0133] Instructions Nos. 1 and 2 store the data of addresses
indicated by the stack pointer in the data registers designated by
the respective instructions.
[0134] Instruction No. 3 adds the contents of the respective
registers stored with the data in accordance with instructions Nos.
1 and 2 and stores the result in either of the data registers.
[0135] Instruction No. 4 stores the content of the data register
designated by the instruction in the address indicated by the
address register designated by the instruction.
[0136] Instruction No. 5 jumps to the instruction of the address
indicated by the address register designated by the instruction. In
the case of the present example, the jump to instruction No. 10 is
conducted.
[0137] Instruction No. 10 adds the contents of the two data
registers designated by the instruction.
[0138] The time chart of when the aforementioned instruction array
is executed is shown in FIG. 14A.
[0139] I. Cycle T.sub.1
[0140] The address generator 32 outputs the address of the
instruction No. 1 to line l31. The associative memory 31 is
selected by this address-and the address generator 32 reads the
data from the main memory 5 when an attempt to access the
associative memory 31 fails. The data read out from the main memory
5 are stored not only in the associative memory 31 but also in the
memory 34.
[0141] II. Cycle T.sub.2
[0142] Since the memory 34 is vacant, the address generator 32
outputs the address of instruction No. 2. The associative memory 31
is selected by this address as with the previous instruction No. 1
and the address generator 32 writes the data from the main memory 5
when an attempt to access the associative memory 31 fails.
Moreover, the read data are stored in the memory 34.
[0143] The decoder 35 analyzes instruction No. 1 from the memory 34
to store the analyzed result in register 380.
[0144] The micro instruction array of instruction No. 1 stored in
register 380 begins execution in the instruction execution unit
4.
[0145] Upon execution, the addresses of the operand data for
storage in the data register are output to line l33. However, since
this instruction is a stack instruction, there is a strong
possiblity that the corresponding entry is present in associative
memory 21. As a result, there is little conflict between the read
demand of instruction No. 2 from the instruction control unit 3 and
the read demand of the operand data from the instruction executing
unit 4.
[0146] If instruction No. 2 is present in the associative memory
31, the read demands of instruction control unit 3 and instruction
execution unit 4 from the main memory 5 do not conflict despite the
fact that the operand data are present in associative memory
21.
[0147] III. Cycle T.sub.3
[0148] Instruction No. 3 is read out from the main memory 5 like
the instructions Nos. 1 and 2 and is stored in the memory 34. In
the decoder 35; the analysis of instruction No. 2 is conducted.
[0149] In instruction execution unit 4, the execution of
instruction No. 1 is ended, and the execution of instruction No. 2
is started.
[0150] Instruction No. 2 is a stack instruction like No. 1 to
effect the location of the associative memory 21 thereby to read
out the operand data from main memory 5 if the address is not
present in the associative memory. The conflict between instruction
control unit 3 and instruction execution unit 4 in this case is
similar to that for instruction No. 1.
[0151] IV. Cycle T.sub.1
[0152] Like instruction No. 1, instruction No. 4 is read out from
the main memory 5 and is stored in the memory 34. In the decoder
35, the analysis of the instruction No. 3 is conducted. In
instruction execution unit 4, the execution of instruction No. 2 is
ended, and the execution of instruction No. 3 is started. Since
instruction No. 3 performs arithmetic operations using the data
register in instruction execution unit 4, operand data are not read
out from the main memory 5.
[0153] V. Cycle T.sub.5
[0154] Instruction No. 5 is read out like instruction No. 1 from
the main memory 5 and is stored in the memory 34. In the decoder
35, the analysis of instruction No. 4 is conducted. In instruction
execution unit 4, the execution of instruction No. 3 is ended, and
the execution of instruction No. 4 is started. Instruction No. 4 is
for writing the data of the data register in the main memory. The
destination address at which the data are to be written is output
to line l33. When the operand buffer 24 checks to determine whether
the present address rewrites the content of the stack and finds
that the content is to be rewritten, its content is rewritten to
the data on the line
[0155] The data on the line 143 are set out to the main memory
5.
[0156] VI. Cycle T.sub.6
[0157] Instruction No. 6 is read out from the main memory 5 like
instruction No. 1 and is stored in the memory 34. In the decoder
35, the analysis of the instruction No. 5 is conducted. The address
generator 36 outputs to line l32 the address of instruction No. 5
being executed by the instruction execution unit. Associative
memory 36 is selected by this address. When no corresponding entry
is present, no output is produced from associative memories 37 and
38. When the corresponding entry is present, the timing follows
Cycles 10 and later, as will be described hereinafter. In the
instruction execution unit 4, the execution of instruction No. 4 is
ended, and the execution of the instruction No. 5 is started.
[0158] VII. Cycle T.sub.7
[0159] Instruction No. 7 is read out from the main memory 5 like
instruction No. 1 and is stored in memory 34. In the decoder 35,
the analysis of instruction No. 6 is conducted. In instruction
execution unit 4, the execution of the instruction No. 5 is ended,
and the address of the instruction No. 10 to be subsequently
executed is output to line l33. Since the branch has succeeded,
moreover, instruction execution unit 4 clears the content of memory
34.
[0160] VIII. Cycle T.sub.8
[0161] Address generator 32 takes the address of instruction No. 10
on line l33 and outputs it to line l31. Instruction No. 10 is
stored in memory like instruction No. 1. In the decoder 35, no
operation is conducted because the content of memory 34 has been
cleared at the Cycle T.sub.7. Nor is operation conducted in
instruction execution unit 4, because the instruction to be
executed has not been decoded. Instruction No. 10 itself is stored
in associative memory 38.
[0162] IX. Cycle T.sub.9
[0163] Instruction No. 11 is read out from main memory 5 like
instruction No. 1 and: is stored in memory 34. In the decoder 35,
the analysis of instruction No. 10 is conducted. The analyzed
result is stored in associative memory 37. Moreover, instruction
No. 11 itself is stored in associative memory 36. At this time, the
address of instruction No. 5 which has been executed last in
instruction execution unit 4 is stored in associative memory 36. As
a result, the common entry is stored with the branched address, the
branched instruction, the branched instruction analyzed result, and
the branched subsequent instruction. In instruction execution unit
4, the execution of the instruction No. 10 is conducted after the
end of its analysis.
[0164] X. Cycle T.sub.7
[0165] If an entry corresponding to the associative memory 36 is
present at Cycle T.sub.6, as shown in FIG. 14B, the instruction per
se is instantly read out from associative memories 37 and 38 as an
analyzed result from instruction No. 10. From associative memory
36, moreover, instruction No. 11 is also read out and is stored in
memory 34. At Cycle T.sub.7, address generator 32 adds the length
of instructions Nos. 10 and 11 to the address of instruction No. 10
given via line l33 to prepare the address of instruction No. 12 and
output the same to line l31. Instruction No. 12 thus read out is
stored in memory 34. In the decoder 35, the analysis of instruction
No. 11 is conducted. Instruction execution unit 4 executes
instruction No. 10 read out from the associative memories 37 and 38
immediately after the end of execution of the instruction No.
5.
[0166] As has been already described, according to the present
invention, even if the instruction control unit and the instruction
execution unit operate in parallel, a conflict in reading out data
from the main memory is unlikely to occur, so that instruction
processing can be speeded up.
* * * * *