| Patent | Date |
|---|
Information storage system, information transfer system and storage medium thereof
Grant 7,100,055 - Owada , et al. August 29, 2 | 2006-08-29 |
Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system
Grant 6,810,454 - Kondo , et al. October 26, 2 | 2004-10-26 |
Data processing system having a card type interface with assigned addressing
Grant 6,792,493 - Matsui , et al. September 14, 2 | 2004-09-14 |
Data processor
App 20040177231 - Nishimukai, Tadahiko ; et al. | 2004-09-09 |
Data processor capable of executing an instruction that makes a cache memory ineffective
Grant 6,779,102 - Nishimukai , et al. August 17, 2 | 2004-08-17 |
Semiconductor device
Grant 6,708,304 - Tsukimori , et al. March 16, 2 | 2004-03-16 |
Information processing apparatus
Grant 6,665,807 - Kondo , et al. December 16, 2 | 2003-12-16 |
Data processing system having a card type interface with assigned addressing
App 20030163624 - Matsui, Shigezumi ; et al. | 2003-08-28 |
Data Processing System Having An External Device Interface With Assigned Addressing
App 20030149821 - Matsui, Shigezumi ; et al. | 2003-08-07 |
Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system
App 20030101299 - Kondo, Nobukazu ; et al. | 2003-05-29 |
Accessing exception handlers without translating the address
Grant 6,425,039 - Yoshioka , et al. July 23, 2 | 2002-07-23 |
Data Processor
App 20020002669 - YOSHIOKA, SHINICHI ; et al. | 2002-01-03 |
Data processor
App 20010032296 - Nishimukai, Tadahiko ; et al. | 2001-10-18 |
Microprocessor having a PC card type interface
Grant 6,049,844 - Matsui , et al. April 11, 2 | 2000-04-11 |
Data processor for implementing virtual pages using a cache and register
Grant 6,047,354 - Yoshioka , et al. April 4, 2 | 2000-04-04 |
Single-chip data processor handling synchronous and asynchronous exceptions by branching from a first exception handler to a second exception handler
Grant 6,038,661 - Yoshioka , et al. March 14, 2 | 2000-03-14 |
Translation lookaside buffer supporting multiple page sizes
Grant 5,907,867 - Shinbo , et al. May 25, 1 | 1999-05-25 |
Microprocessor having PC card interface
Grant 5,848,247 - Matsui , et al. December 8, 1 | 1998-12-08 |
Processor with an addressable address translation buffer operative in associative and non-associative modes
Grant 5,835,963 - Yoshioka , et al. November 10, 1 | 1998-11-10 |
Purge control for ON-chip cache memory
Grant 5,809,274 - Nishimukai , et al. September 15, 1 | 1998-09-15 |
Data processor having an address translation buffer operable with variable page sizes
Grant 5,796,978 - Yoshioka , et al. August 18, 1 | 1998-08-18 |
Data processor and single-chip microcomputer with changing clock frequency and operating voltage
Grant 5,778,237 - Yamamoto , et al. July 7, 1 | 1998-07-07 |
Microprocessor operating at high and low clok frequencies
Grant 5,774,701 - Matsui , et al. June 30, 1 | 1998-06-30 |
Microprocessor for inserting a bus cycle in an instruction set to output an internal information for an emulation
Grant 5,564,041 - Matsui , et al. October 8, 1 | 1996-10-08 |
Microprocessor having apparatus for dynamically controlling a kind of operation to be performed by instructions to be executed
Grant 5,398,319 - Sakamura , et al. March 14, 1 | 1995-03-14 |
Data processor having logical address memories and purge capabilities
Grant 5,349,672 - Nishimukai , et al. September 20, 1 | 1994-09-20 |
System for logical address conversion data fetching from external storage and indication signal for indicating the information externally
Grant 5,278,962 - Masuda , et al. * January 11, 1 | 1994-01-11 |
Data processing system having apparatus for increasing the execution speed of bit field instructions
Grant 5,210,835 - Sakamura , et al. * May 11, 1 | 1993-05-11 |
Microprocessor system
Grant 5,193,159 - Hashimoto , et al. March 9, 1 | 1993-03-09 |
Data processing system
Grant 5,187,782 - Kawasaki , et al. * February 16, 1 | 1993-02-16 |
System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus
Grant 5,125,095 - Nakazawa , et al. June 23, 1 | 1992-06-23 |
Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit
Grant 4,989,140 - Nishimukai , et al. January 29, 1 | 1991-01-29 |
Software debugging system for writing a logical address conversion data into a trace memory of an emulator
Grant 4,954,942 - Masuda , et al. September 4, 1 | 1990-09-04 |
Data processing system having apparatus for increasing the execution speed of bit field instructions
Grant 4,941,085 - Sakamura , et al. July 10, 1 | 1990-07-10 |
Data processing system
Grant 4,897,787 - Kawasaki , et al. January 30, 1 | 1990-01-30 |
Data processing system with coprocessor
Grant 4,894,768 - Iwasaki , et al. January 16, 1 | 1990-01-16 |
Microprocessor for retrying data transfer
Grant 4,845,614 - Hanawa , et al. July 4, 1 | 1989-07-04 |
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