Uchiyama; Kunio

Patent Applications and Registrations

Patent applications and USPTO patent grants for Uchiyama; Kunio.The latest application filed is for "processor system using synchronous dynamic memory".

Company Profile

0.50.28

Uchiyama; Kunio - Tokyo N/A JP
Uchiyama; Kunio - Kodaira JP
UCHIYAMA; Kunio - Kodaira-shi JP
Uchiyama; Kunio - Hachioji JP
Uchiyama; Kunio - Kokubunji JP
Uchiyama; Kunio - Pittsburgh PA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Substrate bias switching unit for a low power processor Grant 8,364,988 - Totsuka , et al. January 29, 2	2013-01-29
Processor system using synchronous dynamic memory Grant 8,234,441 - Uchiyama , et al. July 31, 2	2012-07-31
Processor System Using Synchronous Dynamic Memory App 20110314213 - UCHIYAMA; Kunio ; et al.	2011-12-22
Substrate Bias Switching Unit For A Low Power Processor App 20110208983 - TOTSUKA; Yonetaro ; et al.	2011-08-25
Substrate bias switching unit for a low power processor Grant 7,958,379 - Totsuka , et al. June 7, 2	2011-06-07
Processor system using synchronous dynamic memory Grant 7,904,641 - Uchiyama , et al. March 8, 2	2011-03-08
Semiconductor integrated circuit device having power reduction mechanism Grant 7,750,668 - Horiguchi , et al. July 6, 2	2010-07-06
Substrate Bias Switching Unit For A Low Power Processor App 20100005324 - TOTSUKA; Yonetaro ; et al.	2010-01-07
Substrate bias switching unit for a low power processor Grant 7,475,261 - Totsuka , et al. January 6, 2	2009-01-06
Processor System Using Synchronous Dynamic Memory App 20080229004 - UCHIYAMA; Kunio ; et al.	2008-09-18
Processor system using synchronous dynamic memory Grant 7,376,783 - Uchiyama , et al. May 20, 2	2008-05-20
Semiconductor integrated circuit device having power reduction mechanism App 20080072085 - Horiguchi; Masashi ; et al.	2008-03-20
Semiconductor device App 20080016383 - Watanabe; Takao ; et al.	2008-01-17
Semiconductor integrated circuit device having power reduction mechanism Grant 7,312,640 - Horiguchi , et al. December 25, 2	2007-12-25
Semiconductor device Grant 7,254,082 - Watanabe , et al. August 7, 2	2007-08-07
Processor system using synchronous dynamic memory App 20070061537 - Uchiyama; Kunio ; et al.	2007-03-15
Floating point unit pipeline synchronized with processor pipeline Grant 7,162,616 - Biswas , et al. January 9, 2	2007-01-09
Processor system using synchronous dynamic memory Grant 7,143,230 - Uchiyama , et al. November 28, 2	2006-11-28
Semiconductor device App 20060146635 - Watanabe; Takao ; et al.	2006-07-06
Semiconductor device Grant 7,023,757 - Watanabe , et al. April 4, 2	2006-04-04
Semiconductor integrated circuit device having power reduction mechanism Grant 6,970,019 - Horiguchi , et al. November 29, 2	2005-11-29
Semiconductor integrated circuit device having power reduction mechanism App 20050213414 - Horiguchi, Masashi ; et al.	2005-09-29
Semiconductor integrated circuit device Grant 6,879,188 - Miyazaki , et al. April 12, 2	2005-04-12
Semiconductor integrated circuit and method for manufacturing the same App 20040191991 - Ikeda, Shuji ; et al.	2004-09-30
Data processor App 20040177231 - Nishimukai, Tadahiko ; et al.	2004-09-09
Floating point unit pipeline synchronized with processor pipeline App 20040172522 - Biswas, Prasenjit ; et al.	2004-09-02
Data processor capable of executing an instruction that makes a cache memory ineffective Grant 6,779,102 - Nishimukai , et al. August 17, 2	2004-08-17
Low power processor App 20040158756 - Totsuka, Yonetaro ; et al.	2004-08-12
Floating point unit pipeline synchronized with processor pipeline Grant 6,772,327 - Biswas , et al. August 3, 2	2004-08-03
Processor system using synchronous dynamic memory App 20040143700 - Uchiyama, Kunio ; et al.	2004-07-22
Semiconductor integrated circuit and method for manufacturing the same Grant 6,753,231 - Ikeda , et al. June 22, 2	2004-06-22
Semiconductor integrated circuit device having power reduction mechanism App 20040070425 - Horiguchi, Masashi ; et al.	2004-04-15
Processor for controlling substrate biases in accordance to the operation modes of the processor Grant 6,715,090 - Totsuka , et al. March 30, 2	2004-03-30
Semiconductor integrated circuit device having power reduction mechanism Grant 6,696,865 - Horiguchi , et al. February 24, 2	2004-02-24
Processor system using synchronous dynamic memory Grant 6,697,908 - Uchiyama , et al. February 24, 2	2004-02-24
Semiconductor device App 20030231526 - Watanabe, Takao ; et al.	2003-12-18
Semiconductor integrated circuit and method for manufacturing the same App 20030153147 - Ikeda, Shuji ; et al.	2003-08-14
Semiconductor integrated circuit device Grant 6,601,218 - Sato , et al. July 29, 2	2003-07-29
Semiconductor integrated circuit device App 20030098730 - Miyazaki, Masayuki ; et al.	2003-05-29
Semiconductor integrated circuit device having power reduction mechanism App 20030058002 - Horiguchi, Masashi ; et al.	2003-03-27
Semiconductor integrated circuit and design method and manufacturing method of the same Grant 6,532,579 - Sato , et al. March 11, 2	2003-03-11
Semiconductor integrated circuit device Grant 6,515,519 - Miyazaki , et al. February 4, 2	2003-02-04
Floating point unit pipeline synchronized with processor pipeline App 20020174323 - Biswas, Prasenjit ; et al.	2002-11-21
Semiconductor integrated circuit and method for manufacturing the same App 20020155657 - Ikeda, Shuji ; et al.	2002-10-24
Semiconductor integrated circuit device having power reduction mechanism App 20020084804 - Horiguchi, Masashi ; et al.	2002-07-04
Processor system using synchronous dynamic memory App 20020029317 - Uchiyama, Kunio ; et al.	2002-03-07
Semiconductor integrated circuit and design method and manufacturing method of the same App 20010044918 - Sato, Masayuki ; et al.	2001-11-22
Data processor App 20010032296 - Nishimukai, Tadahiko ; et al.	2001-10-18
Semiconductor integrated circuit device App 20010022743 - Sato, Masayuki ; et al.	2001-09-20
Semiconductor integrated circuit device App 20010021558 - Sato, Masayuki ; et al.	2001-09-13
Semiconductor integrated circuit device having power reduction mechanism App 20010004218 - Horiguchi, Masashi ; et al.	2001-06-21
Data processor and data processing system having two translation lookaside buffers Grant 6,092,172 - Nishimoto , et al. July 18, 2	2000-07-18
Semiconductor integrated circuit device having power reduction mechanism Grant 6,046,604 - Horiguchi , et al. April 4, 2	2000-04-04
Semiconductor integrated circuit device having power reduction mechanism Grant 5,880,604 - Kawahara , et al. March 9, 1	1999-03-09
Floating point unit pipeline synchronized with processor pipeline Grant 5,860,000 - Biswas , et al. January 12, 1	1999-01-12
Semiconductor integrated circuit device having power reduction mechanism Grant 5,828,235 - Horiguchi , et al. October 27, 1	1998-10-27
Purge control for ON-chip cache memory Grant 5,809,274 - Nishimukai , et al. September 15, 1	1998-09-15
Semiconductor integrated circuit device having power reduction mechanism Grant 5,614,847 - Kawahara , et al. March 25, 1	1997-03-25
Semiconductor integrated circuit device having power reduction mechanism Grant 5,583,457 - Horiguchi , et al. December 10, 1	1996-12-10
Processor system using synchronous dynamic memory Grant 5,574,876 - Uchiyama , et al. November 12, 1	1996-11-12
Microprocessor capable of decoding two instructions in parallel Grant 5,408,625 - Narita , et al. April 18, 1	1995-04-18
Semiconductor memory device for performing parallel operations on hierarchical data lines Grant 5,386,394 - Kawahara , et al. January 31, 1	1995-01-31
Data processor having logical address memories and purge capabilities Grant 5,349,672 - Nishimukai , et al. September 20, 1	1994-09-20
Data processor having two instruction registers connected in cascade and two instruction decoders Grant 5,301,285 - Hanawa , et al. April 5, 1	1994-04-05
Multi-processor system for invalidating hierarchical cache Grant 5,287,484 - Nishii , et al. February 15, 1	1994-02-15
Multiprocessor cache system having three states for generating invalidating signals upon write accesses Grant 5,283,886 - Nishii , et al. February 1, 1	1994-02-01
Static memory containing sense amp and sense amp switching circuit Grant 5,267,198 - Hatano , et al. November 30, 1	1993-11-30
Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively Grant 5,202,969 - Sato , et al. April 13, 1	1993-04-13
Static memory containing sense AMP and sense AMP switching circuit Grant 5,193,075 - Hatano , et al. March 9, 1	1993-03-09
Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register Grant 5,146,573 - Sato , et al. September 8, 1	1992-09-08
Multi-processing system and cache apparatus for use in the same Grant 5,140,681 - Uchiyama , et al. August 18, 1	1992-08-18
Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit Grant 4,989,140 - Nishimukai , et al. January 29, 1	1991-01-29
Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction Grant 4,937,738 - Uchiyama , et al. June 26, 1	1990-06-26
System for reexecuting branch instruction without fetching by storing target instruction control information Grant 4,912,635 - Nishimukai , et al. March 27, 1	1990-03-27
Virtual memory supported processor having restoration circuit for register recovering Grant 4,797,816 - Uchiyama , et al. January 10, 1	1989-01-10
Microprocessor capable of stopping its operation at any cycle time Grant 4,720,811 - Yamaguchi , et al. January 19, 1	1988-01-19
Content addressable memory having dual access modes Grant 4,646,271 - Uchiyama , et al. February 24, 1	1987-02-24