U.S. patent application number 10/357579 was filed with the patent office on 2004-08-05 for bi-level resist structure and fabrication method for contact holes on semiconductor substrates.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Company. Invention is credited to Hsu, Ju Wang, Tao, Hun-Jan, Tsai, Ming-Huan, Wu, Tsang Jiuh.
Application Number | 20040152328 10/357579 |
Document ID | / |
Family ID | 32771022 |
Filed Date | 2004-08-05 |
United States Patent
Application |
20040152328 |
Kind Code |
A1 |
Tsai, Ming-Huan ; et
al. |
August 5, 2004 |
BI-LEVEL RESIST STRUCTURE AND FABRICATION METHOD FOR CONTACT HOLES
ON SEMICONDUCTOR SUBSTRATES
Abstract
An improved method of etching very small contact holes through
dielectric layers used to separate conducting layers in multilevel
integrated circuits formed on semiconductor substrates has been
developed. The method uses bi-level ARC coatings in the resist
structure and a unique combination of gaseous components in a
plasma etching process which is used to dry develop the bi-level
resist mask as well as etch through a silicon oxide dielectric
layer. The gaseous components comprise a mixture of a fluorine
containing gas, such as C.sub.4F.sub.8, C.sub.5F.sub.8,
C.sub.4F.sub.6, CHF.sub.3 or similar species, an inert gas, such as
helium or argon, an optional weak oxidant, such as CO or O.sub.2 or
similar species, and a nitrogen source, such as N.sub.2, N.sub.2O,
or NH.sub.3or similar species. The patterned masking layer can be
used to reliably etch contact holes in silicon oxide layers on
semiconductor substrates, where the holes have diameters of about
0.1 micron or less.
Inventors: |
Tsai, Ming-Huan; (Hsinchu,
TW) ; Tao, Hun-Jan; (Hsinchu, TW) ; Wu, Tsang
Jiuh; (Taichung, TW) ; Hsu, Ju Wang; (Taipei,
TW) |
Correspondence
Address: |
GEORGE O. SAILE & ASSOCIATES
28 DAVIS AVENUE
POUGHKEEPSIE
NY
12603
US
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company
|
Family ID: |
32771022 |
Appl. No.: |
10/357579 |
Filed: |
February 4, 2003 |
Current U.S.
Class: |
438/710 ;
257/E21.252; 257/E21.256; 257/E21.257; 257/E21.577 |
Current CPC
Class: |
H01L 21/31144 20130101;
H01L 21/76802 20130101; H01L 21/31116 20130101; H01L 21/31138
20130101 |
Class at
Publication: |
438/710 |
International
Class: |
H01L 021/4763 |
Claims
What is claimed is:
1. A method for forming a patterned masking layer having the
desired pattern of areas on the top surface of a semiconductor
substrate using a multilevel resist structure comprising the steps
of: forming on the top surface of said semiconductor substrate an
inorganic ARC layer; forming an organic ARC layer over said
inorganic ARC layer; forming a resist layer over said organic ARC
layer, exposing the resist layer to the desired pattern, and
developing the resist layer to expose areas of said organic ARC
layer; and exposing the semiconductor substrate to a plasma etching
environment generated by RF or microwave power in a gaseous mixture
of a fluorine containing gas, such as C.sub.4F.sub.8,
C.sub.5F.sub.8, C.sub.4F.sub.6, CHF.sub.3 or similar species, an
inert gas, such as helium or argon, an optional weak oxidant, such
as CO or O.sub.2or similar species, and a nitrogen source, such as
N.sub.2, N.sub.2O, or NH.sub.3 or similar species, for a time
sufficient to etch through the organic ARC layer and the inorganic
ARC layer.
2. The method of claim 1, wherein said gaseous mixture comprises
C.sub.4F.sub.6, CF.sub.4, CHF.sub.3, O.sub.2 and argon.
3. The method of claim 2, wherein the volume ratios of gases,
C.sub.4F.sub.6, CF.sub.4, CHF.sub.3, O.sub.2 are about
1:10:3:4.
4. The method of claim 1, wherein said plasma etching environment
has a pressure between about 5 and 50 mTorr and said plasma is
generated by RF power between about 100 and 900 Watts, applied to
an upper electrode and RF power between about 900 and 2000 Watts,
applied to a lower electrode in a dual electrode etching tool.
5. The method of claim 1, wherein said inorganic ARC layer
comprises SiON and has a thickness between about 100 and 1000
Angstroms.
6. The method of claim 1, wherein said organic ARC layer has a
thickness between about 100 and 1000 Angstroms.
7. A method for forming a contact hole on a semiconductor substrate
comprising the steps of: providing a semiconductor substrate having
formed thereon a layer of first material and a second layer of
dielectric material formed on the top surface of the layer of first
material; providing a first ARC layer comprising an inorganic
material on the top surface of the second layer of dielectric
material; providing a second ARC layer comprising an organic
material on the top surface of the first ARC layer; providing a
patterned mask layer on the top surface of the second ARC layer,
wherein the patterned mask layer has holes therein, said holes
being open to the top surface of the second ARC layer; performing a
first anisotropic etching process in an RF or microwave generated
plasma to remove the second ARC layer comprising an organic
material and the first ARC layer comprising an inorganic material
at the sites of the holes in said patterned mask layer; continuing
said first anisotropic etching process in an RF or microwave
generated plasma to remove the second layer of dielectric material
at the sites of the holes in said patterned mask layer; performing
a second anisotropic etching process in an RF or microwave
generated plasma to remove the layer of first material at the sites
of etched holes in said second layer of dielectric material; and
performing a plasma stripping process to remove the remaining
patterned mask layer and the remaining second ARC layer comprising
an organic material.
8. The method of claim 7, wherein said layer of first material is a
dielectric, which acts as an etch stop when etching holes in said
second layer of dielectric material.
9. The method of claim 8, wherein said layer of first material is a
dielectric comprising silicon nitride.
10. The method of claim 7, wherein said second layer of dielectric
material formed on the top surface of the layer of first material
comprises silicon oxide, having a thickness between about 1000 and
20,000 Angstroms.
11. The method of claim 7, wherein said first anisotropic etching
process is performed in a plasma etching environment generated in a
gaseous mixture of a fluorine containing gas, such as
C.sub.4F.sub.8, C.sub.5F.sub.8, C.sub.4F.sub.6, CHF.sub.3 or
similar species, an inert gas, such as helium or argon, an optional
weak oxidant, such as CO or O.sub.2 or similar species, and a
nitrogen source, such as N.sub.2, N.sub.2O, or NH.sub.3 or similar
species, for a time sufficient to etch through the organic ARC
layer, the inorganic ARC layer and the second layer of dielectric
material.
12. The method of claim 11, wherein said gaseous mixture comprises
C.sub.4F.sub.6, CF.sub.4, CHF.sub.3, O.sub.2 and argon.
13. The method of claim 12, wherein the volume ratios of gases,
C.sub.4F.sub.6, CF.sub.4, CHF.sub.3, O.sub.2 are about
1:10:3:4.
14. The method of claim 7, wherein said first anisotropic etching
process is performed at a pressure between about 5 and 50 mTorr and
said plasma is generated by RF power between about 100 and 900
Watts, applied to an upper electrode and RF power between about 900
and 2000 Watts, applied to a lower electrode in a dual electrode
etching system.
15. The method of claim 7, wherein said inorganic ARC layer
comprises SiON and has a thickness between about 100 and 1000
Angstroms.
16. The method of claim 7, wherein said organic ARC layer has a
thickness between about 100 and 1000 Angstroms.
17. The method of claim 7, wherein said second anisotropic etching
process is performed in a plasma etching environment generated in a
gaseous mixture of C.sub.xF.sub.y/H.sub.2/Ar,
CH.sub.xF.sub.y/H.sub.2/Ar, CH.sub.xF.sub.y/N.sub.2/Ar,
C.sub.xF.sub.y/N.sub.2/Ar, C.sub.xF.sub.y/N.sub.2/H.sub.2/Ar,
CH.sub.xF.sub.y/N.sub.2/H.sub.2/Ar, CH.sub.xF.sub.y/O.sub.2/Ar or
CF.sub.x/O.sub.2/Ar for a time sufficient to etch through the layer
of first material at the sites of etched holes in said second layer
of dielectric material.
18. A method for forming a contact hole on a semiconductor
substrate comprising the steps of: providing a semiconductor
substrate having formed thereon a layer of first material and a
layer of dielectric material formed on the top surface of the layer
of first material; providing a bottom ARC layer comprising a
non-silicon containing organic material on the top surface of the
layer of dielectric material; providing a top ARC layer comprising
a silicon containing organic material on the top surface of the
bottom ARC layer comprising a non-silicon containing organic
material; providing a patterned mask layer on the top surface of
the top ARC layer, wherein the patterned mask layer has holes
therein, said holes being open to the top surface of the top ARC
layer; performing a first anisotropic etching process in an RF or
microwave generated plasma to remove the top ARC layer comprising a
non-silicon containing organic material at the sites of the holes
in said patterned mask layer; and continuing said first anisotropic
etching process in an RF or microwave generated plasma to remove
the bottom ARC layer of non-silicon containing organic material at
the sites of the holes in said patterned mask layer.
19. The method of claim 18, further comprising the steps of:
continuing the first anisotropic etching process in an RF or
microwave generated plasma to remove said layer of dielectric
material at the sites of the holes in said patterned mask layer,
said first anisotropic etching process simultaneously removing the
patterned mask layer on the top surface of the top ARC layer;
performing a second anisotropic etching process in an RF or
microwave generated plasma to remove the layer of first material at
the sites of etched holes in said layer of dielectric material; and
performing a plasma stripping process to remove the remaining
patterned mask layer and the remaining top ARC layer comprising a
silicon containing organic material and bottom ARC layer comprising
a non-silicon containing organic material.
20. The method of claim 18, wherein said layer of first material is
a dielectric.
21. The method of claim 18, wherein said layer of first material is
a dielectric comprising silicon nitride or SiON having a thickness
between about 100 and 1000 Angstroms.
22. The method of claim 18, wherein said layer of dielectric
material formed on the top surface of the layer of first material
comprises silicon oxide.
23. The method of claim 22, wherein said layer of first material
comprises silicon oxide having a thickness between about 1000 and
20,000 Angstroms.
24. The method of claim 18, wherein said bottom ARC layer
comprising a non-silicon containing organic material has a
thickness between about 1000 and 5000 Angstroms.
25. The method of claim 18, wherein said top ARC layer comprising a
silicon containing organic material has a thickness between about
500 and 3000 Angstroms.
26. The method of claim 18, wherein said first anisotropic etching
process is performed in a plasma etching environment generated in a
gaseous mixture of a fluorine containing gas, such as
C.sub.4F.sub.8, C.sub.5F.sub.8, C.sub.4F.sub.6or similar species,
an inert gas, such as helium or argon, an optional weak oxidant,
such as CO or O.sub.2 or similar species, and a nitrogen source,
such as N.sub.2, N.sub.2O, or NH.sub.3 or similar species, for a
time sufficient to etch through the top ARC layer and the bottom
ARC layer.
27. The method of claim 18, wherein said first anisotropic etching
process is performed at a pressure between about 10 and 300 mTorr
and said plasma is generated by RF power between about 300 and 5000
Watts, applied to an upper electrode and RF power between about 300
and 5000 Watts, applied to a lower electrode in a dual electrode
etching system.
28. The method of claim 19, wherein said second anisotropic etching
process is performed in a plasma etching environment generated in a
gaseous mixture of C.sub.xF.sub.y/H.sub.2/Ar,
CH.sub.xF.sub.y/H.sub.2/Ar, CH.sub.xF.sub.y/N.sub.2/Ar,
C.sub.xF.sub.y/N.sub.2/Ar, C.sub.xF.sub.y/N.sub.2/H.sub.2/Ar,
CH.sub.xF.sub.y/N.sub.2/H.sub.2/Ar, CH.sub.xF.sub.y/O.sub.2/Ar or
CF.sub.x/O.sub.2/Ar for a time sufficient to etch through the layer
of first material at the sites of etched holes in said second layer
of dielectric material.
Description
BACKGROUND OF THE INVENTION
[0001] (1) Field of the Invention
[0002] This invention relates to a method of fabricating integrated
circuits and other electronic devices on semiconductor substrates.
More particularly, the invention relates to an improved process for
forming contact holes on semiconductor substrates.
[0003] (2) Description of Related Art
[0004] In the fabrication of semiconductor integrated circuits
multilevel integration structures are used to connect the various
devices in the circuits. As circuit density increases very large
scale integration (VLSI) and ultra-large scale integration (ULSI)
are used to interconnect the devices in integrated circuits
fabricated on semiconductor substrates and the feature sizes of
device components have decreased to 0.1 micron and less. This is
particularly true for the contact holes required to connect devices
between levels in multilevel structures. Therefore, fabrication
processes for achieving VLSI and ULSI levels of integration must be
capable of reliably forming contact holes between successive
levels, where the contact holes have dimensions of the order of 0.1
micron or less in diameter.
[0005] An important challenge in the fabrication of multilevel
integrated circuits on semiconductor substrates is to develop
masking and etching technologies which allow reliable formation of
semiconductor devices, interconnection conducting patterns, and
interlevel contact holes which have dimensions of 0.1 micron on
less. The masking technologies and the etching technologies must be
compatible and result in high fabrication process yield and minimum
process cost. In order to minimize cost, fabrication tool
throughput must be maximized. Therefore, sequential processing in
the same fabrication tool, without necessity to transfer to
additional tools, is desirable and leads to reduced product
cost.
[0006] As device feature size is reduced to 0.1 micron and less,
the ability to achieve good image resolution in high density, small
pitch patterns requires that the photo resist exposure and imaging
processes be performed on a thin photo resist imaging layer.
However, when etching features in thick layers, such as ILD
(Inter-Level Dielectric) layers, thin photo resist masks are
inadequate and schemes to provide more robust masking layers are
required.
[0007] Numerous patents disclose bi-level resist masking structures
in order to achieve greater dimensional fidelity in the desired
integration pattern. For example, U.S. Pat. No. 5,227,280 entitled
"Resists With Enhanced Sensitivity And Contrast" granted Jul. 13,
1993 to James A. Jubinsky et al. describes a bi-level resist
structure and method of fabrication. The method forms a bi-level
resist structure for use in lift-off processes wherein the
underlayer comprises a photo resist layer with an admixture of
cyclic anhydrides and the top layer comprises a photo resist
layer.
[0008] Also, U.S. Pat. No. 5,286,607 entitled "Bi-Layer Resist
Process For Semiconductor Processing" granted Feb. 15, 1994 to
Andrew V. Brown shows a method of forming a resist mask on a
substrate in which a planarizing polymer layer is first formed on
the substrate. Then the planarizing polymer layer is exposed to a
silicon containing medium, so as to cause silicon from the medium
to penetrate the top portion of the planarizing polymer layer. Next
a resist layer is formed over the first layer, exposed and
developed to form a pattern and then RIE is used to remove the
exposed areas of the first layer including the silicon that
penetrated the first layer. Finally RIE in an oxygen plasma removes
the resist layer while etching through the planarizing polymer in
the exposed areas.
[0009] And, U.S. Pat. No. 5,545,512 entitled "Method Of Forming A
Pattern Of Silylated Planarizing Photoresist" granted Aug. 13, 1996
to Tatsuo Nakato describes a multilayer photo resist process,
wherein a mask pattern of silicon dioxide is formed on the surface
of a layer of photo resist. The steps in the method include
irradiating the surface of a photo resist layer to create a
unpatterned silicon-reactive region adjacent to the surface of the
photo resist. The next step is to soft bake the irradiated photo
resist in a silicon containing environment to convert the
silicon-reactive region to a silicon-enriched region adjacent to
the surface of the photo resist. A patterned layer of photo resist
is then formed overlying the silicon-enriched region and an etching
step transfers the mask pattern to the silicon-enriched region of
the photo resist. The remaining areas of the silicon-enriched layer
are exposed to an oxygen plasma which converts the silicon-enriched
areas to silicon dioxide.
[0010] Also, U.S. Pat. No. 5,427,649 entitled "Method For Forming A
Pattern By Silylation" granted Jun. 27, 1995 to Cheol-hong Kim et
al. describes a method for forming a mask pattern by forming a
first photo resist layer having a silylated surface. Then, a second
photo resist layer is formed on the silylation layer, which is then
exposed and developed to form a pattern in the second photo resist
layer. The pattern in the second photo resist layer is used to etch
a pattern in the silylated first photo resist layer. The silylation
pattern is then oxidized. Next, the first photo resist layer is
etched using the oxidized silylation pattern as a mask.
[0011] Also, U.S. Pat. No. 6,218,292 B1 entitled "Dual Layer Bottom
Anti-Reflective Coating" granted Apr. 17, 2001 to David K. Foote
describes a method of manufacturing a semiconductor device wherein
a first anti-reflective coating is deposited on a substrate
followed by depositing a second anti-reflective coating on the
first anti-reflective coating.
[0012] Also, U.S. Pat. No. 6,057,587 entitled "Semiconductor Device
With Anti-Reflective Structure" granted May 2, 2000 to Kouros
Ghandehari et al. reveals an anti-reflective structure for use in
patterning metal layers on semiconductor substrates.
[0013] Also, U.S. Pat. No. 6,037,276 entitled "Method For Improving
Patterning Of A Conductive Layer In An Integrated Circuit" granted
Mar. 14, 2000 to HuaTai Lin et al. shows a lithographic patterning
process on a conductive layer wherein an oxynitride layer is formed
on the conductive layer, a nitride layer is formed on the
oxynitride layer, and a photoresist layer is formed on the nitride
layer.
[0014] Further, U.S. Pat. No. 6,147,007 entitled "Method For
Forming A Contact Hole on a Semiconductor Wafer" granted Nov. 14,
2000 to Chan-Lon Yang et al. describes a process for etching a
contact hole in silicon oxide using a patterned photo resist layer
as a mask. A silicon nitride layer is used as an etch stop when
etching through a silicon oxide layer.
[0015] When circuit density requires that contact holes be of the
order of 0.1 micron or less in diameter, resist masking schemes
which use a single organic ARC (anti-reflection coating) layer or a
single inorganic ARC layer are not adequate. Such single layer ARC
schemes result in irregularly shaped etched holes having severe
striations which can then contribute to shorting between adjacent
contact holes.
[0016] Also, when using a bi-level resist structure, comprising a
top imaging layer and a bottom dry developed organic layer, as the
mask for plasma etching holes in silicon oxide using conventional
gaseous mixtures of C.sub.xF.sub.y, argon, and O.sub.2 the top
imaging layer is not removed by the silicon oxide etch process and
a residue forms on the top of the top imaging layer during the
etching of the silicon oxide. This residue further impacts the
successful removal of the top imaging layer by subsequent O.sub.2
ashing processes and degrades the fabrication process yield.
[0017] The present invention is directed to an improved method of
etching very small contact holes through dielectric layers used to
separate patterned conducting layers in multilevel integrated
circuits formed on semiconductor substrates. The method uses
bi-level ARC coatings in the resist structure and a unique
combination of gaseous components in a plasma etching process which
can be used to dry develop the bi-level resist mask as well as etch
through a silicon oxide dielectric layer. Contact holes formed
using this improved method may be used to make contact to active
devices formed within the semiconductor substrate or the contact
holes may be used to make contact between successive layers in
multilevel integrated circuit structures.
SUMMARY OF THE INVENTION
[0018] It is a general object of the present invention to provide
an improved method for forming a patterned masking layer on the top
surface of a semiconductor substrate using a multilevel resist
structure.
[0019] A more specific object of the present invention is to
provide an improved method of forming contact holes through
dielectric layers on a semiconductor substrate, where the contact
holes have a diameter of about 0.1 micron or less.
[0020] Another object of the present invention is to provide an
improved, high yield method of forming contact holes through a
dielectric layer on a semiconductor substrate, where the contact
holes have a diameter of about 0.1 micron.
[0021] And, yet another object of the present invention is to
provide an improved method of forming contact holes through a
dielectric layer on a semiconductor substrate where the fabrication
process uses the same plasma etching tool to dry develop the image
in the resist mask and to sequentially etch the holes in the
dielectric layer.
[0022] In accordance with the present invention, the above and
other objectives are realized by using a method of forming a
patterned masking layer having the desired pattern of areas on the
top surface of a semiconductor substrate using a multilevel resist
structure comprising the steps of: forming on the top surface of
the semiconductor substrate an inorganic ARC layer; forming an
organic ARC layer over the inorganic ARC layer; forming a resist
layer over the organic ARC layer, exposing the resist layer to the
desired pattern, and developing the resist layer to expose areas of
the organic ARC layer; and exposing the semiconductor substrate to
a plasma etching environment generated by RF or microwave power in
a gaseous mixture of a fluorine containing gas, such as
C.sub.4F.sub.8, C.sub.5F.sub.8, C.sub.4F.sub.6, CHF.sub.3 or
similar species, an inert gas, such as helium or argon, an optional
weak oxidant, such as CO or O.sub.2 or similar species, and a
nitrogen source, such as N.sub.2, N.sub.2O, or NH.sub.3 or similar
species, for a time sufficient to etch through the organic ARC
layer and the inorganic ARC layer.
[0023] In a second embodiment of the present invention, the above
and other objectives are realized by using a method of forming a
contact hole on a semiconductor substrate comprising the steps of:
providing a semiconductor substrate having formed thereon a layer
of first material and a second layer of dielectric material formed
on the top surface of the layer of first material; providing a
first ARC layer comprising an inorganic material on the top surface
of the second layer of dielectric material; providing a second ARC
layer comprising an organic material on the top surface of the
first ARC layer; providing a patterned mask layer on the top
surface of the second ARC layer, wherein the patterned mask layer
has holes therein, said holes being open to the top surface of the
second ARC layer; performing a first anisotropic etching process in
an RF or microwave generated plasma to remove the second ARC layer
comprising an organic material and the first ARC layer comprising
an inorganic material at the sites of the holes in said patterned
mask layer; continuing said first anisotropic etching process in an
RF or microwave generated plasma to remove the second layer of
dielectric material at the sites of the holes in the patterned mask
layer; performing a second anisotropic etching process in an RF or
microwave generated plasma to remove the layer of first material at
the sites of etched holes in said second layer of dielectric
material; and performing a plasma stripping process to remove the
remaining patterned mask layer and the remaining second ARC layer
comprising an organic material.
[0024] In a third embodiment of the present invention, the above
and other objectives are realized by using a method of forming a
contact hole on a semiconductor substrate comprising the steps of:
providing a semiconductor substrate having formed thereon a layer
of first material and a layer of dielectric material formed on the
top surface of the layer of first material; providing a bottom ARC
layer comprising a non-silicon containing organic material on the
top surface of the layer of dielectric material; providing a top
ARC layer comprising a silicon containing organic material on the
top surface of the bottom ARC layer comprising a non-silicon
containing organic material; providing a patterned mask layer on
the top surface of the top ARC layer, wherein the patterned mask
layer has holes therein, said holes being open to the top surface
of the top ARC layer; performing a first anisotropic etching
process in an RF or microwave generated plasma to remove the top
ARC layer comprising a non-silicon containing organic material at
the sites of the holes in said patterned mask layer; continuing
said first anisotropic etching process in an RF or microwave
generated plasma to remove the bottom ARC layer of non-silicon
containing organic material at the sites of the holes in said
patterned mask layer; and further comprising the steps of:
continuing the first anisotropic etching process in an RF or
microwave generated plasma to remove said layer of dielectric
material at the sites of the holes in said patterned mask layer,
said first anisotropic etching process simultaneously removing the
patterned mask layer on the top surface of the top ARC layer;
performing a second anisotropic etching process in an RF or
microwave generated plasma to remove the layer of first material at
the sites of etched holes in said layer of dielectric material; and
performing a plasma stripping process to remove the remaining
patterned mask layer and the remaining top ARC layer comprising a
silicon containing organic material and bottom ARC layer comprising
a non-silicon containing organic material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The object and other advantages of this invention are best
described in the preferred embodiments with reference to the
attached drawings that include:
[0026] FIGS. 1A and 1B, which in cross-sectional representation
illustrate the method of one embodiment of the present
invention.
[0027] FIGS. 2A-2E, which in cross-sectional representation
illustrate the method of a second embodiment of the present
invention.
[0028] FIGS. 3A-3D, which in cross-sectional representation
illustrate the method of a third embodiment of the present
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0029] The new and improved method of forming a patterned masking
layer on the top surface of a semiconductor substrate using a
multilevel resist structure and the method of forming contact holes
through dielectric layers on a semiconductor substrate, where the
contact holes have a diameter of about 0.1 micron or less will now
be described in detail.
[0030] Please refer to FIGS. 1A and 1B, which in cross-sectional
representation illustrate the method of one embodiment of the
present invention. Referring to FIG. 1A, a semiconductor substrate
10 is provided and the semiconductor substrate 10 comprises
isolation areas 11, which may contain an active area 12 and a
dielectric layer 13. The isolation areas 11 may be silicon oxide or
other dielectrics. The active area 12 may comprise titanium
silicide or other silicides. The dielectric layer 13 may be silicon
oxide or other suitable insulating materials. Formed on the top
surface of the semiconductor substrate is an inorganic ARC layer
14. Inorganic ARC layer 14 comprises SiON and has a thickness
between about 100 and 1000 Angstroms. Next, an organic ARC layer 15
is formed over the inorganic ARC layer 14. The organic ARC layer 15
has a thickness between about 100 and 1000 Angstroms. Layer 16 is a
patterned resist layer formed over the organic ARC layer 15.
Conventional exposure and development processes are used to form
the desired pattern in the resist layer and to form holes in the
resist layer at sites where contacts are to be made on the
semiconductor substrate. Illustrated is one such hole 17, which
exposes the underlying organic ARC layer 15.
[0031] Now referring to FIG. 1B, the semiconductor substrate having
thereon the structure illustrated in FIG. 1A is loaded into a
plasma etch tool and exposed to a plasma etching environment
generated by RF or microwave power in a gaseous mixture of a
fluorine containing gas, such as C.sub.4F.sub.8, C.sub.5F.sub.8,
C.sub.4F.sub.6, CHF.sub.3 or similar species, an inert gas, such as
helium or argon, an optional weak oxidant, such as CO or O.sub.2 or
similar species, and a nitrogen source, such as N.sub.2, N.sub.2O,
or NH.sub.3 or similar species, for a time sufficient to etch
through the organic ARC layer 15 and the inorganic ARC layer 14. A
plasma generated in a gaseous mixture comprising C.sub.4F.sub.6,
CF.sub.4, CHF.sub.3, O.sub.2 and argon, where the volume ratios of
gases, C.sub.4F.sub.6, CF.sub.4, CHF.sub.3, O.sub.2 are about
1:10:3:3, has been used to etch through both the organic ARC layer
15 and the inorganic ARC layer 14. The plasma etching environment
has a pressure between about 5 and 50 mTorr and the plasma is
generated by RF power between about 100 and 900 Watts, applied to
an upper electrode and RF power between about 900 and 2000 Watts,
applied to a lower electrode in a dual electrode plasma etch
tool.
[0032] FIGS. 2A-2D illustrate in cross-sectional representation the
method of a second embodiment of the present invention. Referring
to FIG. 2A, semiconductor substrate 20 has a layer of first
material 21 formed thereon. A second layer of dielectric material
22 is formed on the top surface of the layer of first material 21.
Semiconductor substrate 20 may be silicon, germanium or other such
semiconductors. The layer of first material 21 is a dielectric,
such as silicon nitride or SiON having a thickness between about
100 and 1000 Angstroms. The layer of first material 21 acts as an
etch stop when etching holes in the second layer of dielectric
material 22, which comprises silicon oxide having a thickness
between about 3000 and 10,000 Angstroms. Formed on the top surface
of second layer of dielectric material 22 is a first inorganic ARC
layer 24, which comprises SiON and has a thickness between about
100 and 1000 Angstroms. Next, an organic ARC layer 25 is formed
over the inorganic ARC layer 24. The organic ARC layer 25 has a
thickness between about 100 and 1000 Angstroms. Layer 26 is a
patterned resist layer formed over the organic ARC layer 25.
Conventional exposure and development processes are used to form
the desired pattern in the resist layer and to form holes in the
resist layer at sites where contacts are to be made on the
semiconductor substrate. Illustrated is one such hole 27, which
exposes the underlying organic ARC layer 25.
[0033] Now referring to FIG. 2B, the semiconductor substrate having
thereon the structure illustrated in FIG. 2A is loaded into a
plasma etch tool and exposed to a first anisotropic etching process
in a plasma etching environment generated by RF or microwave power
in a gaseous mixture of a fluorine containing gas, such as
C.sub.4F.sub.8, C.sub.5F.sub.8, C.sub.4F.sub.6, CHF.sub.3 or
similar species, an inert gas, such as helium or argon, an optional
weak oxidant, such as CO or O.sub.2 or similar species, and a
nitrogen source, such as N.sub.2, N.sub.2O or NH.sub.3 or similar
species, for a time sufficient to etch through the organic ARC
layer 25 and the inorganic ARC layer 24. A plasma generated in a
gaseous mixture comprising C.sub.4F.sub.6, CF.sub.4, CHF.sub.3,
O.sub.2 and argon, where the volume ratios of gases,
C.sub.4F.sub.6, CF.sub.4, CHF.sub.3, O.sub.2 are about 1:10:3:4,
has been used to etch through both the organic ARC layer 25 and the
inorganic ARC layer 24. The plasma etching environment has a
pressure between about 5 and 50 mTorr and the plasma is generated
by RF power between about 100 and 900 Watts, applied to an upper
electrode and RF power between about 900 and 2000 Watts, applied to
a lower electrode in a dual electrode plasma etch tool.
[0034] The next step is to continue the first anisotropic etching
process, as illustrated in FIG. 2C, to remove the second layer of
dielectric material 22 at the site of hole 27. The same plasma etch
tool is used and the same gaseous components and etch process
parameters as stated above are used for this continuation of the
first anisotropic etching process.
[0035] Now referring to FIG. 2D, a second anisotropic etching
process is used to remove the layer of first material 21 at the
site of hole 27. This second anisotropic etching process is
performed in a plasma etching environment in a gaseous mixture of
CF.sub.x/H.sub.2/Ar, CH.sub.xF.sub.y/H.sub.2/Ar,
CH.sub.xF.sub.y/N.sub.2/Ar, CH.sub.xF.sub.y/N.sub.2/H.sub.2/Ar,
CH.sub.xF.sub.y/O.sub.2/Ar or CF.sub.x/O.sub.2/Ar for a time
sufficient to etch through the layer of first material 21 at the
site of hole 27.
[0036] As illustrated in FIGS. 2D and 2E, a plasma stripping
process is next used to remove the remaining patterned mask layer
26 and the remaining second ARC layer 25 comprising an organic
material to result in the structure as shown in FIG. 2E.
[0037] Another method for forming a contact hole on a semiconductor
substrate is illustrated in FIGS. 3A-3D. Referring to FIG. 3A, a
semiconductor substrate 30 is provided, having thereon a layer of
first material 31, comprising a dielectric, such as silicon nitride
or SiON having a thickness between about 100 and 1000 Angstroms.
Semiconductor substrate 30 may be silicon, germanium or other such
semiconductors. The layer of first material 31 acts as an etch stop
when etching holes in the second layer of dielectric material 32,
which comprises silicon oxide having a thickness between about 1000
and 20,000 Angstroms. Formed on the top surface of second layer of
dielectric material 32 is a bottom ARC layer 33, which comprises a
non-silicon containing organic material and has a thickness between
about 1000 and 5000 Angstroms. Formed on top of bottom ARC layer 33
is top ARC layer 34, which comprises a silicon containing organic
material having a thickness between about 500 to 3000 Angstroms.
Layer 35 is a patterned resist layer formed over the top ARC layer
34. Conventional exposure and development processes are used to
form the desired pattern in the resist layer and to form holes in
the resist layer at sites where contacts are to be made on the
semiconductor substrate. Illustrated is one such hole 36, which
exposes the underlying top ARC layer 34.
[0038] Now referring to FIG. 3B, the semiconductor substrate having
thereon the structure illustrated in FIG. 3A is loaded into a
plasma etch tool and exposed to a first anisotropic etching process
in a plasma etching environment generated by RF or microwave power
in a gaseous mixture of a fluorine containing gas, such as
C.sub.4F.sub.8, C.sub.5F.sub.8, C.sub.4F.sub.6 CHF.sub.3 or similar
species, an inert gas, such as helium or argon, an optional weak
oxidant, such as CO or O.sub.2 or similar species, and a nitrogen
source, such as N.sub.2, N.sub.2O or NH.sub.3 or similar species
for a time sufficient to etch through the top ARC layer 34 and the
bottom ARC layer 33. A plasma generated in a gaseous mixture
comprising C.sub.4F.sub.6, CF.sub.4, CHF.sub.3, O.sub.2 and argon,
where the volume ratios of gases, C.sub.4F.sub.6, CF.sub.4,
CHF.sub.3, O.sub.2 are about 1:10:3:4, has been used to etch
through top ARC layer 34 and bottom ARC layer 33. The plasma
etching environment has a pressure between about 5 and 50 mTorr and
the plasma is generated by RF power between about 100 and 900
Watts, applied to an upper electrode and RF power between about 900
and 2000 Watts, applied to a lower electrode in a dual electrode
plasma etch tool.
[0039] The next step is to continue the first anisotropic etching
process, as illustrated in FIG. 3C, to remove the layer of
dielectric material 32 at the site of hole 36. The same plasma etch
tool is used and the same gaseous components and etch process
parameters as stated above are used for this continuation of the
first anisotropic etching process. At the same time patterned
resist layer 35 is removed from the top surface of top ARC layer
34.
[0040] Now referring to FIG. 3D, a second anisotropic etching
process is used to remove the layer of first material 31 at the
site of hole 35. This second anisotropic etching process is
performed in a plasma etching environment in a gaseous mixture of
CF.sub.x/H.sub.2/Ar, CH.sub.xF.sub.y/H.sub.2/Ar,
CH.sub.xF.sub.y/N.sub.2/Ar, CH.sub.xF.sub.y/N.sub.2/H.sub.2/Ar,
CH.sub.xF.sub.y/O.sub.2/Ar or CF.sub.x/O.sub.2/Ar for a time
sufficient to etch through the layer of first material 31 at the
site of hole 36. At the same time the remaining ARC layers 33 and
34 are removed from the surface of the layer of dielectric material
32 resulting in the structure illustrated in FIG. 3D.
[0041] A plasma stripping process may then be used to remove any
remaining organic material from the surface of the structure
illustrated in FIG. 3D.
[0042] While the invention has been particularly shown and
described with reference to the preferred embodiments thereof, it
will be understood by those skilled in the art that various changes
in form and details may be made without departing from the spirit
and scope of the invention.
* * * * *