Hsu; Ju-Wang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Hsu; Ju-Wang.The latest application filed is for "method for manufacturing semiconductor structure".

Company Profile

2.28.30

Hsu; Ju-Wang - Taipei TW
HSU; Ju-Wang - Taipei City TW
Hsu; Ju-Wang - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for manufacturing semiconductor structure Grant 11,355,642 - Hsu , et al. June 7, 2	2022-06-07
Method For Manufacturing Semiconductor Structure App 20200052122 - HSU; Ju-Wang ; et al.	2020-02-13
Fin field effect transistor and method of forming the same Grant 10,483,397 - Hsu , et al. Nov	2019-11-19
Fin Field Effect Transistor And Method Of Forming The Same App 20150137265 - HSU; Ju-Wang ; et al.	2015-05-21
Fin field effect transistor and method of forming the same Grant 8,927,353 - Hsu , et al. January 6, 2	2015-01-06
Method of fabricating gate structures Grant 8,030,214 - Wu , et al. October 4, 2	2011-10-04
Method Of Fabricating Gate Structures App 20110207315 - WU; Pochi ; et al.	2011-08-25
Contact hole structures and contact structures and fabrication methods thereof Grant 7,875,547 - Hsu , et al. January 25, 2	2011-01-25
Spacer layer etch method providing enhanced microelectronic device performance Grant 7,678,655 - Su , et al. March 16, 2	2010-03-16
Fin Filled Effect Transistor And Method Of Forming The Same App 20080277745 - Hsu; Ju-Wang ; et al.	2008-11-13
Method and structure for a 1T-RAM bit cell and macro Grant 7,425,740 - Liu , et al. September 16, 2	2008-09-16
Measuring low dielectric constant film properties during processing Grant 7,400,401 - Tsai , et al. July 15, 2	2008-07-15
Poly Silicon Hard Mask App 20080122107 - Tsai; Jang-Shiang ; et al.	2008-05-29
CMOS devices with improved gap-filling Grant 7,378,308 - Hsu , et al. May 27, 2	2008-05-27
Alternative interconnect structure for semiconductor devices Grant 7,341,935 - Hsu , et al. March 11, 2	2008-03-11
Spacer layer etch method providing enhanced microelectronic device performance App 20080026518 - Su; Hung Der ; et al.	2008-01-31
Method for forming high selectivity protection layer on semiconductor device Grant 7,316,970 - Chen , et al. January 8, 2	2008-01-08
CMOS devices with improved gap-filling App 20070235823 - Hsu; Ju-Wang ; et al.	2007-10-11
Multiple gate field effect transistor structure Grant 7,271,448 - Hsu , et al. September 18, 2	2007-09-18
Bi-level resist structure and fabrication method for contact holes on semiconductor substrates Grant 7,265,060 - Tsai , et al. September 4, 2	2007-09-04
Semiconductor device and method of making the same Grant 7,259,050 - Chen , et al. August 21, 2	2007-08-21
Method of forming contact plug on silicide structure Grant 7,256,137 - Wu , et al. August 14, 2	2007-08-14
Resistance-reduced semiconductor device and methods for fabricating the same Grant 7,256,498 - Huang , et al. August 14, 2	2007-08-14
Self-aligned double gate device and method for forming same Grant 7,230,270 - Chen , et al. June 12, 2	2007-06-12
Method for forming integrated advanced semiconductor device using sacrificial stress layer Grant 7,223,647 - Hsu , et al. May 29, 2	2007-05-29
Method and structure for a 1T-RAM bit cell and macro App 20070080387 - Liu; Sheng-Da ; et al.	2007-04-12
Transistor with high dielectric constant gate and method for forming the same Grant 7,179,701 - Hsu , et al. February 20, 2	2007-02-20
Method for selectively stressing MOSFETs to improve charge carrier mobility App 20060223255 - Chen; Chien-Hao ; et al.	2006-10-05
Measuring low dielectric constant film properties during processing App 20060220653 - Tsai; Jang-Shiang ; et al.	2006-10-05
Multiple gate field effect transistor structure App 20060180854 - Hsu; Ju-Wang ; et al.	2006-08-17
Method For Selectively Stressing Mosfets To Improve Charge Carrier Mobility App 20060183279 - Chen; Chien-Hao ; et al.	2006-08-17
Contact hole structures and contact structures and fabrication methods thereof App 20060154478 - Hsu; Ju-Wang ; et al.	2006-07-13
Geometrically optimized spacer to improve device performance App 20060148157 - Tao; Hun-Jan ; et al.	2006-07-06
Method for selectively stressing MOSFETs to improve charge carrier mobility Grant 7,052,946 - Chen , et al. May 30, 2	2006-05-30
Self-aligned double gate device and method for forming same App 20060108644 - Chen; Hao-Yu ; et al.	2006-05-25
Method for forming integrated advanced semiconductor device using sacrificial stress layer App 20060099745 - Hsu; Ju-Wang ; et al.	2006-05-11
Transistor with high dielectric constant gate and method for forming the same App 20060063322 - Hsu; Ju-Wang ; et al.	2006-03-23
Plasma treatment and etching process for ultra-thin dielectric films Grant 7,008,878 - Hsu , et al. March 7, 2	2006-03-07
Method for forming a resist protect layer App 20060014396 - Chen; Chien-Hao ; et al.	2006-01-19
Alternative interconnect structure for semiconductor devices App 20050285268 - Hsu, Ju-Wang ; et al.	2005-12-29
Resistance-reduced semiconductor device and methods for fabricating the same App 20050258499 - Huang, Yi-Chun ; et al.	2005-11-24
Semiconductor device and method of making the same App 20050242376 - Chen, Chien-Hao ; et al.	2005-11-03
Resistance-reduced semiconductor device and fabrication thereof App 20050212058 - Huang, Yi-Chun ; et al.	2005-09-29
Method for selectively stressing MOSFETs to improve charge carrier mobility App 20050199958 - Chen, Chien-Hao ; et al.	2005-09-15
Method of forming contact plug on silicide structure App 20050158986 - Wu, Chii-Ming ; et al.	2005-07-21
Plasma treatment and etching process for ultra-thin dielectric films App 20050136680 - Hsu, Ju-Wang ; et al.	2005-06-23
Method of forming contact plug on silicide structure Grant 6,884,736 - Wu , et al. April 26, 2	2005-04-26
Methods for improving sheet resistance of silicide layer after removal of etch stop layer Grant 6,838,381 - Hsu , et al. January 4, 2	2005-01-04
Bi-level resist structure and fabrication method for contact holes on semiconductor substrates App 20040248414 - Tsai, Ming-Huan ; et al.	2004-12-09
Bi-layer photoresist method for forming high resolution semiconductor features Grant 6,787,455 - Tsai , et al. September 7, 2	2004-09-07
Bi-level resist structure and fabrication method for contact holes on semiconductor substrates Grant 6,780,782 - Tsai , et al. August 24, 2	2004-08-24
Bi-level Resist Structure And Fabrication Method For Contact Holes On Semiconductor Substrates App 20040152328 - Tsai, Ming-Huan ; et al.	2004-08-05
Methods for improving sheet resistance of silicide layer after removal of etch stop layer App 20040127026 - Hsu, Peng-Fu ; et al.	2004-07-01
Method of forming contact plug on silicide structure App 20040067635 - Wu, Chii-Ming ; et al.	2004-04-08
Metal silicide etch resistant plasma etch method Grant 6,706,640 - Tsai , et al. March 16, 2	2004-03-16
Bi-layer photoresist method for forming high resolution semiconductor features App 20030119330 - Tsai, Ming-Huan ; et al.	2003-06-26
Integrated approach for controlling top dielectric loss during spacer etching Grant 6,498,067 - Perng , et al. December 24, 2	2002-12-24

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.